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build: Replace "$(shell $(DEFINE) $(CC) ...)" with $(DEFINE_PREFIX)

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to unify the way to define macros in Makefile

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This commit is contained in:
Xiang Xiao 2023-06-22 23:50:01 +08:00 committed by Petro Karashchenko
parent 7986f66006
commit a2f01f5e64
1 changed files with 2 additions and 2 deletions
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4
Application.mk
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@ -205,8 +205,8 @@ MAINNAME := $(addsuffix _main,$(PROGNAME))
$(MAINCXXOBJ): %$(CXXEXT)$(SUFFIX)$(OBJEXT): %$(CXXEXT)
$(eval MAIN=$(word $(call GETINDEX,$<,$(MAINCXXSRCS)),$(MAINNAME)))
$(eval $<_CXXFLAGS += ${shell $(DEFINE) "$(CXX)" main=$(MAIN)})
$(eval $<_CXXELFFLAGS += ${shell $(DEFINE) "$(CXX)" main=$(MAIN)})
$(eval $<_CXXFLAGS += ${DEFINE_PREFIX}main=$(MAIN))
$(eval $<_CXXELFFLAGS += ${DEFINE_PREFIX}main=$(MAIN))
$(if $(and $(CONFIG_BUILD_LOADABLE),$(CXXELFFLAGS)), \
$(call ELFCOMPILEXX, $<, $@), $(call COMPILEXX, $<, $@))