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nuttx/arch/risc-v/include/arch.h

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Add support for the RISC-V architecture and configs/nr5m100-nexys4 board. I will be making the FPGA code for this available soon (within a week I would say). The board support on this is pretty thin, but it seems like maybe a good idea to get the base RISC-V stuff in since there are people interested in it.
2016-10-16 17:47:07 +02:00
/****************************************************************************
* arch/risc-v/include/arch.h
*
NuttX: Ken Pettit: update licenses to Apache Ken Pettit has submitted the ICLA and we can migrate the licenses to Apache. Sebastien Lorquet has submitted the ICLA and we can migrate the licenses to Apache. Gregory Nutt has submitted the SGA and we can migrate the licenses to Apache. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-04-10 08:50:57 +02:00
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
Add support for the RISC-V architecture and configs/nr5m100-nexys4 board. I will be making the FPGA code for this available soon (within a week I would say). The board support on this is pretty thin, but it seems like maybe a good idea to get the base RISC-V stuff in since there are people interested in it.
2016-10-16 17:47:07 +02:00
*
NuttX: Ken Pettit: update licenses to Apache Ken Pettit has submitted the ICLA and we can migrate the licenses to Apache. Sebastien Lorquet has submitted the ICLA and we can migrate the licenses to Apache. Gregory Nutt has submitted the SGA and we can migrate the licenses to Apache. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-04-10 08:50:57 +02:00
* http://www.apache.org/licenses/LICENSE-2.0
Add support for the RISC-V architecture and configs/nr5m100-nexys4 board. I will be making the FPGA code for this available soon (within a week I would say). The board support on this is pretty thin, but it seems like maybe a good idea to get the base RISC-V stuff in since there are people interested in it.
2016-10-16 17:47:07 +02:00
*
NuttX: Ken Pettit: update licenses to Apache Ken Pettit has submitted the ICLA and we can migrate the licenses to Apache. Sebastien Lorquet has submitted the ICLA and we can migrate the licenses to Apache. Gregory Nutt has submitted the SGA and we can migrate the licenses to Apache. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-04-10 08:50:57 +02:00
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
Add support for the RISC-V architecture and configs/nr5m100-nexys4 board. I will be making the FPGA code for this available soon (within a week I would say). The board support on this is pretty thin, but it seems like maybe a good idea to get the base RISC-V stuff in since there are people interested in it.
2016-10-16 17:47:07 +02:00
*
****************************************************************************/
arch: Fix included directed -> included directly This typo had been copied and pasted into numerous irq and syscall headers.
2020-04-05 23:00:04 +02:00
/* This file should never be included directly but, rather,
Add support for the RISC-V architecture and configs/nr5m100-nexys4 board. I will be making the FPGA code for this available soon (within a week I would say). The board support on this is pretty thin, but it seems like maybe a good idea to get the base RISC-V stuff in since there are people interested in it.
2016-10-16 17:47:07 +02:00
* only indirectly through nuttx/arch.h
*/
#ifndef __ARCH_RISCV_INCLUDE_ARCH_H
#define __ARCH_RISCV_INCLUDE_ARCH_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
RISC-V: Initial support for CONFIG_BUILD_KERNEL This implements initial support for kernel build (address environments, page allocator) for RISC-V. This is done a bit differently compared to the ARMV7 implementation: - Support implemented for Sv39 MMU, however the implementation should be extensible for other MMU types also. - Instead of preserving and moving the L1 references around, a canonical approach is used instead, where the page table base address register is switched upon context switch. - To preserve a bit of memory, only a single L1/L2 table is supported, this gives access to 1GiB of virtual memory for each process, which should be more than enough. Some things worth noting: - Assumes page pool is mapped with vaddr=paddr mappings - The CONFIG_ARCH_XXXX_VBASE and CONFIG_ARCH_XXXX_NPAGES values are ignored, with the exception of CONFIG_ARCH_DATA_VBASE which is used for ARCH_DATA_RESERVE - ARCH_DATA_RESERVE is placed at the beginning of the userspace task's address environment
2022-03-11 12:35:39 +01:00
# include <stddef.h>
Add support for the RISC-V architecture and configs/nr5m100-nexys4 board. I will be making the FPGA code for this available soon (within a week I would say). The board support on this is pretty thin, but it seems like maybe a good idea to get the base RISC-V stuff in since there are people interested in it.
2016-10-16 17:47:07 +02:00
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
RISC-V: Initial support for CONFIG_BUILD_KERNEL This implements initial support for kernel build (address environments, page allocator) for RISC-V. This is done a bit differently compared to the ARMV7 implementation: - Support implemented for Sv39 MMU, however the implementation should be extensible for other MMU types also. - Instead of preserving and moving the L1 references around, a canonical approach is used instead, where the page table base address register is switched upon context switch. - To preserve a bit of memory, only a single L1/L2 table is supported, this gives access to 1GiB of virtual memory for each process, which should be more than enough. Some things worth noting: - Assumes page pool is mapped with vaddr=paddr mappings - The CONFIG_ARCH_XXXX_VBASE and CONFIG_ARCH_XXXX_NPAGES values are ignored, with the exception of CONFIG_ARCH_DATA_VBASE which is used for ARCH_DATA_RESERVE - ARCH_DATA_RESERVE is placed at the beginning of the userspace task's address environment
2022-03-11 12:35:39 +01:00
/* Provide the maximum amount of page table levels per MMU type */
#ifdef CONFIG_ARCH_MMU_TYPE_SV39
# define ARCH_PGT_MAX_LEVELS (3)
risc-v: SV32 MMU support for qemu-rv.
2023-03-27 01:01:47 +02:00
#elif CONFIG_ARCH_MMU_TYPE_SV32
# define ARCH_PGT_MAX_LEVELS (2)
RISC-V: Initial support for CONFIG_BUILD_KERNEL This implements initial support for kernel build (address environments, page allocator) for RISC-V. This is done a bit differently compared to the ARMV7 implementation: - Support implemented for Sv39 MMU, however the implementation should be extensible for other MMU types also. - Instead of preserving and moving the L1 references around, a canonical approach is used instead, where the page table base address register is switched upon context switch. - To preserve a bit of memory, only a single L1/L2 table is supported, this gives access to 1GiB of virtual memory for each process, which should be more than enough. Some things worth noting: - Assumes page pool is mapped with vaddr=paddr mappings - The CONFIG_ARCH_XXXX_VBASE and CONFIG_ARCH_XXXX_NPAGES values are ignored, with the exception of CONFIG_ARCH_DATA_VBASE which is used for ARCH_DATA_RESERVE - ARCH_DATA_RESERVE is placed at the beginning of the userspace task's address environment
2022-03-11 12:35:39 +01:00
#endif
/* Amount of static page tables allocated for an address environment */
#ifdef CONFIG_ARCH_ADDRENV
# define ARCH_SPGTS (ARCH_PGT_MAX_LEVELS - 1)
#endif
Add support for the RISC-V architecture and configs/nr5m100-nexys4 board. I will be making the FPGA code for this available soon (within a week I would say). The board support on this is pretty thin, but it seems like maybe a good idea to get the base RISC-V stuff in since there are people interested in it.
2016-10-16 17:47:07 +02:00
/****************************************************************************
* Public Types
****************************************************************************/
RISC-V: Initial support for CONFIG_BUILD_KERNEL This implements initial support for kernel build (address environments, page allocator) for RISC-V. This is done a bit differently compared to the ARMV7 implementation: - Support implemented for Sv39 MMU, however the implementation should be extensible for other MMU types also. - Instead of preserving and moving the L1 references around, a canonical approach is used instead, where the page table base address register is switched upon context switch. - To preserve a bit of memory, only a single L1/L2 table is supported, this gives access to 1GiB of virtual memory for each process, which should be more than enough. Some things worth noting: - Assumes page pool is mapped with vaddr=paddr mappings - The CONFIG_ARCH_XXXX_VBASE and CONFIG_ARCH_XXXX_NPAGES values are ignored, with the exception of CONFIG_ARCH_DATA_VBASE which is used for ARCH_DATA_RESERVE - ARCH_DATA_RESERVE is placed at the beginning of the userspace task's address environment
2022-03-11 12:35:39 +01:00
#ifdef CONFIG_ARCH_ADDRENV
#ifndef __ASSEMBLY__
/* A task group must have its L1 table in memory always, and the rest can
* be dynamically committed to memory (and even swapped).
*
risc-v/arch.h: revising comments This revises comments about page tables to help understanding. Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-03-25 08:43:04 +01:00
* In this implementation level tables except the final level N are always
* kept in static memory, while the level N tables are always dynamically
* allocated. There is one static page per level in `spgtables[]`.
RISC-V: Initial support for CONFIG_BUILD_KERNEL This implements initial support for kernel build (address environments, page allocator) for RISC-V. This is done a bit differently compared to the ARMV7 implementation: - Support implemented for Sv39 MMU, however the implementation should be extensible for other MMU types also. - Instead of preserving and moving the L1 references around, a canonical approach is used instead, where the page table base address register is switched upon context switch. - To preserve a bit of memory, only a single L1/L2 table is supported, this gives access to 1GiB of virtual memory for each process, which should be more than enough. Some things worth noting: - Assumes page pool is mapped with vaddr=paddr mappings - The CONFIG_ARCH_XXXX_VBASE and CONFIG_ARCH_XXXX_NPAGES values are ignored, with the exception of CONFIG_ARCH_DATA_VBASE which is used for ARCH_DATA_RESERVE - ARCH_DATA_RESERVE is placed at the beginning of the userspace task's address environment
2022-03-11 12:35:39 +01:00
*
* The implications ? They depend on the MMU type.
*
risc-v/addrenv: Improve the commenting on struct arch_addrenv_s I can never remember whether the static page table list contains the table's physical or kernel virtual address.. Add the fact as a comment there. Also add the limitations that come from this static page table approach for Sv32.
2023-11-01 13:33:48 +01:00
* For Sv32 this means that:
* - A task can not have more than 4GB of memory allocated.
* - The minimum amount of memory needed for page tables per task is 8K,
* which gives access to 4MB of memory. This is plenty for many tasks.
*
RISC-V: Initial support for CONFIG_BUILD_KERNEL This implements initial support for kernel build (address environments, page allocator) for RISC-V. This is done a bit differently compared to the ARMV7 implementation: - Support implemented for Sv39 MMU, however the implementation should be extensible for other MMU types also. - Instead of preserving and moving the L1 references around, a canonical approach is used instead, where the page table base address register is switched upon context switch. - To preserve a bit of memory, only a single L1/L2 table is supported, this gives access to 1GiB of virtual memory for each process, which should be more than enough. Some things worth noting: - Assumes page pool is mapped with vaddr=paddr mappings - The CONFIG_ARCH_XXXX_VBASE and CONFIG_ARCH_XXXX_NPAGES values are ignored, with the exception of CONFIG_ARCH_DATA_VBASE which is used for ARCH_DATA_RESERVE - ARCH_DATA_RESERVE is placed at the beginning of the userspace task's address environment
2022-03-11 12:35:39 +01:00
* For Sv39 this means that:
* - A task can not have more than 1GB of memory allocated. This should be
* plenty enough...
* - The minimum amount of memory needed for page tables per task is 12K,
* which gives access to 2MB of memory. This is plenty for many tasks.
*/
arch/addrenv: Change group_addrenv_t to arch_addrenv_t This is preparation for moving address environments out of the group structure into the tcb. Why move ? Because the group is destroyed very early in the exit phase, but the MMU mappings are needed until the context switch to the next process is complete. Otherwise the MMU will lose its mappings and the system will crash.
2023-01-26 14:35:08 +01:00
struct arch_addrenv_s
RISC-V: Initial support for CONFIG_BUILD_KERNEL This implements initial support for kernel build (address environments, page allocator) for RISC-V. This is done a bit differently compared to the ARMV7 implementation: - Support implemented for Sv39 MMU, however the implementation should be extensible for other MMU types also. - Instead of preserving and moving the L1 references around, a canonical approach is used instead, where the page table base address register is switched upon context switch. - To preserve a bit of memory, only a single L1/L2 table is supported, this gives access to 1GiB of virtual memory for each process, which should be more than enough. Some things worth noting: - Assumes page pool is mapped with vaddr=paddr mappings - The CONFIG_ARCH_XXXX_VBASE and CONFIG_ARCH_XXXX_NPAGES values are ignored, with the exception of CONFIG_ARCH_DATA_VBASE which is used for ARCH_DATA_RESERVE - ARCH_DATA_RESERVE is placed at the beginning of the userspace task's address environment
2022-03-11 12:35:39 +01:00
{
risc-v/addrenv: Improve the commenting on struct arch_addrenv_s I can never remember whether the static page table list contains the table's physical or kernel virtual address.. Add the fact as a comment there. Also add the limitations that come from this static page table approach for Sv32.
2023-11-01 13:33:48 +01:00
/* Physical addresses of the static page tables (levels N-1) here, these
* are allocated when a task is created.
RISC-V: Initial support for CONFIG_BUILD_KERNEL This implements initial support for kernel build (address environments, page allocator) for RISC-V. This is done a bit differently compared to the ARMV7 implementation: - Support implemented for Sv39 MMU, however the implementation should be extensible for other MMU types also. - Instead of preserving and moving the L1 references around, a canonical approach is used instead, where the page table base address register is switched upon context switch. - To preserve a bit of memory, only a single L1/L2 table is supported, this gives access to 1GiB of virtual memory for each process, which should be more than enough. Some things worth noting: - Assumes page pool is mapped with vaddr=paddr mappings - The CONFIG_ARCH_XXXX_VBASE and CONFIG_ARCH_XXXX_NPAGES values are ignored, with the exception of CONFIG_ARCH_DATA_VBASE which is used for ARCH_DATA_RESERVE - ARCH_DATA_RESERVE is placed at the beginning of the userspace task's address environment
2022-03-11 12:35:39 +01:00
*/
uintptr_t spgtables[ARCH_SPGTS];
risc-v/addrenv: Improve the commenting on struct arch_addrenv_s I can never remember whether the static page table list contains the table's physical or kernel virtual address.. Add the fact as a comment there. Also add the limitations that come from this static page table approach for Sv32.
2023-11-01 13:33:48 +01:00
/* The text, data, heap bases and heap size here */
RISC-V: Initial support for CONFIG_BUILD_KERNEL This implements initial support for kernel build (address environments, page allocator) for RISC-V. This is done a bit differently compared to the ARMV7 implementation: - Support implemented for Sv39 MMU, however the implementation should be extensible for other MMU types also. - Instead of preserving and moving the L1 references around, a canonical approach is used instead, where the page table base address register is switched upon context switch. - To preserve a bit of memory, only a single L1/L2 table is supported, this gives access to 1GiB of virtual memory for each process, which should be more than enough. Some things worth noting: - Assumes page pool is mapped with vaddr=paddr mappings - The CONFIG_ARCH_XXXX_VBASE and CONFIG_ARCH_XXXX_NPAGES values are ignored, with the exception of CONFIG_ARCH_DATA_VBASE which is used for ARCH_DATA_RESERVE - ARCH_DATA_RESERVE is placed at the beginning of the userspace task's address environment
2022-03-11 12:35:39 +01:00
uintptr_t textvbase;
uintptr_t datavbase;
uintptr_t heapvbase;
size_t heapsize;
risc-v/addrenv: Improve the commenting on struct arch_addrenv_s I can never remember whether the static page table list contains the table's physical or kernel virtual address.. Add the fact as a comment there. Also add the limitations that come from this static page table approach for Sv32.
2023-11-01 13:33:48 +01:00
/* The page directory root (satp) value */
RISC-V: Initial support for CONFIG_BUILD_KERNEL This implements initial support for kernel build (address environments, page allocator) for RISC-V. This is done a bit differently compared to the ARMV7 implementation: - Support implemented for Sv39 MMU, however the implementation should be extensible for other MMU types also. - Instead of preserving and moving the L1 references around, a canonical approach is used instead, where the page table base address register is switched upon context switch. - To preserve a bit of memory, only a single L1/L2 table is supported, this gives access to 1GiB of virtual memory for each process, which should be more than enough. Some things worth noting: - Assumes page pool is mapped with vaddr=paddr mappings - The CONFIG_ARCH_XXXX_VBASE and CONFIG_ARCH_XXXX_NPAGES values are ignored, with the exception of CONFIG_ARCH_DATA_VBASE which is used for ARCH_DATA_RESERVE - ARCH_DATA_RESERVE is placed at the beginning of the userspace task's address environment
2022-03-11 12:35:39 +01:00
uintptr_t satp;
};
arch/addrenv: Change group_addrenv_t to arch_addrenv_t This is preparation for moving address environments out of the group structure into the tcb. Why move ? Because the group is destroyed very early in the exit phase, but the MMU mappings are needed until the context switch to the next process is complete. Otherwise the MMU will lose its mappings and the system will crash.
2023-01-26 14:35:08 +01:00
typedef struct arch_addrenv_s arch_addrenv_t;
RISC-V: Initial support for CONFIG_BUILD_KERNEL This implements initial support for kernel build (address environments, page allocator) for RISC-V. This is done a bit differently compared to the ARMV7 implementation: - Support implemented for Sv39 MMU, however the implementation should be extensible for other MMU types also. - Instead of preserving and moving the L1 references around, a canonical approach is used instead, where the page table base address register is switched upon context switch. - To preserve a bit of memory, only a single L1/L2 table is supported, this gives access to 1GiB of virtual memory for each process, which should be more than enough. Some things worth noting: - Assumes page pool is mapped with vaddr=paddr mappings - The CONFIG_ARCH_XXXX_VBASE and CONFIG_ARCH_XXXX_NPAGES values are ignored, with the exception of CONFIG_ARCH_DATA_VBASE which is used for ARCH_DATA_RESERVE - ARCH_DATA_RESERVE is placed at the beginning of the userspace task's address environment
2022-03-11 12:35:39 +01:00
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_ARCH_ADDRENV */
Add support for the RISC-V architecture and configs/nr5m100-nexys4 board. I will be making the FPGA code for this available soon (within a week I would say). The board support on this is pretty thin, but it seems like maybe a good idea to get the base RISC-V stuff in since there are people interested in it.
2016-10-16 17:47:07 +02:00
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
Fix nxstyle complaints
2020-05-07 02:40:46 +02:00
extern "C"
{
Add support for the RISC-V architecture and configs/nr5m100-nexys4 board. I will be making the FPGA code for this available soon (within a week I would say). The board support on this is pretty thin, but it seems like maybe a good idea to get the base RISC-V stuff in since there are people interested in it.
2016-10-16 17:47:07 +02:00
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ARCH_RISCV_INCLUDE_ARCH_H */
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