41 lines
1.6 KiB
Plaintext
41 lines
1.6 KiB
Plaintext
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README for the Expressif ESP32 Core board (V2)
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The ESP32 is a dual-core system from Expressif with two Harvard
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architecture Xtensa LX6 CPUs. All embedded memory, external memory and
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peripherals are located on the data bus and/or the instruction bus of
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these CPUs. With some minor exceptions, the address mapping of two CPUs
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is symmetric, meaning they use the same addresses to access the same
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memory. Multiple peripherals in the system can access embedded memory via
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DMA.
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The two CPUs are named "PRO_CPU" and "APP_CPU" (for "protocol" and
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"application"), however for most purposes the two CPUs are
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interchangeable.
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Features:
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* Address Space
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- Symmetric address mapping
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- 4 GB (32-bit) address space for both data bus and instruction bus
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- 1296 KB embedded memory address space
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- 19704 KB external memory address space
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- 512 KB peripheral address space
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- Some embedded and external memory regions can be accessed by either
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data bus or instruction bus
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- 328 KB DMA address space
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* Embedded Memory
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- 448 KB Internal ROM
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- 520 KB Internal SRAM
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- 8 KB RTC FAST Memory
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- 8 KB RTC SLOW Memory
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* External Memory
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Off-chip SPI memory can be mapped into the available address space as
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external memory. Parts of the embedded memory can be used as transparent
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cache for this external memory.
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- Supports up to 16 MB off-Chip SPI Flash.
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- Supports up to 8 MB off-Chip SPI SRAM.
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* Peripherals
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- 41 peripherals
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* DMA
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- 13 modules are capable of DMA operation
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