2014-11-26 22:18:24 +01:00
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README
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======
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README for NuttX port to the LPC4357-EVB board from Embest featuring the NXP
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LPC4357FET256 MCU - The port was derived from the LPC4357-EVB board NuttX
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port.
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Contents
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========
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- LPC4357-EVB development board
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- Status
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- Code Red IDE/Tools
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Booting the LPCLink
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Using GDB
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Troubleshooting
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Command Line Flash Programming
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Executing from SPIFI
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USB DFU Booting
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2014-11-27 17:28:32 +01:00
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- LED and Pushbuttons
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2014-11-26 22:18:24 +01:00
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- Serial Console
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- FPU
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- LPC4357-EVB Configuration Options
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- Configurations
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- STATUS
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LPC4357-EVB board
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=================
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Memory Map
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----------
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Block Start Length
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Name Address
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--------------------- ---------- ------
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RAM 0x10000000 32K
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RAM2 0x10080000 40K
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SPIFI flash 0x14000000 4096K
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FlashA 0x1a000000 512k
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FlashB 0x1b000000 512k
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Console
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-------
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The LPC4357-EVB default console is the USART0.
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Status
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======
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This is the current status of the LPC43xx port:
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- The basic OS test configuration and the basic NSH configurations
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are present and fully verified. This includes: SYSTICK system time,
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pin and GPIO configuration, and serial console support. A SPIFI
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MTD driver is also in place but requires further verification.
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2019-07-11 18:50:00 +02:00
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- The following drivers have been copied from the LPC17xx/LPC40xx port, but
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2014-11-26 22:18:24 +01:00
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require integration into the LPC43xx. This integration should
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consist of:
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2019-07-11 18:50:00 +02:00
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- Remove LPC17xx/LPC40xx power, clocking, and pin configuration logic.
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2014-11-26 22:18:24 +01:00
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- Adding of clock source and frequency to the board.h file.
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- Adding of LPC43 clock connection and pin configuration logic.
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Within any luck, these drivers should come up very quickly:
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- lpc43_adc.c,
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- lpc43_dac.c,
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- lpc43_gpdma.c,
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- lpc43_i2c.c,
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- lpc43_spi.c, and
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- lpc43_ssp.c
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2019-07-11 18:50:00 +02:00
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These LPC17xx/LPC40xx drivers were not brought into the LPC43xx port because
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2017-05-11 21:35:56 +02:00
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it appears that these peripherals have been completely redesigned:
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2014-11-26 22:18:24 +01:00
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- CAN,
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- Ethernet,
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- USB device, and
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- USB host.
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The following LPC43xx peripherals are unsupported. Some may be
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2019-07-11 18:50:00 +02:00
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compatible with the LPC17xx/LPC40xx, but there is no LPC17xx/LPC40xx driver to be
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2014-11-26 22:18:24 +01:00
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ported:
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- SD/MMC,
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- EMC,
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- USB0,
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- USB1,
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- Ethernet,
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- LCD,
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- SCT,
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- Timers 0-3
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- MCPWM,
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- QEI,
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- Alarm timer,
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- WWDT,
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- RTC,
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- Event monitor, and
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- CAN,
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For the missing drivers some of these can be leveraged from other
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MCUs that appear to support the same peripheral IP.
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- USB0 appears to be the same as the USB OTG peripheral for the
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LPC31xx. It should be possible to drop in the LPC31xx driver
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with a small porting effort.
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- The Ethernet block looks to be based on the same IP as the
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STM32 Ethernet and, as a result, it should be possible to leverage
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the STM32 Ethernet driver with a little more effort.
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Code Red IDE/Tools
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^^^^^^^^^^^^^^^^^^
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Booting the LPCLink
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-------------------
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The first step is to activate the LPCLink's boot mode. Some general
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instructions to do this are provided here:
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http://support.code-red-tech.com/CodeRedWiki/BootingLPCLink
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For my RedSuite installation path, that can be done using the following
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steps in a Cygwin bash shell:
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$ /cygdrive/c/code_red/RedSuite_4.2.3_379/redsuite/bin/Scripts/bootLPCXpresso.cmd winusb
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Booting LPC-Link with LPCXpressoWIN.enc
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Press any key to continue . . .
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The same file logic can be found the less restrictive LPCXpresso package at:
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/cygdrive/c/nxp/LPCXpresso_4.2.3_292/lpcxpresso/bin
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(The "free" RedSuite version has a download limit of 8K; the "free" LPCXpresso
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version has a download limit of 128K).
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2017-04-26 18:12:13 +02:00
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NOTE that the following alias may be defined to enter the boot mode with a
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simpler command:
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2014-11-26 22:18:24 +01:00
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alias lpc43xx='${SCRIPT_BIN}/Scripts/bootLPCXpresso.cmd winusb'
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2017-04-26 18:12:13 +02:00
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You may also have to modify the PATH environment variable if your make cannot
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find the tools.
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2014-11-26 22:18:24 +01:00
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$ lpc43xx
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Booting LPC-Link with LPCXpressoWIN.enc
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Press any key to continue . . .
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Using GDB
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---------
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The underlying debugger within Red Suite/LPCXpresso is GDB. That GDB
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used from the command line. The GDB configuration details for command
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line use are on Code Red Wiki:
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http://support.code-red-tech.com/CodeRedWiki/UsingGDB
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and is also summarized here (see the full Wiki for additional details
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and options).
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The Code Red Debug Driver implements the GDB "remote" protocol to allow
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connection to debug targets. To start a debug session using GDB, use
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following steps:
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arm-none-eabi-gdb executable.axf : Start GDB and name the debug image
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target extended-remote | <debug driver> <options> : Start debug driver, connect to target
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load : Load image and download to target
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The where <debug driver> is crt_emu_lpc18_43_nxp for LPC18xx and LPC43xx.
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Your PATH variable should be set up so that the debug driver executable
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can be found. For my installation, the driver for the LPC18xx and LPC43xx
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is located at:
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/cygdrive/c/code_red/RedSuite_4.2.3_379/redsuite/bin/crt_emu_lpc18_43_nxp.exe, OR
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/cygdrive/c/nxp/LPCXpresso_4.2.3_292/lpcxpresso/bin/crt_emu_lpc18_43_nxp.exe
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And <options> are:
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-n set information level for the debug driver. n should be 2, 3 or 4.
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2 should be sufficient in most circumstances
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-p<part> is the target device to connect to and you should use
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<part>=LPC4357.
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-wire=<probe> specifies the debug probe. For LPCLink on Windows 7 use
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<probe>=winusb. The 128K free version only supports the LPC-Link
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and RedProbe debug probes. Other JTAG interfaces are supported in
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the full version.
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Thus the correct invocation for the LPC4357 under Windows7 would be:
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target extended-remote | crt_emu_lpc18_43_nxp -2 -pLPC4357 -wire=winusb
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DDD. This command can be used to start GDB under the graphics front-end
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DDD:
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$ ddd --debugger arm-none-eabi-gdb nuttx &
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NOTE 1: Don't forget to put the LPCLink in boot mode as described above
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before starting GDB. So a typical session might look like this:
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$ lpc43xx
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Booting LPC-Link with LPCXpressoWIN.enc
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Press any key to continue . . .
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$ arm-none-eabi-gdb nuttx
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(gdb) target extended-remote | crt_emu_lpc18_43_nxp -2 -pLPC4357 -wire=winusb
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(gdb) load
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(gdb) r
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(gdb) c
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NOTE 2: Don't forget to enable CONFIG_DEBUG_SYMBOLS=y in your NuttX
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configuration file when you build NuttX. That option is necessary to build
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in debugging symbols.
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NOTE 3: There are few things that NuttX has to do differently if you
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2016-06-11 22:14:08 +02:00
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are using a debugger. Make sure that you also set CONFIG_DEBUG_FEATURES=y. Nothing
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2014-11-26 22:18:24 +01:00
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also is needed and no debug output will be generated; but NuttX will
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2016-06-11 22:14:08 +02:00
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use CONFIG_DEBUG_FEATURES=y to mean that a debugger is attached and will deal
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2014-11-26 22:18:24 +01:00
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with certain resets and debug controls appropriately.
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So you should have:
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2016-06-11 22:14:08 +02:00
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CONFIG_DEBUG_FEATURES=y
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2014-11-26 22:18:24 +01:00
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CONFIG_DEBUG_SYMBOLS=y
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NOTE 4: Every time that you control-C out of the command line GDB, you
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leave a copy of the Code Red debugger (crt_emu_lpc18_43_nxp) running. I
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have found that if you have these old copies of the debugger running,
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hen strange things can happen when start yet another copy of the
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debugger (I suspect that GDB may be talking with the wrong debugger).
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If you exit GDB with quit (not control-C), it seems to clean-up okay.
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But I have taken to keeping a Process Explorer window open all of the
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time to keep track of how many of these bad processes have been created.
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NOTE 5: There is also a certain function that is causing some problems.
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The very first thing that the start-up logic does is call a function
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called lpc43_softreset() which resets most of the peripherals. But it
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also causes some crashes... I think because the resets are causing some
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interrupts.
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I put a big delay in the soft reset logic between resetting and clearing
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pending interrupts and that seems to help some but I am not confident
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that that is a fix. I think that the real fix might be to just eliminated
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this lpc43_softreset() function if we determine that it is not needed.
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If you step over lpc43_softreset() after loading the coding (using the 'n'
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command), then everything seems work okay.
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Troubleshooting
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---------------
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This page provides some troubleshooting information that you can use to
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verify that the LPCLink is working correctly:
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http://support.code-red-tech.com/CodeRedWiki/LPCLinkDiagnostics
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Command Line Flash Programming
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------------------------------
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The LPC18xx/LPC43xx debug driver can also be used to program the LPC43xx
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flash directly from the command line. The script flash.sh that may be
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2019-08-05 15:13:48 +02:00
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found in the boards/lpc4357-evb/scripts directory can do that with
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2014-11-26 22:18:24 +01:00
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a single command line command.
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Executing from SPIFI
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--------------------
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By default, the configurations here assume that you are executing directly
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from SRAM.
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2020-05-13 16:18:31 +02:00
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CONFIG_LPC43_BOOT_SRAM=y : Executing in SRAM
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2022-04-18 18:02:33 +02:00
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CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI=y : GNU EABI toolchain for Linux
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2014-11-26 22:18:24 +01:00
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To execute from SPIFI, you would need to set:
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CONFIG_LPC43_BOOT_SPIFI=y : Executing from SPIFI
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CONFIG_RAM_SIZE=(128*1024) : SRAM Bank0 size
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CONFIG_RAM_START=0x10000000 : SRAM Bank0 base address
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CONFIG_SPIFI_OFFSET=(512*1024) : SPIFI file system offset
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To boot the LPC4357-EVB from SPIFI the DIP switches should be 1-OFF,
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2-ON, 3-ON, 4-ON (LOW LOW LOW HIGH in Table 19, MSB to LSB).
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If the code in flash hard faults after reset and crt_emu_lpc18_43_nxp
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can't reset the MCU, an alternative is to temporarily change switch 1
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to ON and press the reset button so it enters UART boot mode. Then
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change it back to OFF and reset to boot again from flash.
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# Use -wire to specify the debug probe in use:
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# (empty) Red Probe+
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# -wire=winusb LPC-Link on Windows XP
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# -wire=hid LPC-Link on Windows Vista/ Windows 7
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# Add -g -4 for verbose output
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crt_emu_lpc18_43_nxp -wire=hid -pLPC4357 -load-base=0x14000000
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-flash-load-exec=nuttx.bin -flash-driver=LPC1850A_4350A_SPIFI.cfx
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USB DFU Booting
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---------------
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To be provided.
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2014-11-27 17:28:32 +01:00
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LED and Pushbuttons
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===================
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LED
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---
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The LPC4357-EVB has one user-controllable LED labelled D6 controlled
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by the signal LED_3V3:
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LED SIGNAL MCU
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D6 LED_3V3 PE_& GPIO7[7]
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2014-11-27 19:38:04 +01:00
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A low output illuminates the LED.
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2014-11-27 17:28:32 +01:00
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If CONFIG_ARCH_LEDS is defined, the LED will be controlled as follows
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for NuttX debug functionality (where NC means "No Change").
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-------------------------- ---------
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LED
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-------------------------- ---------
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LED_STARTED OFF
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LED_HEAPALLOCATE OFF
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LED_IRQSENABLED OFF
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LED_STACKCREATED ON
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LED_INIRQ NC
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LED_SIGNAL NC
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LED_ASSERTION NC
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LED_PANIC Flashing
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-------------------------- ---------
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If CONFIG_ARCH_LEDS is not defined, then the LEDs are completely under
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control of the application. The following interfaces are then available
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for application control of the LEDs:
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2020-06-05 12:08:02 +02:00
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uint32_t board_userled_initialize(void);
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2015-11-01 19:45:58 +01:00
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void board_userled(int led, bool ledon);
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2020-06-06 12:35:44 +02:00
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void board_userled_all(uint32_t ledset);
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2014-11-27 17:28:32 +01:00
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Pushbuttons
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-----------
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To be provided
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2014-11-26 22:18:24 +01:00
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Serial Console
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==============
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The LPC4357-EVB does not have RS-232 drivers or serial connectors on board.
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USART, USART2 and USART3 are available on J12 as follows:
|
|
|
|
|
|
|
|
------ ------ -----------------------
|
|
|
|
SIGNAL J12 PIN LPC4357FET256 PIN
|
|
|
|
(TFBGA256 package)
|
|
|
|
------ ------ -----------------------
|
|
|
|
U0_TXD pin 3 F6 P9_5 U0_TXD=Alt 4
|
|
|
|
U0_RXD pin 4 F9 P9_6 U0_RXD=Alt 4
|
|
|
|
U2_TXD pin 5 H8 P1_13 U1_TXD=Alt 1
|
|
|
|
U2_RXD pin 6 J8 P1_14 U1_RXD=Alt 1
|
|
|
|
U3_TXD pin 7 H8 P1_13 U1_TXD=Alt 1
|
|
|
|
U3_RXD pin 8 J8 P1_14 U1_RXD=Alt 1
|
|
|
|
------ ------ -----------------------
|
|
|
|
|
|
|
|
GND is available on J12 pins 29 and 30
|
|
|
|
5V is available on J12 pin 2
|
|
|
|
3.3v id available on J12 pin 1
|
|
|
|
|
|
|
|
FPU
|
|
|
|
===
|
|
|
|
|
|
|
|
FPU Configuration Options
|
|
|
|
-------------------------
|
|
|
|
|
|
|
|
There are two version of the FPU support built into the most NuttX Cortex-M4
|
2018-08-13 15:39:38 +02:00
|
|
|
ports.
|
2014-11-26 22:18:24 +01:00
|
|
|
|
2018-06-20 20:30:37 +02:00
|
|
|
1. Non-Lazy Floating Point Register Save
|
2014-11-26 22:18:24 +01:00
|
|
|
|
2018-06-20 20:30:37 +02:00
|
|
|
In this configuration floating point register save and restore is
|
|
|
|
implemented on interrupt entry and return, respectively. In this
|
|
|
|
case, you may use floating point operations for interrupt handling
|
|
|
|
logic if necessary. This FPU behavior logic is enabled by default
|
|
|
|
with:
|
|
|
|
|
|
|
|
CONFIG_ARCH_FPU=y
|
|
|
|
|
|
|
|
2. Lazy Floating Point Register Save.
|
|
|
|
|
|
|
|
An alternative mplementation only saves and restores FPU registers only
|
|
|
|
on context switches. This means: (1) floating point registers are not
|
|
|
|
stored on each context switch and, hence, possibly better interrupt
|
2014-11-26 22:18:24 +01:00
|
|
|
performance. But, (2) since floating point registers are not saved,
|
|
|
|
you cannot use floating point operations within interrupt handlers.
|
|
|
|
|
|
|
|
This logic can be enabled by simply adding the following to your .config
|
|
|
|
file:
|
|
|
|
|
2018-06-20 20:30:37 +02:00
|
|
|
CONFIG_ARCH_FPU=y
|
2014-11-26 22:18:24 +01:00
|
|
|
|
|
|
|
LPC4357-EVB Configuration Options
|
|
|
|
=====================================
|
|
|
|
|
|
|
|
CONFIG_ARCH - Identifies the arch/ subdirectory. This should
|
|
|
|
be set to:
|
|
|
|
|
|
|
|
CONFIG_ARCH=arm
|
|
|
|
|
|
|
|
CONFIG_ARCH_family - For use in C code:
|
|
|
|
|
|
|
|
CONFIG_ARCH_ARM=y
|
|
|
|
|
|
|
|
CONFIG_ARCH_architecture - For use in C code:
|
|
|
|
|
|
|
|
CONFIG_ARCH_CORTEXM3=y
|
|
|
|
|
|
|
|
CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
|
|
|
|
|
|
|
|
CONFIG_ARCH_CHIP=lpc43xx
|
|
|
|
|
|
|
|
CONFIG_ARCH_CHIP_name - For use in C code to identify the exact
|
|
|
|
chip:
|
|
|
|
|
|
|
|
CONFIG_ARCH_CHIP_LPC4357=y
|
|
|
|
|
2019-08-05 15:13:48 +02:00
|
|
|
CONFIG_ARCH_BOARD - Identifies the boards/ subdirectory and
|
2014-11-26 22:18:24 +01:00
|
|
|
hence, the board that supports the particular chip or SoC.
|
|
|
|
|
|
|
|
CONFIG_ARCH_BOARD=lpc4357-evb (for the LPC4357-EVB board)
|
|
|
|
|
|
|
|
CONFIG_ARCH_BOARD_name - For use in C code
|
|
|
|
|
|
|
|
CONFIG_ARCH_BOARD_LPC4357EVB=y
|
|
|
|
|
|
|
|
CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
|
|
|
|
of delay loops
|
|
|
|
|
|
|
|
CONFIG_ENDIAN_BIG - define if big endian (default is little
|
|
|
|
endian)
|
|
|
|
|
|
|
|
CONFIG_RAM_SIZE - Describes the installed DRAM (CPU SRAM in this case):
|
|
|
|
|
|
|
|
CONFIG_RAM_SIZE=(32*1024) (32Kb)
|
|
|
|
|
|
|
|
There is an additional 32Kb of SRAM in AHB SRAM banks 0 and 1.
|
|
|
|
|
|
|
|
CONFIG_RAM_START - The start address of installed DRAM
|
|
|
|
|
|
|
|
CONFIG_RAM_START=0x10000000
|
|
|
|
|
|
|
|
CONFIG_ARCH_FPU - The LPC43xxx supports a floating point unit (FPU)
|
|
|
|
|
|
|
|
CONFIG_ARCH_FPU=y
|
|
|
|
|
|
|
|
CONFIG_LPC43_BOOT_xxx - The startup code needs to know if the code is running
|
|
|
|
from internal FLASH, external FLASH, SPIFI, or SRAM in order to
|
|
|
|
initialize properly. Note that a boot device is not specified for
|
|
|
|
cases where the code is copied into SRAM; those cases are all covered
|
|
|
|
by CONFIG_LPC43_BOOT_SRAM.
|
|
|
|
|
|
|
|
CONFIG_LPC43_BOOT_SRAM=y : Running from SRAM (0x1000:0000)
|
|
|
|
CONFIG_LPC43_BOOT_SPIFI=y : Running from QuadFLASH (0x1400:0000)
|
|
|
|
CONFIG_LPC43_BOOT_FLASHA=y : Running in internal FLASHA (0x1a00:0000)
|
|
|
|
CONFIG_LPC43_BOOT_FLASHB=y : Running in internal FLASHA (0x1b00:0000)
|
|
|
|
CONFIG_LPC43_BOOT_CS0FLASH=y : Running in external FLASH CS0 (0x1c00:0000)
|
|
|
|
CONFIG_LPC43_BOOT_CS1FLASH=y : Running in external FLASH CS1 (0x1d00:0000)
|
|
|
|
CONFIG_LPC43_BOOT_CS2FLASH=y : Running in external FLASH CS2 (0x1e00:0000)
|
|
|
|
CONFIG_LPC43_BOOT_CS3FLASH=y : Running in external FLASH CS3 (0x1f00:0000)
|
|
|
|
|
|
|
|
CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that
|
|
|
|
have LEDs
|
|
|
|
|
|
|
|
CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
|
|
|
|
stack. If defined, this symbol is the size of the interrupt
|
|
|
|
stack in bytes. If not defined, the user task stacks will be
|
|
|
|
used during interrupt handling.
|
|
|
|
|
|
|
|
CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
|
|
|
|
|
|
|
|
CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture.
|
|
|
|
|
|
|
|
Individual subsystems can be enabled:
|
|
|
|
|
|
|
|
CONFIG_LPC43_ADC0=y
|
|
|
|
CONFIG_LPC43_ADC1=y
|
|
|
|
CONFIG_LPC43_ATIMER=y
|
2018-06-28 23:11:23 +02:00
|
|
|
CONFIG_LPC43_CAN0=y
|
2014-11-26 22:18:24 +01:00
|
|
|
CONFIG_LPC43_CAN1=y
|
|
|
|
CONFIG_LPC43_DAC=y
|
|
|
|
CONFIG_LPC43_EMC=y
|
|
|
|
CONFIG_LPC43_ETHERNET=y
|
|
|
|
CONFIG_LPC43_EVNTMNTR=y
|
|
|
|
CONFIG_LPC43_GPDMA=y
|
|
|
|
CONFIG_LPC43_I2C0=y
|
|
|
|
CONFIG_LPC43_I2C1=y
|
|
|
|
CONFIG_LPC43_I2S0=y
|
|
|
|
CONFIG_LPC43_I2S1=y
|
|
|
|
CONFIG_LPC43_LCD=y
|
|
|
|
CONFIG_LPC43_MCPWM=y
|
|
|
|
CONFIG_LPC43_QEI=y
|
|
|
|
CONFIG_LPC43_RIT=y
|
|
|
|
CONFIG_LPC43_RTC=y
|
|
|
|
CONFIG_LPC43_SCT=y
|
|
|
|
CONFIG_LPC43_SDMMC=y
|
|
|
|
CONFIG_LPC43_SPI=y
|
|
|
|
CONFIG_LPC43_SPIFI=y
|
|
|
|
CONFIG_LPC43_SSP0=y
|
|
|
|
CONFIG_LPC43_SSP1=y
|
|
|
|
CONFIG_LPC43_TMR0=y
|
|
|
|
CONFIG_LPC43_TMR1=y
|
|
|
|
CONFIG_LPC43_TMR2=y
|
|
|
|
CONFIG_LPC43_TMR3=y
|
|
|
|
CONFIG_LPC43_USART0=y
|
|
|
|
CONFIG_LPC43_UART1=y
|
|
|
|
CONFIG_LPC43_USART2=y
|
|
|
|
CONFIG_LPC43_USART3=y
|
|
|
|
CONFIG_LPC43_USB0=y
|
|
|
|
CONFIG_LPC43_USB1=y
|
|
|
|
CONFIG_LPC43_USB1_ULPI=y
|
|
|
|
CONFIG_LPC43_WWDT=y
|
|
|
|
|
|
|
|
LPC43xx specific U[S]ART device driver settings
|
|
|
|
|
|
|
|
CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the UARTn for the
|
|
|
|
console and ttys0 (default is the USART0).
|
|
|
|
CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received.
|
|
|
|
This specific the size of the receive buffer
|
|
|
|
CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before
|
|
|
|
being sent. This specific the size of the transmit buffer
|
|
|
|
CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be
|
|
|
|
CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8.
|
|
|
|
CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
|
|
|
|
CONFIG_U[S]ARTn_2STOP - Two stop bits
|
|
|
|
|
|
|
|
CONFIG_USARTn_RS485MODE - Support LPC43xx USART0,2,3 RS485 mode
|
|
|
|
ioctls (TIOCSRS485 and TIOCGRS485) to enable and disable
|
|
|
|
RS-485 mode.
|
|
|
|
|
|
|
|
LPC43xx specific CAN device driver settings. These settings all
|
|
|
|
require CONFIG_CAN:
|
|
|
|
|
|
|
|
CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID. Default
|
|
|
|
Standard 11-bit IDs.
|
2018-06-28 23:11:23 +02:00
|
|
|
CONFIG_LPC43_CAN0_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC43_CAN0
|
|
|
|
is defined.
|
|
|
|
CONFIG_LPC43_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC43_CAN1
|
|
|
|
is defined.
|
2018-06-28 23:44:42 +02:00
|
|
|
CONFIG_LPC43_CAN_TSEG1 - The number of CAN time quanta in segment 1.
|
|
|
|
Default: 12
|
|
|
|
CONFIG_LPC43_CAN_TSEG2 = the number of CAN time quanta in segment 2.
|
|
|
|
Default: 4
|
2014-11-26 22:18:24 +01:00
|
|
|
|
|
|
|
LPC43xx specific PHY/Ethernet device driver settings. These setting
|
|
|
|
also require CONFIG_NET and CONFIG_LPC43_ETHERNET.
|
|
|
|
|
|
|
|
CONFIG_ETH0_PHY_KS8721 - Selects Micrel KS8721 PHY
|
2020-02-23 09:50:23 +01:00
|
|
|
CONFIG_LPC43_AUTONEG - Enable auto-negotiation
|
2018-06-30 19:55:41 +02:00
|
|
|
|
2019-07-11 18:50:00 +02:00
|
|
|
CONFIG_LPC17_40_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb
|
2018-06-30 19:55:41 +02:00
|
|
|
CONFIG_LPC43_ETH_NTXDESC - Configured number of Tx descriptors. Default: 18
|
|
|
|
CONFIG_LPC43_ETH_NRXDESC - Configured number of Rx descriptors. Default: 18
|
2014-11-26 22:18:24 +01:00
|
|
|
CONFIG_NET_REGDEBUG - Enabled low level register debug. Also needs
|
2016-06-11 22:14:08 +02:00
|
|
|
CONFIG_DEBUG_FEATURES.
|
2014-11-26 22:18:24 +01:00
|
|
|
CONFIG_NET_DUMPPACKET - Dump all received and transmitted packets.
|
2016-06-11 22:14:08 +02:00
|
|
|
Also needs CONFIG_DEBUG_FEATURES.
|
2014-11-26 22:18:24 +01:00
|
|
|
|
|
|
|
LPC43xx USB Device Configuration
|
|
|
|
|
|
|
|
CONFIG_LPC43_USBDEV_FRAME_INTERRUPT
|
|
|
|
Handle USB Start-Of-Frame events.
|
|
|
|
Enable reading SOF from interrupt handler vs. simply reading on demand.
|
|
|
|
Probably a bad idea... Unless there is some issue with sampling the SOF
|
|
|
|
from hardware asynchronously.
|
|
|
|
CONFIG_LPC43_USBDEV_EPFAST_INTERRUPT
|
|
|
|
Enable high priority interrupts. I have no idea why you might want to
|
|
|
|
do that
|
|
|
|
CONFIG_LPC43_USBDEV_NDMADESCRIPTORS
|
|
|
|
Number of DMA descriptors to allocate in SRAM.
|
|
|
|
CONFIG_LPC43_USBDEV_DMA
|
2019-07-11 18:50:00 +02:00
|
|
|
Enable lpc17xx/lpc40xx-specific DMA support
|
2014-11-26 22:18:24 +01:00
|
|
|
CONFIG_LPC43_USBDEV_NOVBUS
|
|
|
|
Define if the hardware implementation does not support the VBUS signal
|
|
|
|
CONFIG_LPC43_USBDEV_NOLED
|
|
|
|
Define if the hardware implementation does not support the LED output
|
|
|
|
|
|
|
|
Configurations
|
|
|
|
==============
|
|
|
|
|
|
|
|
Each LPC4357-EVB configuration is maintained in a sub-directory and can be selected
|
|
|
|
as follow:
|
|
|
|
|
2019-08-06 00:53:39 +02:00
|
|
|
tools/configure.sh lpc4357-evb:<subdir>
|
2014-11-26 22:18:24 +01:00
|
|
|
|
|
|
|
Where <subdir> is one of the following:
|
|
|
|
|
|
|
|
nsh:
|
|
|
|
----
|
|
|
|
This configuration is the NuttShell (NSH) example at examples/nsh/.
|
|
|
|
|
|
|
|
NOTES:
|
|
|
|
|
|
|
|
1. This configuration uses the mconf-based configuration tool. To
|
|
|
|
change this configurations using that tool, you should:
|
|
|
|
|
|
|
|
a. Build and install the kconfig-mconf tool. See nuttx/README.txt
|
2015-06-28 16:08:57 +02:00
|
|
|
see additional README.txt files in the NuttX tools repository.
|
2014-11-26 22:18:24 +01:00
|
|
|
|
|
|
|
b. Execute 'make menuconfig' in nuttx/ in order to start the
|
|
|
|
reconfiguration process.
|
|
|
|
|
|
|
|
2. The project can exucute directly from SRAM with NuttX loaded by a debugger
|
|
|
|
by setting the following configuration options.
|
|
|
|
|
2020-05-13 16:18:31 +02:00
|
|
|
CONFIG_LPC43_BOOT_SRAM=y : Executing in SRAM
|
2022-04-18 18:02:33 +02:00
|
|
|
CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI=y : GNU EABI toolchain for Windows
|
2014-11-26 22:18:24 +01:00
|
|
|
|
|
|
|
3. To execute from SPIFI, you would need to set:
|
|
|
|
|
|
|
|
CONFIG_LPC43_BOOT_SPIFI=y : Executing from SPIFI
|
|
|
|
CONFIG_RAM_SIZE=(128*1024) : SRAM Bank0 size
|
|
|
|
CONFIG_RAM_START=0x10000000 : SRAM Bank0 base address
|
|
|
|
CONFIG_SPIFI_OFFSET=(512*1024) : SPIFI file system offset
|
|
|
|
|
|
|
|
CONFIG_MM_REGIONS should also be increased if you want to other SRAM banks
|
|
|
|
to the memory pool.
|
|
|
|
|
|
|
|
4. This configuration an also be used create a block device on the SPIFI
|
|
|
|
FLASH. CONFIG_LPC43_SPIFI=y must also be defined to enable SPIFI setup
|
|
|
|
support:
|
|
|
|
|
|
|
|
SPIFI device geometry:
|
|
|
|
|
|
|
|
CONFIG_SPIFI_OFFSET - Offset the beginning of the block driver this many
|
|
|
|
bytes into the device address space. This offset must be an exact
|
|
|
|
multiple of the erase block size (CONFIG_SPIFI_BLKSIZE). Default 0.
|
|
|
|
CONFIG_SPIFI_BLKSIZE - The size of one device erase block. If not defined
|
|
|
|
then the driver will try to determine the correct erase block size by
|
|
|
|
examining that data returned from spifi_initialize (which sometimes
|
|
|
|
seems bad).
|
|
|
|
|
|
|
|
Other SPIFI options
|
|
|
|
|
|
|
|
CONFIG_SPIFI_SECTOR512 - If defined, then the driver will report a more
|
|
|
|
FAT friendly 512 byte sector size and will manage the read-modify-write
|
|
|
|
operations on the larger erase block.
|
|
|
|
CONFIG_SPIFI_READONLY - Define to support only read-only operations.
|
|
|
|
CONFIG_SPIFI_LIBRARY - Don't use the LPC43xx ROM routines but, instead,
|
|
|
|
use an external library implementation of the SPIFI interface.
|
|
|
|
CONFIG_SPIFI_VERIFY - Verify all spifi_program() operations by reading
|
|
|
|
from the SPI address space after each write.
|
|
|
|
CONFIG_DEBUG_SPIFI_DUMP - Debug option to dump read/write buffers. You
|
|
|
|
probably do not want to enable this unless you want to dig through a
|
2016-06-11 22:14:08 +02:00
|
|
|
*lot* of debug output! Also required CONFIG_DEBUG_FEATURES, CONFIG_DEBUG_INFO,
|
2014-11-26 22:18:24 +01:00
|
|
|
and CONFIG_DEBUG_FS,
|
|
|
|
|
|
|
|
5. In my experience, there were some missing function pointers in the LPC43xx
|
|
|
|
SPIFI ROM routines and the SPIFI configuration could only be built with
|
|
|
|
CONFIG_SPIFI_LIBRARY=y. The SPIFI library is proprietary and cannot be
|
|
|
|
provided within NuttX open source repository; SPIFI library binaries can
|
|
|
|
be found on the lpcware.com website. In this build sceneario, you must
|
|
|
|
also provide the patch to the external SPIFI library be defining the make
|
|
|
|
variable EXTRA_LIBS in the top-level Make.defs file. Good luck!
|
|
|
|
|
|
|
|
6. By default the LPC4357-EVB port is configured to run from the onboard flash
|
|
|
|
bank A at 0x1a000000. In order to achieve this, the resulting NuttX binary
|
|
|
|
will need to have a checksum computed over the vector table and then be
|
|
|
|
converted to a hex file which can then be flashed using a debugger such as
|
|
|
|
the ULINK2 through Keil.
|
|
|
|
|
|
|
|
The checksum can be computed using the checksum binary provided with the
|
|
|
|
LPCXpresso IDE software suite as follows:
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./checksum nuttx.bin -p LPC4357 -v
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This will modify the binary file, appending the checksum to the correct place
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at the end of the vector table.
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The binary must now be converted to a hex file, which can be achieved using
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the srec_cat utility, which is part of the SRecord package (srecord.sourceforge.net)
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as follows:
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srec_cat nuttx.bin -binary -offset 0x1a000000 -o nuttx.hex -intel --line-length=44
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Now the hex file can be loaded using a debugger, and the code will execute from
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flash.
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STATUS
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======
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1. This configuration derives from the LPC4330 Xplorer configuration. In
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many cases there have been global substitutions for naming to the
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LPC4357 EVB without corresponding updates to the technical description.
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2014-11-27 17:28:32 +01:00
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Thus all technical details should be taken with a grain of salt. GPIO
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definitions may actually are remnants of the LPC4330-Xplorer that still
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need clean-up.
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