187 lines
9.3 KiB
C
187 lines
9.3 KiB
C
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/************************************************************************************
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* arch/arm/src/sama5/chip/sam_l2cc.h
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*
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_L2CC_H
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#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_L2CC_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip/sam_memorymap.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* L2CC Register Offsets ************************************************************/
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#define SAM_L2CC_IDR_OFFSET 0x0000 /* Cache ID Register */
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#define SAM_L2CC_TYPR_OFFSET 0x0004 /* Cache Type Register */
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#define SAM_L2CC_CR_OFFSET 0x0100 /* Control Register */
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#define SAM_L2CC_ACR_OFFSET 0x0104 /* Auxiliary Control Register */
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#define SAM_L2CC_TRCR_OFFSET 0x0108 /* Tag RAM Control Register */
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#define SAM_L2CC_DRCR_OFFSET 0x010c /* Data RAM Control Register */
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/* 0x0110-0x01fc Reserved */
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#define SAM_L2CC_ECR_OFFSET 0x0200 /* Event Counter Control Register */
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#define SAM_L2CC_ECFGR1_OFFSET 0x0204 /* Event Counter 1 Configuration Register */
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#define SAM_L2CC_ECFGR0_OFFSET 0x0208 /* Event Counter 0 Configuration Register */
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#define SAM_L2CC_EVR1_OFFSET 0x020c /* Event Counter 1 Value Register */
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#define SAM_L2CC_EVR0_OFFSET 0x0210 /* Event Counter 0 Value Register */
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#define SAM_L2CC_IMR_OFFSET 0x0214 /* Interrupt Mask Register */
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#define SAM_L2CC_MISR_OFFSET 0x0218 /* Masked Interrupt Status Register */
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#define SAM_L2CC_RISR_OFFSET 0x021c /* Raw Interrupt Status Register */
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#define SAM_L2CC_ICR_OFFSET 0x0220 /* Interrupt Clear Register */
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/* 0x0224-0x072c Reserved */
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#define SAM_L2CC_CSR_OFFSET 0x0730 /* Cache Synchronization Register */
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/* 0x0734-0x076c Reserved */
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#define SAM_L2CC_IPALR_OFFSET 0x0770 /* Invalidate Physical Address Line Register */
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/* 0x0774-0x0778 Reserved */
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#define SAM_L2CC_IWR_OFFSET 0x077c /* Invalidate Way Register */
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/* 0x0780-0x07af Reserved */
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#define SAM_L2CC_CPALR_OFFSET 0x07b0 /* Clean Physical Address Line Register */
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/* 0x07b4 Reserved */
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#define SAM_L2CC_CIR_OFFSET 0x07b8 /* Clean Index Register */
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#define SAM_L2CC_CWR_OFFSET 0x07bc /* Clean Way Register */
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/* 0x07c0-0x07ec Reserved */
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#define SAM_L2CC_CIPALR_OFFSET 0x07f0 /* Clean Invalidate Physical Address Line Register */
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/* 0x07f4 Reserved */
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#define SAM_L2CC_CIIR_OFFSET 0x07f8 /* Clean Invalidate Index Register */
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#define SAM_L2CC_CIWR_OFFSET 0x07fc /* Clean Invalidate Way Register */
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/* 0x0800-0x08fc Reserved */
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#define SAM_L2CC_DLKR_OFFSET 0x0900 /* Data Lockdown Register */
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#define SAM_L2CC_ILKR_OFFSET 0x0904 /* Instruction Lockdown Register */
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/* 0x0908-0x0f3c Reserved */
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#define SAM_L2CC_DCR_OFFSET 0x0f40 /* Debug Control Register */
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/* 0x0f44-0x0f5c Reserved */
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#define SAM_L2CC_PCR_OFFSET 0x0f60 /* Prefetch Control Register */
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/* 0x0f64-0x0f7c Reserved */
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#define SAM_L2CC_POWCR_OFFSET 0x0f80 /* Power Control Register */
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/* L2CC Register Addresses **********************************************************/
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#define SAM_L2CC_IDR (SAM_L2CC_VSECTION+SAM_L2CC_IDR_OFFSET)
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#define SAM_L2CC_TYPR (SAM_L2CC_VSECTION+SAM_L2CC_TYPR_OFFSET)
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#define SAM_L2CC_CR (SAM_L2CC_VSECTION+SAM_L2CC_CR_OFFSET)
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#define SAM_L2CC_ACR (SAM_L2CC_VSECTION+SAM_L2CC_ACR_OFFSET)
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#define SAM_L2CC_TRCR (SAM_L2CC_VSECTION+SAM_L2CC_TRCR_OFFSET)
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#define SAM_L2CC_DRCR (SAM_L2CC_VSECTION+SAM_L2CC_DRCR_OFFSET)
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#define SAM_L2CC_ECR (SAM_L2CC_VSECTION+SAM_L2CC_ECR_OFFSET)
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#define SAM_L2CC_ECFGR1 (SAM_L2CC_VSECTION+SAM_L2CC_ECFGR1_OFFSET)
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#define SAM_L2CC_ECFGR0 (SAM_L2CC_VSECTION+SAM_L2CC_ECFGR0_OFFSET)
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#define SAM_L2CC_EVR1 (SAM_L2CC_VSECTION+SAM_L2CC_EVR1_OFFSET)
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#define SAM_L2CC_EVR0 (SAM_L2CC_VSECTION+SAM_L2CC_EVR0_OFFSET)
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#define SAM_L2CC_IMR (SAM_L2CC_VSECTION+SAM_L2CC_IMR_OFFSET)
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#define SAM_L2CC_MISR (SAM_L2CC_VSECTION+SAM_L2CC_MISR_OFFSET)
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#define SAM_L2CC_RISR (SAM_L2CC_VSECTION+SAM_L2CC_RISR_OFFSET)
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#define SAM_L2CC_ICR (SAM_L2CC_VSECTION+SAM_L2CC_ICR_OFFSET)
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#define SAM_L2CC_CSR (SAM_L2CC_VSECTION+SAM_L2CC_CSR_OFFSET)
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#define SAM_L2CC_IPALR (SAM_L2CC_VSECTION+SAM_L2CC_IPALR_OFFSET)
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#define SAM_L2CC_IWR (SAM_L2CC_VSECTION+SAM_L2CC_IWR_OFFSET)
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#define SAM_L2CC_CPALR (SAM_L2CC_VSECTION+SAM_L2CC_CPALR_OFFSET)
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#define SAM_L2CC_CIR (SAM_L2CC_VSECTION+SAM_L2CC_CIR_OFFSET)
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#define SAM_L2CC_CWR (SAM_L2CC_VSECTION+SAM_L2CC_CWR_OFFSET)
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#define SAM_L2CC_CIPALR (SAM_L2CC_VSECTION+SAM_L2CC_CIPALR_OFFSET)
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#define SAM_L2CC_CIIR (SAM_L2CC_VSECTION+SAM_L2CC_CIIR_OFFSET)
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#define SAM_L2CC_CIWR (SAM_L2CC_VSECTION+SAM_L2CC_CIWR_OFFSET)
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#define SAM_L2CC_DLKR (SAM_L2CC_VSECTION+SAM_L2CC_DLKR_OFFSET)
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#define SAM_L2CC_ILKR (SAM_L2CC_VSECTION+SAM_L2CC_ILKR_OFFSET)
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#define SAM_L2CC_DCR (SAM_L2CC_VSECTION+SAM_L2CC_DCR_OFFSET)
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#define SAM_L2CC_PCR (SAM_L2CC_VSECTION+SAM_L2CC_PCR_OFFSET)
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#define SAM_L2CC_POWCR (SAM_L2CC_VSECTION+SAM_L2CC_POWCR_OFFSET)
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/* L2CC Register Bit Definitions ****************************************************/
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/* Cache ID Register */
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#define L2CC_IDR_
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/* Cache Type Register */
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#define L2CC_TYPR_
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/* Control Register */
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#define L2CC_CR_
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/* Auxiliary Control Register */
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#define L2CC_ACR_
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/* Tag RAM Control Register */
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#define L2CC_TRCR_
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/* Data RAM Control Register */
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#define L2CC_DRCR_
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/* Event Counter Control Register */
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#define L2CC_ECR_
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/* Event Counter 1 Configuration Register */
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#define L2CC_ECFGR1_
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/* Event Counter 0 Configuration Register */
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#define L2CC_ECFGR0_
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/* Event Counter 1 Value Register */
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#define L2CC_EVR1_
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/* Event Counter 0 Value Register */
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#define L2CC_EVR0_
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/* Interrupt Mask Register */
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#define L2CC_IMR_
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/* Masked Interrupt Status Register */
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#define L2CC_MISR_
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/* Raw Interrupt Status Register */
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#define L2CC_RISR_
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/* Interrupt Clear Register */
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#define L2CC_ICR_
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/* Cache Synchronization Register */
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#define L2CC_CSR_
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/* Invalidate Physical Address Line Register */
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#define L2CC_IPALR_
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/* Invalidate Way Register */
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#define L2CC_IWR_
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/* Clean Physical Address Line Register */
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#define L2CC_CPALR_
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/* Clean Index Register */
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#define L2CC_CIR_
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/* Clean Way Register */
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#define L2CC_CWR_
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/* Clean Invalidate Physical Address Line Register */
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#define L2CC_CIPALR_
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/* Clean Invalidate Index Register */
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#define L2CC_CIIR_
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/* Clean Invalidate Way Register */
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#define L2CC_CIWR_
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/* Data Lockdown Register */
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#define L2CC_DLKR_
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/* Instruction Lockdown Register */
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#define L2CC_ILKR_
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/* Debug Control Register */
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#define L2CC_DCR_
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/* Prefetch Control Register */
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#define L2CC_PCR_
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/* Power Control Register */
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#define L2CC_POWCR_
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#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_L2CC_H */
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