185 lines
7.0 KiB
C
185 lines
7.0 KiB
C
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/****************************************************************************
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* boards/arm/stm32/nucleo-g474re/include/board.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_STM32_NUCLEO-G474RE_INCLUDE_BOARD_H
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#define __BOARDS_ARM_STM32_NUCLEO-G474RE_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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#undef STM32_BOARD_XTAL /* Not installed by default */
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#define STM32_HSI_FREQUENCY 16000000ul /* 16MHz */
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#define STM32_LSI_FREQUENCY 32000 /* 32kHz */
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#undef STM32_HSE_FREQUENCY /* Not installed by default */
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#undef STM32_LSE_FREQUENCY /* Not available on this board */
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/* Main PLL Configuration.
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*
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* PLL source is HSI = 16MHz
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* PLLN = 85, PLLM = 4, PLLP = 10, PLLQ = 2, PLLR = 2
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*
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* f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM)
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* f(PLL_P) = f(VCO Clock) / PLLP
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* f(PLL_Q) = f(VCO Clock) / PLLQ
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* f(PLL_R) = f(VCO Clock) / PLLR
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*
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* Where:
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* 8 <= PLLN <= 127
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* 1 <= PLLM <= 16
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* PLLP = 2 through 31
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* PLLQ = 2, 4, 6, or 8
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* PLLR = 2, 4, 6, or 8
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*
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* Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R).
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* 64MHz <= f(VCO Clock) <= 344MHz.
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*
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* Given the above:
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*
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* f(VCO Clock) = HSI x PLLN / PLLM
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* = 16MHz x 85 / 4
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* = 340MHz
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*
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* PLLPCLK = f(VCO Clock) / PLLP
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* = 340MHz / 10
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* = 34MHz
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* (May be used for ADC)
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*
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* PLLQCLK = f(VCO Clock) / PLLQ
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* = 340MHz / 2
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* = 170MHz
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* (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to
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* 48MHz, may be used for USB, RNG.)
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*
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* PLLRCLK = f(VCO Clock) / PLLR
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* = 340MHz / 2
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* = 170MHz
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* (May be used for SYSCLK and most peripherals.)
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*/
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#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSI
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#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \
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RCC_PLLCFGR_PLLQEN | \
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RCC_PLLCFGR_PLLREN)
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#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(85)
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#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(4)
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#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10)
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#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2
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#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2
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#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85)
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#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10)
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#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2)
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#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2)
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/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */
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#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL
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#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
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#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY
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/* AHB clock (HCLK) is SYSCLK (170MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
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/* APB1 clock (PCLK1) is HCLK (170MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK
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#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY
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/* APB2 clock (PCLK2) is HCLK (170MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
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#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
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/* LED definitions **********************************************************/
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/* The NucleoG474RE board has one user LED.
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*
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* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in
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* any way. The following definitions are used to access individual LEDs.
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_LED1 0 /* LD2 (Green) */
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#define BOARD_NLEDS 1
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/* LED bits for use with board_userled_all() */
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#define BOARD_LED1_BIT (1 << BOARD_LED1)
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/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 user LEDs
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* on the board. The following definitions describe how NuttX controls the
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* LEDs:
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*
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* |--------------------|-------------------------|------------|
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* | SYMBOL | Meaning | LED states |
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* |--------------------|-------------------------|------------|
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* | LED_STARTED | NuttX has been started | 0 0 0 0 |
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* | LED_HEAPALLOCATE | Heap has been allocated | 0 0 0 0 |
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* | LED_IRQSENABLED | Interrupts enabled | 0 0 0 0 |
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* | LED_STACKCREATED | Idle stack created | 1 0 0 0 |
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* | LED_INIRQ | In an interrupt | No change |
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* | LED_SIGNAL | In a signal handler | No change |
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* | LED_ASSERTION | An assertion failed | No change |
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* | LED_PANIC | The system has crashed | 0 B 0 0 |
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* | LED_IDLE | STM32 is is sleep mode | Not used |
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* |--------------------|-------------------------|------------|
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*
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* LED states legend:
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* 0 = off
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* 1 = on
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* B = blink
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*/
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#define LED_STARTED 0
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#define LED_HEAPALLOCATE 0
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#define LED_IRQSENABLED 0
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#define LED_STACKCREATED 1
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#define LED_INIRQ 2
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#define LED_SIGNAL 2
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#define LED_ASSERTION 2
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#define LED_PANIC 3
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/* Button definitions *******************************************************/
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/* Alternate function pin selections ****************************************/
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/* USART3 (ST LINK V3E Virtual Console) */
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#define GPIO_USART3_TX GPIO_USART3_TX_3 /* PC10 */
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#define GPIO_USART3_RX GPIO_USART3_RX_3 /* PC11 */
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/* Pin Multiplexing Disambiguation ******************************************/
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#endif /* __BOARDS_ARM_STM32_NUCLEO_G474RE_INCLUDE_BOARD_H */
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