2023-09-16 12:11:01 +02:00
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/****************************************************************************
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* boards/arm/at32/at32f437-mini/include/board.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_AT32_AT32F437_MINI_INCLUDE_BOARD_H
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#define __BOARDS_ARM_AT32_AT32F437_MINI_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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# include <stdbool.h>
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#endif
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/* Do not include at32-specific header files here */
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* The AT32F437-MINI board features a single 8MHz crystal.
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* Space is provided for a 32kHz RTC backup crystal, but it is not stuffed.
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*
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* This is the canonical configuration:
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* System Clock source : PLL (HSE)
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* SYSCLK(Hz) : 288000000 Determined by PLL
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* configuration
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* HCLK(Hz) : 288000000 (AT32_RCC_CFGR_HPRE)
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* AHB Prescaler : 1 (AT32_RCC_CFGR_HPRE)
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* APB1 Prescaler : 2 (AT32_RCC_CFGR_PPRE1)
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* APB2 Prescaler : 2 (AT32_RCC_CFGR_PPRE2)
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* HSE Frequency(Hz) : 8000000 (AT32_BOARD_XTAL)
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* PLLM : 1 (AT32_PLLCFG_PLLMS)
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* PLLN : 144 (AT32_PLLCFG_PLLNS)
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* PLLP : 4 (AT32_PLLCFG_PLLFR)
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* Main regulator output voltage : Scale1 mode Needed for high speed
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* SYSCLK
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* Prefetch Buffer : OFF
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* Instruction cache : ON
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* Data cache : ON
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* Require 48MHz for USB OTG FS, : Enabled
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* SDIO clock
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*/
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/* HSI - 48 MHz RC factory-trimmed
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* LSI - 40 KHz RC
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* HSE - On-board crystal frequency is 8MHz
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* LSE - 32.768 kHz
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*/
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#define AT32_BOARD_XTAL 8000000ul
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#define AT32_HSI_FREQUENCY 48000000ul
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#define AT32_LSI_FREQUENCY 40000
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#define AT32_HSE_FREQUENCY AT32_BOARD_XTAL
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#define AT32_LSE_FREQUENCY 32768
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/* Main PLL Configuration.
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*
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* PLL source is HSE
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*
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* FREQUENCY = HSE * AT32_PLLCFG_PLLN / (AT32_PLLCFG_PLLM * AT32_PLLCFG_PLLP)
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*
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*/
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#define AT32_PLLCFG_PLLM CRM_PLL_CFG_PLL_MS(1)
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#define AT32_PLLCFG_PLLN CRM_PLL_CFG_PLL_NS(144)
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#define AT32_PLLCFG_PLLP CRM_PLL_CFG_PLL_FR_4
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#define AT32_SYSCLK_FREQUENCY 288000000ul
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/* AHB clock (HCLK) is SYSCLK (288MHz) */
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#define AT32_HCLK_FREQUENCY AT32_SYSCLK_FREQUENCY /* HCLK = SYSCLK / 1 */
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/* APB1 clock (PCLK1) is HCLK/2 (144MHz) */
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#define AT32_PCLK1_FREQUENCY (AT32_HCLK_FREQUENCY/2) /* PCLK1 = HCLK / 2 */
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/* Timers driven from APB1 will be twice PCLK1 */
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#define AT32_APB1_TIM2_CLKIN (2*AT32_PCLK1_FREQUENCY)
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#define AT32_APB1_TIM3_CLKIN (2*AT32_PCLK1_FREQUENCY)
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#define AT32_APB1_TIM4_CLKIN (2*AT32_PCLK1_FREQUENCY)
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#define AT32_APB1_TIM5_CLKIN (2*AT32_PCLK1_FREQUENCY)
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#define AT32_APB1_TIM6_CLKIN (2*AT32_PCLK1_FREQUENCY)
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#define AT32_APB1_TIM7_CLKIN (2*AT32_PCLK1_FREQUENCY)
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#define AT32_APB1_TIM12_CLKIN (2*AT32_PCLK1_FREQUENCY)
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#define AT32_APB1_TIM13_CLKIN (2*AT32_PCLK1_FREQUENCY)
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#define AT32_APB1_TIM14_CLKIN (2*AT32_PCLK1_FREQUENCY)
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/* APB2 clock (PCLK2) is HCLK/2 (144MHz) */
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#define AT32_PCLK2_FREQUENCY (AT32_HCLK_FREQUENCY/2) /* PCLK2 = HCLK / 2 */
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/* Timers driven from APB2 will be twice PCLK2 */
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#define AT32_APB2_TIM1_CLKIN (2*AT32_PCLK2_FREQUENCY)
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#define AT32_APB2_TIM8_CLKIN (2*AT32_PCLK2_FREQUENCY)
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#define AT32_APB2_TIM9_CLKIN (2*AT32_PCLK2_FREQUENCY)
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#define AT32_APB2_TIM10_CLKIN (2*AT32_PCLK2_FREQUENCY)
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#define AT32_APB2_TIM11_CLKIN (2*AT32_PCLK2_FREQUENCY)
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#define AT32_APB2_TIM20_CLKIN (2*AT32_PCLK2_FREQUENCY)
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
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* otherwise frequency is 2xAPBx.
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* Note: TIM1,8 are on APB2, others on APB1
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*/
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#define BOARD_TIM1_FREQUENCY (AT32_HCLK_FREQUENCY)
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#define BOARD_TIM2_FREQUENCY (AT32_HCLK_FREQUENCY)
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#define BOARD_TIM3_FREQUENCY (AT32_HCLK_FREQUENCY)
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#define BOARD_TIM4_FREQUENCY (AT32_HCLK_FREQUENCY)
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#define BOARD_TIM5_FREQUENCY (AT32_HCLK_FREQUENCY)
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#define BOARD_TIM6_FREQUENCY (AT32_HCLK_FREQUENCY)
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#define BOARD_TIM7_FREQUENCY (AT32_HCLK_FREQUENCY)
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#define BOARD_TIM8_FREQUENCY (AT32_HCLK_FREQUENCY)
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/* SDIO dividers. Note that slower clocking is required when DMA is disabled
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* in order to avoid RX overrun/TX underrun errors due to delayed responses
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* to service FIFOs in interrupt driven mode. These values have not been
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* tuned!!!
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*
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* SDIOCLK=AT32_HCLK_FREQUENCY, SDIO_CK=SDIOCLK/(1438+2)=200 KHz
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*/
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#define SDIO_INIT_CLKDIV (1438 << SDIO_CLKCR_CLKDIV_SHIFT)
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/* DMA ON: SDIOCLK=AT32_HCLK_FREQUENCY, SDIO_CK=SDIOCLK/(10+2)=24 MHz
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* DMA OFF: SDIOCLK=AT32_HCLK_FREQUENCY, SDIO_CK=SDIOCLK/(22+2)=12 MHz
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*/
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#ifdef CONFIG_SDIO_DMA
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# define SDIO_MMCXFR_CLKDIV (10 << SDIO_CLKCR_CLKDIV_SHIFT)
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#else
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# define SDIO_MMCXFR_CLKDIV (22 << SDIO_CLKCR_CLKDIV_SHIFT)
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#endif
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/* DMA ON: SDIOCLK=AT32_HCLK_FREQUENCY, SDIO_CK=SDIOCLK/(10+2)=24 MHz
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* DMA OFF: SDIOCLK=AT32_HCLK_FREQUENCY, SDIO_CK=SDIOCLK/(22+2)=12 MHz
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*/
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#ifdef CONFIG_SDIO_DMA
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# define SDIO_SDXFR_CLKDIV (10 << SDIO_CLKCR_CLKDIV_SHIFT)
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#else
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# define SDIO_SDXFR_CLKDIV (22 << SDIO_CLKCR_CLKDIV_SHIFT)
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#endif
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#define GPIO_SDIO_CMD GPIO_SDIO_CMD_1
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#define GPIO_SDIO_CK GPIO_SDIO_CK_1
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#define GPIO_SDIO_D0 GPIO_SDIO_D0_3
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#define GPIO_SDIO_D1 GPIO_SDIO_D1_1
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#define GPIO_SDIO_D2 GPIO_SDIO_D2_1
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#define GPIO_SDIO_D3 GPIO_SDIO_D3_1
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/* LED definitions **********************************************************/
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/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs
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* in any way. The following definitions are used to access individual LEDs.
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_LED1 0
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#define BOARD_LED2 1
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#define BOARD_NLEDS 2
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#define BOARD_LED_GREEN BOARD_LED1
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#define BOARD_LED_ORANGE BOARD_LED2
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/* LED bits for use with board_userled_all() */
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#define BOARD_LED1_BIT (1 << BOARD_LED1)
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#define BOARD_LED2_BIT (1 << BOARD_LED2)
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/* If CONFIG_ARCH_LEDS is defined, then NuttX will control the 2 LEDs on
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* board the AT32F437-MINI. The following definitions describe how NuttX
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* controls the LEDs:
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*
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* SYMBOL Meaning LED state
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* LED1 LED2
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* ------------------- ----------------------- -------- --------
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* LED_STARTED NuttX has been started OFF OFF
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* LED_HEAPALLOCATE Heap has been allocated OFF OFF
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* LED_IRQSENABLED Interrupts enabled OFF OFF
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* LED_STACKCREATED Idle stack created ON OFF
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* LED_INIRQ In an interrupt No change
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* LED_SIGNAL In a signal handler No change
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* LED_ASSERTION An assertion failed No change
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* LED_PANIC The system has crashed OFF Blinking
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* LED_IDLE AT32 is is sleep mode Not used
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*/
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#define LED_STARTED 0
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#define LED_HEAPALLOCATE 0
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#define LED_IRQSENABLED 0
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#define LED_STACKCREATED 1
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#define LED_INIRQ 2
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#define LED_SIGNAL 2
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#define LED_ASSERTION 2
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#define LED_PANIC 3
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/* USB
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* pll clock = AT32_HCLK_FREQUENCY(288MHz)
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* usb clock use pll
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* usb_clk = 288/6 = 48MHz
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*/
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#define USB_CONFIG_USBDIV (CRM_MISC2_USBDIV_6P0)
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/* USART1 */
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# define GPIO_USART1_TX GPIO_USART1_TX_1
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# define GPIO_USART1_RX GPIO_USART1_RX_1
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/* USART2 for RS485 */
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# define GPIO_USART2_TX GPIO_USART2_TX_2
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# define GPIO_USART2_RX GPIO_USART2_RX_2
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# define GPIO_USART2_RS485_DIR (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_DRV_STRONG |\
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GPIO_OUTPUT_CLEAR | GPIO_PORTD | GPIO_PIN4)
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/* SPI1 */
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#define GPIO_SPI1_MISO GPIO_SPI1_MISO_2
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#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_2
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#define GPIO_SPI1_SCK GPIO_SPI1_SCK_2
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/* CAN */
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#define GPIO_CAN1_RX GPIO_CAN1_RX_3
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#define GPIO_CAN1_TX GPIO_CAN1_TX_3
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/* ETH */
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#define GPIO_ETH_RMII_TX_EN GPIO_ETH_RMII_TX_EN_1 /* PB11 */
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#define GPIO_ETH_RMII_TXD0 GPIO_ETH_RMII_TXD0_1 /* PB12 */
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#define GPIO_ETH_RMII_TXD1 GPIO_ETH_RMII_TXD1_1 /* PB13 */
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/* I2C */
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#define GPIO_I2C3_SCL GPIO_I2C3_SCL_2
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#define GPIO_I2C3_SDA GPIO_I2C3_SDA_2
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/* PWM */
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#define GPIO_TIM3_CH1OUT GPIO_TIM3_CH1OUT_4
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#define GPIO_TIM20_CH1OUT GPIO_TIM20_CH1OUT_2
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#endif /* __BOARDS_ARM_AT32_AT32F437-MINN_INCLUDE_BOARD_H */
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