2016-10-16 17:47:07 +02:00
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/****************************************************************************
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* arch/risc-v/include/rv32im/csr.h
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*
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* Copyright (C) 2016 Ken Pettit. All rights reserved.
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* Author: Ken Pettit <pettitkd@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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2020-04-05 23:00:04 +02:00
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/* This file should never be included directly but, rather, only indirectly
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2016-10-16 17:47:07 +02:00
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* through nuttx/irq.h
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*/
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#ifndef __ARCH_RISCV_INCLUDE_RV32IM_CSR_H
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#define __ARCH_RISCV_INCLUDE_RV32IM_CSR_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Machine Information Registers */
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#define CSR_MISA 0xF10
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#define CSR_MVENDORID 0xF11
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#define CSR_MARCHID 0xF12
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#define CSR_MIMPID 0xF13
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#define CSR_MHARTID 0xF14
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/* Machine Trap Registers */
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#define CSR_MSTATUS 0x300
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#define CSR_MTDELEG 0x302
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#define CSR_MIE 0x304
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#define CSR_MTVEC 0x305
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#define CSR_MIVEC 0x30f
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/* Machine Trap Handling */
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#define CSR_MSCRATCH 0x340
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#define CSR_MEPC 0x341
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#define CSR_MCAUSE 0x342
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#define CSR_MBADADDR 0x343
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#define CSR_MIP 0x344
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/* Machine Timers and Counters */
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#define CSR_CYCLE 0xF00
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#define CSR_TIME 0xF01
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#define CSR_INSTRET 0xF02
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#define CSR_CYCLEH 0xF80
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#define CSR_TIMEH 0xF81
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#define CSR_INSTRETH 0xF82
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/* Debug interface CSRs */
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#define CSR_DCSR 0x7B0
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#define CSR_DPC 0x7B1
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#define CSR_DSCRATCH 0x7B2
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Variables
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#endif /* __ARCH_RISCV_INCLUDE_RV32IM_CSR_H */
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