nuttx/arch/sim/src/up_setjmp_arm.S

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/****************************************************************************
* arch/sim/src/up_setjmp_arm.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
*
* Extracted from the MUSL C-library by Bitbucket user nbkolchin. The MUSL
* C library has a compatible MIT license and is released here under the
* NuttX 3-clause BSD license:
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
.syntax unified
.global up_setjmp
.type up_setjmp,%function
up_setjmp:
mov ip,r0
stmia ip!,{v1,v2,v3,v4,v5,v6,sl,fp}
mov r2,sp
stmia ip!,{r2,lr}
mov r0,#0
#if 0
adr r1,1f
ldr r2,1f
ldr r1,[r1,r2]
tst r1,#0x260
beq 3f
tst r1,#0x20
beq 2f
stc p2, cr4, [ip], #48
2: tst r1,#0x40
beq 2f
.fpu vfp
vstmia ip!, {d8-d15}
.fpu softvfp
.eabi_attribute 10, 0
.eabi_attribute 27, 0
2: tst r1,#0x200
beq 3f
stcl p1, cr10, [ip], #8
stcl p1, cr11, [ip], #8
stcl p1, cr12, [ip], #8
stcl p1, cr13, [ip], #8
stcl p1, cr14, [ip], #8
stcl p1, cr15, [ip], #8
#endif
3: bx lr
.syntax unified
.global up_longjmp
.type up_longjmp,%function
up_longjmp:
mov ip,r0
movs r0,r1
moveq r0,#1
ldmia ip!, {v1,v2,v3,v4,v5,v6,sl,fp}
ldmia ip!, {r2,lr}
mov sp,r2
#if 0
.fpu vfp
vldmia ip!, {d8-d15}
.fpu softvfp
.eabi_attribute 10, 0
.eabi_attribute 27, 0
2: tst r1,#0x200
beq 3f
ldcl p1, cr10, [ip], #8
ldcl p1, cr11, [ip], #8
ldcl p1, cr12, [ip], #8
ldcl p1, cr13, [ip], #8
ldcl p1, cr14, [ip], #8
ldcl p1, cr15, [ip], #8
#endif
3: bx lr