2009-05-08 23:12:33 +02:00
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/****************************************************************************
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* arch/arm/src/lm3s/lm3s_irq.c
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* arch/arm/src/chip/lm3s_irq.c
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <nuttx/irq.h>
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#include "up_arch.h"
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#include "os_internal.h"
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#include "up_internal.h"
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2009-05-13 16:29:22 +02:00
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#include "lm3s_internal.h"
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2009-05-08 23:12:33 +02:00
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/****************************************************************************
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* Definitions
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****************************************************************************/
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2009-05-13 00:15:49 +02:00
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#define DEFPRIORITY32 \
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(NVIC_SYSH_PRIORITY_DEFAULT << 24 |\
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NVIC_SYSH_PRIORITY_DEFAULT << 16 |\
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NVIC_SYSH_PRIORITY_DEFAULT << 8 |\
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NVIC_SYSH_PRIORITY_DEFAULT)
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2009-05-08 23:12:33 +02:00
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/****************************************************************************
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* Public Data
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****************************************************************************/
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uint32 *current_regs;
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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2009-05-13 00:15:49 +02:00
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/****************************************************************************
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* Name: lml3s_irqinfo
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*
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* Description:
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* Given an IRQ number, provide the register and bit setting to enable or
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* disable the irq.
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*
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****************************************************************************/
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static int lml3s_irqinfo(int irq, uint32 *regaddr, uint32 *bit)
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{
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DEBUGASSERT(irq >= LMSB_IRQ_MPU && irq < NR_IRQS);
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/* Check for external interrupt */
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if (irq >= LM3S_IRQ_INTERRUPTS)
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{
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if (irq < LM3S_IRQ_INTERRUPTS + 32)
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{
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*regaddr = NVIC_IRQ0_31_ENABLE;
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*bit = 1 << (irq - LM3S_IRQ_INTERRUPTS);
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}
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else if (irq < NR_IRQS)
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{
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*regaddr = NVIC_IRQ32_63_ENABLE;
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*bit = 1 << (irq - LM3S_IRQ_INTERRUPTS - 32);
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}
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else
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{
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return ERROR; /* Invalid interrupt */
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}
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}
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/* Handler processor exceptions. Only a few can be disabled */
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else
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{
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*regaddr = NVIC_SYSHCON;
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if (irq == LMSB_IRQ_MPU)
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{
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*bit = NVIC_SYSHCON_MEMFAULTENA;
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}
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else if (irq == LMSB_IRQ_BUSFAULT)
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{
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*bit = NVIC_SYSHCON_BUSFAULTENA;
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}
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else if (irq == LMSB_IRQ_USAGEFAULT)
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{
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*bit = NVIC_SYSHCON_USGFAULTENA;
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}
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else if (irq == LMSB_IRQ_SYSTICK)
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{
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*regaddr = NVIC_SYSTICK_CTRL;
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*bit = NVIC_SYSTICK_CTRL_ENABLE;
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}
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else
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{
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return ERROR; /* Invalid or unsupported exception */
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}
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}
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return OK;
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}
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2009-05-08 23:12:33 +02:00
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/****************************************************************************
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* Public Funtions
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****************************************************************************/
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/****************************************************************************
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* Name: up_irqinitialize
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****************************************************************************/
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void up_irqinitialize(void)
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{
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2009-05-13 00:15:49 +02:00
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/* Disable all interrupts */
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putreg32(0, NVIC_IRQ0_31_ENABLE);
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putreg32(0, NVIC_IRQ32_63_ENABLE);
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/* Set all interrrupts (and exceptions) to the default priority */
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putreg32(DEFPRIORITY32, NVIC_IRQ0_3_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_IRQ4_7_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_IRQ8_11_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_IRQ12_15_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_IRQ16_19_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_IRQ20_23_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_IRQ24_27_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_IRQ28_31_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_IRQ32_35_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_IRQ36_39_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_IRQ40_43_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_IRQ44_47_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_IRQ48_51_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_IRQ52_55_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_IRQ56_59_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_IRQ60_63_PRIORITY);
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2009-05-08 23:12:33 +02:00
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/* currents_regs is non-NULL only while processing an interrupt */
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current_regs = NULL;
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/* Attach all processor exceptions (except reset and sys tick) */
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#ifdef CONFIG_DEBUG
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irq_attach(LMSB_IRQ_NMI, lm3s_nmi);
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irq_attach(LMSB_IRQ_HARDFAULT, lm3s_hardfault);
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irq_attach(LMSB_IRQ_MPU, lm3s_mpu);
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irq_attach(LMSB_IRQ_BUSFAULT, lm3s_busfault);
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irq_attach(LMSB_IRQ_USAGEFAULT, lm3s_usagefault);
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irq_attach(LMSB_IRQ_SVCALL, lm3s_svcall);
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irq_attach(LMSB_IRQ_DBGMONITOR, lm3s_dbgmonitor);
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irq_attach(LMSB_IRQ_PENDSV, lm3s_pendsv);
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irq_attach(LMSB_IRQ_RESERVED, lm3s_reserved);
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#endif
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#ifndef CONFIG_SUPPRESS_INTERRUPTS
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/* Initialize FIQs */
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#ifdef CONFIG_ARCH_FIQ
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up_fiqinitialize();
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#endif
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/* And finally, enable interrupts */
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irqrestore(0);
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#endif
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}
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/****************************************************************************
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* Name: up_disable_irq
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*
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* Description:
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* Disable the IRQ specified by 'irq'
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*
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****************************************************************************/
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void up_disable_irq(int irq)
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{
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2009-05-13 00:15:49 +02:00
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uint32 regaddr;
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uint32 regval;
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uint32 bit;
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if (lml3s_irqinfo(irq, ®addr, &bit) == 0)
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{
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/* Clear the appropriate bit in the register to enable the interrupt */
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regval = getreg32(regaddr);
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regval &= ~bit;
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putreg32(regval, regaddr);
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}
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2009-05-08 23:12:33 +02:00
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}
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/****************************************************************************
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* Name: up_enable_irq
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*
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* Description:
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* Enable the IRQ specified by 'irq'
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*
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****************************************************************************/
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void up_enable_irq(int irq)
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{
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2009-05-13 00:15:49 +02:00
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uint32 regaddr;
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uint32 regval;
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uint32 bit;
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if (lml3s_irqinfo(irq, ®addr, &bit) == 0)
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{
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/* Set the appropriate bit in the register to enable the interrupt */
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regval = getreg32(regaddr);
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regval |= bit;
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putreg32(regval, regaddr);
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}
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2009-05-08 23:12:33 +02:00
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}
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/****************************************************************************
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* Name: up_maskack_irq
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*
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* Description:
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* Mask the IRQ and acknowledge it
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*
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****************************************************************************/
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void up_maskack_irq(int irq)
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{
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2009-05-13 00:15:49 +02:00
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up_disable_irq(irq);
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2009-05-08 23:12:33 +02:00
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}
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2009-05-13 00:15:49 +02:00
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/****************************************************************************
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* Name: up_prioritize_irq
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*
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* Description:
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* Set the priority of an IRQ.
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*
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* Since this API is not supported on all architectures, it should be
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* avoided in common implementations where possible.
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*
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****************************************************************************/
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#ifdef CONFIG_ARCH_IRQPRIO
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int up_prioritize_irq(int irq, int priority)
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{
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uint32 regaddr;
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uint32 regval;
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int shift;
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DEBUGASSERT(irq >= LMSB_IRQ_MPU && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MAX);
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if (irq < LM3S_IRQ_INTERRUPTS)
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{
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regaddr = NVIC_SYSH_PRIORITY(irq);
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}
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else
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{
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irq -= LM3S_IRQ_INTERRUPTS;
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regaddr = NVIC_IRQ_PRIORITY(irq);
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}
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regval = getreg32(regaddr);
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shift = ((irq & 3) << 3);
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regval &= ~(0xff << shift);
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regval |= (priority << shift);
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putreg32(regval, regaddr);
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return OK;
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}
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#endif
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2009-05-08 23:12:33 +02:00
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/****************************************************************************
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* Name: lm3s_nmi, lm3s_hardfault, lm3s_mpu, lm3s_busfault, lm3s_usagefault,
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* lm3s_svcall, lm3s_dbgmonitor, lm3s_pendsv, lm3s_reserved
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*
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* Description:
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* Handlers for various execptions. None are handler and all are fatal
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* error conditions.
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*
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****************************************************************************/
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#ifdef CONFIG_DEBUG
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int lm3s_nmi(int irq, FAR void *context)
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{
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(void)irqsave();
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dbg("PANIC!!! NMI received\n");
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PANIC(OSERR_UNEXPECTEDISR);
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return 0;
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}
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int lm3s_hardfault(int irq, FAR void *context)
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{
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(void)irqsave();
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dbg("PANIC!!! Hard fault received\n");
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PANIC(OSERR_UNEXPECTEDISR);
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return 0;
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}
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int lm3s_mpu(int irq, FAR void *context)
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{
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(void)irqsave();
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dbg("PANIC!!! MPU interrupt received\n");
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PANIC(OSERR_UNEXPECTEDISR);
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return 0;
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}
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int lm3s_busfault(int irq, FAR void *context)
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{
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(void)irqsave();
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dbg("PANIC!!! Bus fault recived\n");
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PANIC(OSERR_UNEXPECTEDISR);
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return 0;
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}
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int lm3s_usagefault(int irq, FAR void *context)
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{
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(void)irqsave();
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dbg("PANIC!!! Usage fault received\n");
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PANIC(OSERR_UNEXPECTEDISR);
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return 0;
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}
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int lm3s_svcall(int irq, FAR void *context)
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{
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(void)irqsave();
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dbg("PANIC!!! SVCALL received\n");
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PANIC(OSERR_UNEXPECTEDISR);
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return 0;
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}
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int lm3s_dbgmonitor(int irq, FAR void *context)
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{
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(void)irqsave();
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dbg("PANIC!!! Debug Monitor receieved\n");
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PANIC(OSERR_UNEXPECTEDISR);
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return 0;
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}
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int lm3s_pendsv(int irq, FAR void *context)
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{
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(void)irqsave();
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dbg("PANIC!!! PendSV received\n");
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PANIC(OSERR_UNEXPECTEDISR);
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return 0;
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}
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|
|
|
|
|
|
|
int lm3s_reserved(int irq, FAR void *context)
|
|
|
|
{
|
|
|
|
(void)irqsave();
|
|
|
|
dbg("PANIC!!! Reserved interrupt\n");
|
|
|
|
PANIC(OSERR_UNEXPECTEDISR);
|
|
|
|
return 0;
|
|
|
|
}
|
2009-05-13 16:29:22 +02:00
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#endif
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