58 lines
2.2 KiB
C
58 lines
2.2 KiB
C
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/****************************************************************************
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* arch/arm/src/stm32wl5/chip.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32WL5_CHIP_H
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#define __ARCH_ARM_SRC_STM32WL5_CHIP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/* Include the memory map and the chip definitions file.
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* Other chip hardware files should then include this file for the proper
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* setup.
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*/
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#include <arch/irq.h>
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#include <arch/stm32wl5/chip.h>
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#include "hardware/stm32wl5_pinmap.h"
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#include "hardware/stm32wl5_memorymap.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* If the common ARMv7-M vector handling logic is used, then it expects the
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* following definition in this file that provides the number of supported
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* external interrupts which, for this architecture, is provided in the
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* arch/stm32wl5/chip.h header file.
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*/
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#define ARMV7M_PERIPHERAL_INTERRUPTS STM32WL5_IRQ_NEXTINTS
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/* Cache line sizes (in bytes) for the STM32WL5 */
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#define ARMV7M_DCACHE_LINESIZE 0 /* no cache */
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#define ARMV7M_ICACHE_LINESIZE 0 /* no cache */
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#endif /* __ARCH_ARM_SRC_STM32WL5_CHIP_H */
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