46 lines
1.4 KiB
ReStructuredText
46 lines
1.4 KiB
ReStructuredText
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==================
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Bouffalo Lab BL808
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==================
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`Bouffalo Lab BL808 <https://github.com/bouffalolab/bl_docs/tree/main/BL808_RM/en>`_ is a 64-bit / 32-bit RISC-V SoC with 3 RISC-V Cores:
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- **D0 Multimedia Core:** T-Head C906 480 MHz 64-bit RISC-V CPU
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- RV64IMAFCV
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- Level 1 Instruction and Data Cache (Harvard architecture)
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- Sv39 Memory Management Unit
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- jTLB (128 entries)
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- AXI 4.0 128-bit master interface
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- Core Local Interrupt (CLINT) and Platform-Level Interrupt Controller (PLIC)
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- 80 External Interrupt Sources
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- BHT (8K) and BTB
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- RISC-V PMP (8 configurable areas)
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- **M0 Wireless Core:** T-Head E907 320 MHz 32-bit RISC-V CPU
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- RV32IMAFCP
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- 32-bit / 16-bit Mixed Instruction Set
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- RISC-V Machine Mode and User Mode
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- 32 x 32-bit Integer General Purpose Registers (GPR)
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- 32 x 32-bit / 64-bit Floating-Point GPRs
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- AXI 4.0 main device interface and AHB 5.0 peripheral interface
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- Instruction and Data Cache
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- **LP Low Power Core:** T-Head E902 150 MHz 32-bit RISC-V CPU
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- RV32E[M]C
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- **RAM:** Embedded 64 MB PSRAM
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- **Wireless:** 2.4 GHz 1T1R WiFi 802.11 b/g/n, Bluetooth 5.2, Zigbee
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- **Ethernet:** 10 / 100 Mbps
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- **USB:** USB 2.0 OTG
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- **Audio:** Microphone and Speaker
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- **Video Input:** Dual-lane MIPI CSI
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- **Peripherals:** UART, SPI, I2C, PWM, SDH, EMAC, USB
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Supported Boards
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================
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.. toctree::
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:glob:
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:maxdepth: 1
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boards/*/*
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