2015-08-25 17:10:12 +02:00
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/************************************************************************************
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* drivers/mtd/st25fl1.c
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* Driver for QuadSPI-based S25FL116K, S25FL132K, and S25L164K
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <string.h>
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#include <assert.h>
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#include <errno.h>
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#include <debug.h>
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#include <nuttx/kmalloc.h>
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#include <nuttx/fs/ioctl.h>
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2015-08-26 01:20:54 +02:00
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#include <nuttx/spi/qspi.h>
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2015-08-25 17:10:12 +02:00
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#include <nuttx/mtd/mtd.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Configuration ********************************************************************/
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2015-08-30 02:54:20 +02:00
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/* QuadSPI Mode. Per data sheet, either Mode 0 or Mode 3 may be used. */
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2015-08-25 17:10:12 +02:00
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2015-08-26 01:20:54 +02:00
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#ifndef CONFIG_ST25FL1_QSPIMODE
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# define CONFIG_ST25FL1_QSPIMODE QSPIDEV_MODE0
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2015-08-25 17:10:12 +02:00
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#endif
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2015-08-30 02:54:20 +02:00
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/* QuadSPI Frequency per data sheet::
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*
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* – Normal Read (Serial):
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* 50 MHz clock rate (-40°C to +85°C/105°C)
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* 45 MHz clock rate (-40°C to +125°C)
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* – Fast Read (Serial):
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* 108 MHz clock rate (-40°C to +85°C/105°C)
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* 97 MHz clock rate (-40°C to +125°C)
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* – Dual Read:
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* 108 MHz clock rate (-40°C to +85°C/105°C)
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* 97 MHz clock rate (-40°C to +125°C)
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* – Quad Read:
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* 108 MHz clock rate (-40°C to +85°C/105°C)
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* 97 MHz clock rate for S25FL164K (-40°C to +125°C)
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*
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* Table 5.8:
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* - Clock frequency for all SPI commands except for Read Data
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* command (0x03) and Fast Read command (0x0b): 108 MHz
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* - Clock frequency for Read Data command (0x03): 50 MHz
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* - Clock frequency for all Fast Read commands SIO and MIO: 108 MHz
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*
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* In this implementation, only "Quad" reads are performed.
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*/
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2015-08-25 17:10:12 +02:00
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2015-08-30 02:54:20 +02:00
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#ifndef CONFIG_ST25FL1_QSPI_FREQUENCY
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# define CONFIG_ST25FL1_QSPI_FREQUENCY 108000000
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2015-08-25 17:10:12 +02:00
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#endif
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/* ST25FL1 Commands *****************************************************************/
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/* Configuration, Status, Erase, Program Commands ***********************************/
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/* Command Value Description: */
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/* Data sequence */
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#define ST25FL1_READ_STATUS1 0x05 /* Read status register 1: *
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* 0x05 | SR1 */
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#define ST25FL1_READ_STATUS2 0x35 /* Read status register 2: *
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* 0x35 | SR2 */
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#define ST25FL1_READ_STATUS3 0x33 /* Read status register 3: *
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* 0x33 | SR3 */
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#define ST25FL1_WRITE_ENABLE 0x06 /* Write enable: *
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* 0x06 */
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#define ST25FL1_VWRITE_ENABLE 0x50 /* Write enable for volatile status: *
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* 0x50 */
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#define ST25FL1_WRITE_DISABLE 0x04 /* Write disable command code: *
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* 0x04 */
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#define ST25FL1_WRITE_STATUS 0x01 /* Write status register: *
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* 0x01 | SR1 | SR2 | SR3 */
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#define ST25FL1_WRAP_ENABLE 0x77 /* Set Burst with Wrap: *
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* 0x77 | xx | xx | xx | SR3 */
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#define ST25FL1_UNPROTECT_SECTOR 0x39 /* Set Block / Pointer Protection: *
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* 0x39 | ADDR(MS) | ADDR(MID) | xx */
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#define ST25FL1_PAGE_PROGRAM 0x02 /* Page Program: *
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* 0x02 | ADDR(MS) | ADDR(MID) | *
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* ADDR(LS) | data */
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#define ST25FL1_SECTOR_ERASE 0x20 /* Sector Erase (4 kB) *
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* 0x02 | ADDR(MS) | ADDR(MID) | *
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* ADDR(LS) */
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#define ST25FL1_BLOCK_ERASE 0xd8 /* Block Erase (64 kB): *
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* 0x02 | ADDR(MS) | ADDR(MID) | *
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* ADDR(LS) */
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#define ST25FL1_CHIP_ERASE_1 0x60 /* Chip Erase 1: *
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* 0x60 */
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#define ST25FL1_CHIP_ERASE_2 0xc7 /* Chip Erase 2: *
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* 0xc7 */
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#define ST25FL1_ERASE_PROG_SUSPEND 0x75 /* Erase / Program Suspend: *
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* 0x75 */
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#define ST25FL1_ERASE_PROG_RESUME 0x7a /* Erase / Program Resume: *
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* 0x7a */
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/* Read Commands ********************************************************************/
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/* Command Value Description: */
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/* Data sequence */
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#define ST25FL1_READ_DATA 0x03 /* Read Data: *
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* 0x03 | ADDR(MS) | ADDR(MID) | *
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* ADDR(LS) | data... */
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#define ST25FL1_FAST_READ 0x0b /* Fast Read: *
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* 0x0b | ADDR(MS) | ADDR(MID) | *
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* ADDR(LS) | dummy | data... */
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#define ST25FL1_FAST_READ_DUAL 0x3b /* Fast Read Dual Output: *
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* 0x3b | ADDR(MS) | ADDR(MID) | *
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* ADDR(LS) | dummy | data... */
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#define ST25FL1_FAST_READ_QUAD 0x6b /* Fast Read Dual Output: *
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* 0x6b | ADDR(MS) | ADDR(MID) | *
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* ADDR(LS) | dummy | data... */
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#define ST25FL1_FAST_READ_DUALIO 0xbb /* Fast Read Dual I/O: *
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* 0xbb | ADDR(MS) | ADDR(LS) | data... */
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#define ST25FL1_FAST_READ_QUADIO 0xeb /* Fast Read Quad I/O: *
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* 0xeb | ADDR | data... */
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#define ST25FL1_CONT_READ_RESET 0xff /* Continuous Read Mode Reset: *
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* 0xff | 0xff */
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/* Reset Commands *******************************************************************/
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/* Command Value Description: */
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/* Data sequence */
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#define ST25FL1_SOFT_RESET_ENABLE 0x66 /* Software Reset Enable: *
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* 0x66 */
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#define ST25FL1_SOFT_RESET 0x99 /* Software Reset: *
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* 0x99 */
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/* Continuous Read Mode Reset: *
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* 0xff | 0xff */
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/* ID/Security Commands *************************&***********************************/
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/* Command Value Description: */
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/* Data sequence */
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#define ST25FL1_DEEP_PWRDOWN 0xb9 /* Deep Power-down: *
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* 0xb9 */
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#define ST25FL1_RELEASE_PWRDOWN 0xab /* Release Power down / Device ID: *
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* 0xab | dummy | dummy | dummy | *
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* DeviceID */
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#define ST25FL1_MANUFACTURER 0x90 /* Manufacturer / Device ID: *
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* 0x90 | dummy | dummy | 0x00 | *
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* Manufacturer | DeviceID */
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#define ST25FL1_JEDEC_ID 0x9f /* JEDEC ID: *
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* 0x9f | Manufacturer | MemoryType | *
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* Capacity */
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#define ST25FL1_READ_SFDP 0x5a /* Read SFDP Register / Read Unique ID *
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* Number: *
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* 0x5a | 0x00 | 0x00 | ADDR | dummy | *
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* data... */
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#define ST25FL1_READ_SECURITY 0x48 /* Read Security Registers: *
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* 0x48 | ADDR(MS) | ADDR(MID) | *
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* ADDR(LS) | dummy | data... */
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#define ST25FL1_ERASE_SECURITY 0x44 /* Erase Security Registers: *
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* 0x48 | ADDR(MS) | ADDR(MID) | *
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* ADDR(LS) */
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#define ST25FL1_PROgRAM_SECURITY 0x42 /* Program Security Registers: *
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* 0x42 | ADDR(MS) | ADDR(MID) | *
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* ADDR(LS) | data... */
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/* Flash Manufacturer JEDEC IDs */
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2015-08-26 22:16:45 +02:00
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#define ST25FL1_JEDEC_ID_SPANSION 0x01
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#define ST25FL1_JEDEC_ID_ATMEL 0x1f
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#define ST25FL1_JEDEC_ID_ST 0x20
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#define ST25FL1_JEDEC_ID_SST 0xbf
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#define ST25FL1_JEDEC_ID_MACRONIX 0xc2
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#define ST25FL1_JEDEC_ID_WINBOND 0xef
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2015-08-26 22:16:45 +02:00
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/* ST25FL1 JEDIC IDs */
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#define ST25FL1_JEDEC_DEVICE_TYPE 0x40 /* ST25FL1 memory devuce type */
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#define S25FL116K_JEDEC_CAPACITY 0x15 /* S25FL116K memory capacity */
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#define S25FL132K_JEDEC_CAPACITY 0x16 /* S25FL132K memory capacity */
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#define S25FL164K_JEDEC_CAPACITY 0x17 /* S25FL164K memory capacity */
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2015-08-25 17:10:12 +02:00
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/* ST25FL1 Registers ****************************************************************/
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/* Status register bit definitions */
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#define STATUS1_BUSY_MASK (1 << 0) /* Bit 0: Device ready/busy status */
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# define STATUS1_READY (0 << 0) /* 0 = Not Busy */
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# define STATUS1_BUSY (1 << 0) /* 1 = Busy */
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#define STATUS1_WEL_MASK (1 << 1) /* Bit 1: Write enable latch status */
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# define STATUS1_WEL_DISABLED (0 << 1) /* 0 = Not Write Enabled */
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# define STATUS1_WEL_ENABLED (1 << 1) /* 1 = Write Enabled */
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#define STATUS1_BP_SHIFT (2) /* Bits 2-4: Block protect bits */
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#define STATUS1_BP_MASK (7 << STATUS1_BP_SHIFT)
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# define STATUS1_BP_NONE (0 << STATUS1_BP_SHIFT)
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# define STATUS1_BP_ALL (7 << STATUS1_BP_SHIFT)
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#define STATUS1_TB_MASK (1 << 5) /* Bit 5: Top / Bottom Protect */
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# define STATUS1_TB_TOP (0 << 5) /* 0 = BP2-BP0 protect Top down */
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# define STATUS1_TB_BOTTOM (1 << 5) /* 1 = BP2-BP0 protect Bottom up */
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#define STATUS1_SEC_MASK (1 << 6) /* Bit 6: Sector / Block Protect */
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# define STATUS1_SEC_BLOCK (0 << 6) /* 0 = BP2-BP0 protect 64-kB blocks */
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# define STATUS1_SEC_SECTOR (1 << 6) /* 1 = BP2-BP0 protect 4-kB sectors */
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#define STATUS1_SRP0_MASK (1 << 7) /* Bit 7: Status register protect 0 */
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# define STATUS1_SRP0_UNLOCKED (0 << 7) /* 0 = WP# no effect / PS Lock Down */
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# define STATUS1_SRP0_LOCKED (1 << 7) /* 1 = WP# protect / OTP Lock Down */
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#define STATUS2_SRP1_MASK (1 << 0) /* Bit 0: Status register protect 1 */
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# define STATUS2_SRP1_UNLOCKED (0 << 0) /* 0 = WP# no effect / PS Lock Down */
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# define STATUS2_SRP1_LOCKED (1 << 0) /* 1 = WP# protect / OTP Lock Down */
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#define STATUS2_QUAD_ENABLE_MASK (1 << 1) /* Bit 1: Quad Enable */
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# define STATUS2_QUAD_DISABLE (0 << 1) /* 0 = Quad Mode Not Enabled */
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# define STATUS2_QUAD_ENABLE (1 << 1) /* 1 = Quad Mode Enabled */
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#define STATUS2_LB_SHIFT (2) /* Bits 2-5: Security Register Lock */
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#define STATUS2_LB_MASK (15 << STATUS2_LB_SHIFT)
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# define STATUS2_LB_NONE (0 << STATUS2_LB_SHIFT)
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# define STATUS2_LB_ALL (15 << STATUS2_LB_SHIFT)
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#define STATUS2_CMP_MASK (1 << 6) /* Bit 6: Complement Protect */
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# define STATUS2_CMP_NORMAL (0 << 6) /* 0 = Normal Protection Map */
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# define STATUS2_CMP_INVERTED (1 << 6) /* 1 = Inverted Protection Map */
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#define STATUS2_SUS_MASK (1 << 7) /* Bit 7: Suspend Status */
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# define STATUS2_SUS_NONE (0 << 7) /* 0 = Erase / Program not suspended */
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# define STATUS2_SUS_SUSPENDED (1 << 7) /* 1 = Erase / Program suspended */
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#define STATUS3_LC_SHIFT (0) /* Bits 0-3: Latency control */
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#define STATUS3_LC_MASK (15 << STATUS3_LC_SHIFT)
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#define STATUS3_W4_MASK (1 << 4) /* Bit 4: Burst Wrap Enable */
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# define STATUS3_W4_DISABLED (0 << 4) /* 0 = Wrap Enabled */
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# define STATUS3_W4_ENABLED (1 << 4) /* 1 = Wrap Disabled */
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#define STATUS3_W56_SHIFT (5) /* Bits 5-6: Burst Wrap Length */
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#define STATUS3_W56_MASK (3 << STATUS3_W56_SHIFT)
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|
|
|
|
# define STATUS3_W56_8BYTE (0 << STATUS3_W56_SHIFT)
|
|
|
|
|
# define STATUS3_W56_16BYTE (1 << STATUS3_W56_SHIFT)
|
|
|
|
|
# define STATUS3_W56_32BYTE (2 << STATUS3_W56_SHIFT)
|
|
|
|
|
# define STATUS3_W56_63BYTE (3 << STATUS3_W56_SHIFT)
|
|
|
|
|
/* Bit 7: Reserved */
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* Chip Geometries ******************************************************************/
|
|
|
|
|
/* All members of the family support uniform 4K-byte sectors */
|
|
|
|
|
|
|
|
|
|
#define S25FL116K_SECTOR_SIZE (4*1024)
|
2015-08-26 22:16:45 +02:00
|
|
|
|
#define S25FL116K_SECTOR_SHIFT (12)
|
2015-08-25 17:10:12 +02:00
|
|
|
|
#define S25FL116K_SECTOR_COUNT (512)
|
2015-08-28 18:15:39 +02:00
|
|
|
|
#define S25FL116K_PAGE_SIZE (256)
|
|
|
|
|
#define S25FL116K_PAGE_SHIFT (8)
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
|
|
|
|
#define S25FL132K_SECTOR_SIZE (4*1024)
|
2015-08-28 18:15:39 +02:00
|
|
|
|
#define S25FL132K_SECTOR_SHIFT (12)
|
2015-08-25 17:10:12 +02:00
|
|
|
|
#define S25FL132K_SECTOR_COUNT (1024)
|
2015-08-28 18:15:39 +02:00
|
|
|
|
#define S25FL132K_PAGE_SIZE (256)
|
|
|
|
|
#define S25FL132K_PAGE_SHIFT (8)
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
|
|
|
|
#define S25FL164K_SECTOR_SIZE (4*1024)
|
2015-08-26 22:16:45 +02:00
|
|
|
|
#define S25FL164K_SECTOR_SHIFT (12)
|
2015-08-25 17:10:12 +02:00
|
|
|
|
#define S25FL164K_SECTOR_COUNT (2048)
|
2015-08-28 18:15:39 +02:00
|
|
|
|
#define S25FL164K_PAGE_SIZE (256)
|
|
|
|
|
#define S25FL164K_PAGE_SHIFT (8)
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
|
|
|
|
/* Cache flags **********************************************************************/
|
|
|
|
|
|
|
|
|
|
#define ST25FL1_CACHE_VALID (1 << 0) /* 1=Cache has valid data */
|
|
|
|
|
#define ST25FL1_CACHE_DIRTY (1 << 1) /* 1=Cache is dirty */
|
|
|
|
|
#define ST25FL1_CACHE_ERASED (1 << 2) /* 1=Backing FLASH is erased */
|
|
|
|
|
|
|
|
|
|
#define IS_VALID(p) ((((p)->flags) & ST25FL1_CACHE_VALID) != 0)
|
|
|
|
|
#define IS_DIRTY(p) ((((p)->flags) & ST25FL1_CACHE_DIRTY) != 0)
|
|
|
|
|
#define IS_ERASED(p) ((((p)->flags) & ST25FL1_CACHE_DIRTY) != 0)
|
|
|
|
|
|
|
|
|
|
#define SET_VALID(p) do { (p)->flags |= ST25FL1_CACHE_VALID; } while (0)
|
|
|
|
|
#define SET_DIRTY(p) do { (p)->flags |= ST25FL1_CACHE_DIRTY; } while (0)
|
|
|
|
|
#define SET_ERASED(p) do { (p)->flags |= ST25FL1_CACHE_DIRTY; } while (0)
|
|
|
|
|
|
|
|
|
|
#define CLR_VALID(p) do { (p)->flags &= ~ST25FL1_CACHE_VALID; } while (0)
|
|
|
|
|
#define CLR_DIRTY(p) do { (p)->flags &= ~ST25FL1_CACHE_DIRTY; } while (0)
|
|
|
|
|
#define CLR_ERASED(p) do { (p)->flags &= ~ST25FL1_CACHE_DIRTY; } while (0)
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
|
* Private Types
|
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
|
|
/* This type represents the state of the MTD device. The struct mtd_dev_s must
|
|
|
|
|
* appear at the beginning of the definition so that you can freely cast between
|
|
|
|
|
* pointers to struct mtd_dev_s and struct st25fl1_dev_s.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
struct st25fl1_dev_s
|
|
|
|
|
{
|
|
|
|
|
struct mtd_dev_s mtd; /* MTD interface */
|
2015-08-26 22:16:45 +02:00
|
|
|
|
FAR struct qspi_dev_s *qspi; /* Saved QuadSPI interface instance */
|
2015-08-25 17:10:12 +02:00
|
|
|
|
uint16_t nsectors; /* Number of erase sectors */
|
2015-08-26 22:16:45 +02:00
|
|
|
|
uint8_t sectorshift; /* Log2 of sector size */
|
2015-08-28 18:15:39 +02:00
|
|
|
|
uint8_t pageshift; /* Log2 of page size */
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_ST25FL1_SECTOR512
|
|
|
|
|
uint8_t flags; /* Buffered sector flags */
|
|
|
|
|
uint16_t esectno; /* Erase sector number in the cache*/
|
|
|
|
|
FAR uint8_t *sector; /* Allocated sector data */
|
|
|
|
|
#endif
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
|
* Private Function Prototypes
|
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
2015-08-26 22:16:45 +02:00
|
|
|
|
/* Locking */
|
|
|
|
|
|
|
|
|
|
static void st25fl1_lock(FAR struct qspi_dev_s *qspi);
|
|
|
|
|
static inline void st25fl1_unlock(FAR struct qspi_dev_s *qspi);
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
2015-08-26 22:16:45 +02:00
|
|
|
|
/* Low-level message helpers */
|
|
|
|
|
|
|
|
|
|
static int st25fl1_command(FAR struct qspi_dev_s *qspi, uint8_t cmd);
|
|
|
|
|
static int st25fl1_command_address(FAR struct qspi_dev_s *qspi, uint8_t cmd,
|
2015-08-27 22:16:51 +02:00
|
|
|
|
off_t addr, uint8_t addrlen);
|
2015-08-26 22:16:45 +02:00
|
|
|
|
static int st25fl1_command_read(FAR struct qspi_dev_s *qspi, uint8_t cmd,
|
|
|
|
|
FAR void *buffer, size_t buflen);
|
|
|
|
|
static int st25fl1_command_write(FAR struct qspi_dev_s *qspi, uint8_t cmd,
|
|
|
|
|
FAR const void *buffer, size_t buflen);
|
|
|
|
|
static uint8_t sf25fl1_read_status1(FAR struct qspi_dev_s *qspi);
|
|
|
|
|
static uint8_t sf25fl1_read_status2(FAR struct qspi_dev_s *qspi);
|
|
|
|
|
static uint8_t sf25fl1_read_status3(FAR struct qspi_dev_s *qspi);
|
|
|
|
|
static void st25fl1_write_enable(FAR struct qspi_dev_s *qspi);
|
|
|
|
|
static void st25fl1_write_disable(FAR struct qspi_dev_s *qspi);
|
|
|
|
|
|
|
|
|
|
static int st25fl1_readid(FAR struct st25fl1_dev_s *priv);
|
2015-08-29 23:58:54 +02:00
|
|
|
|
static int st25fl1_protect(FAR struct st25fl1_dev_s *priv,
|
|
|
|
|
off_t startblock, size_t nblocks);
|
|
|
|
|
static int st25fl1_unprotect(FAR struct st25fl1_dev_s *priv,
|
|
|
|
|
off_t startblock, size_t nblocks);
|
|
|
|
|
static bool st25fl1_isprotected(FAR struct st25fl1_dev_s *priv,
|
|
|
|
|
uint8_t status, off_t address);
|
2015-08-26 22:16:45 +02:00
|
|
|
|
static int st25fl1_erase_sector(FAR struct st25fl1_dev_s *priv, off_t offset);
|
|
|
|
|
static int st25fl1_erase_chip(FAR struct st25fl1_dev_s *priv);
|
2015-08-28 20:01:08 +02:00
|
|
|
|
static int st25fl1_read_byte(FAR struct st25fl1_dev_s *priv, FAR uint8_t *buffer,
|
2015-08-26 22:16:45 +02:00
|
|
|
|
off_t address, size_t nbytes);
|
2015-08-28 20:01:08 +02:00
|
|
|
|
static int st25fl1_write_page(FAR struct st25fl1_dev_s *priv,
|
2015-08-26 22:16:45 +02:00
|
|
|
|
FAR const uint8_t *buffer, off_t address, size_t nbytes);
|
2015-08-25 17:10:12 +02:00
|
|
|
|
#ifdef CONFIG_ST25FL1_SECTOR512
|
2015-08-28 20:01:08 +02:00
|
|
|
|
static int st25fl1_flush_cache(struct st25fl1_dev_s *priv);
|
2015-08-26 22:16:45 +02:00
|
|
|
|
static FAR uint8_t *st25fl1_read_cache(struct st25fl1_dev_s *priv, off_t sector);
|
|
|
|
|
static void st25fl1_erase_cache(struct st25fl1_dev_s *priv, off_t sector);
|
2015-08-28 20:01:08 +02:00
|
|
|
|
static int st25fl1_write_cache(FAR struct st25fl1_dev_s *priv,
|
2015-08-26 22:16:45 +02:00
|
|
|
|
FAR const uint8_t *buffer, off_t sector, size_t nsectors);
|
2015-08-25 17:10:12 +02:00
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* MTD driver methods */
|
|
|
|
|
|
2015-08-26 22:16:45 +02:00
|
|
|
|
static int st25fl1_erase(FAR struct mtd_dev_s *dev, off_t startblock,
|
|
|
|
|
size_t nblocks);
|
2015-08-25 17:10:12 +02:00
|
|
|
|
static ssize_t st25fl1_bread(FAR struct mtd_dev_s *dev, off_t startblock,
|
2015-08-26 22:16:45 +02:00
|
|
|
|
size_t nblocks, FAR uint8_t *buf);
|
2015-08-25 17:10:12 +02:00
|
|
|
|
static ssize_t st25fl1_bwrite(FAR struct mtd_dev_s *dev, off_t startblock,
|
2015-08-26 22:16:45 +02:00
|
|
|
|
size_t nblocks, FAR const uint8_t *buf);
|
2015-08-25 17:10:12 +02:00
|
|
|
|
static ssize_t st25fl1_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes,
|
2015-08-26 22:16:45 +02:00
|
|
|
|
FAR uint8_t *buffer);
|
|
|
|
|
static int st25fl1_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg);
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
|
* Private Data
|
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
|
* Private Functions
|
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
|
* Name: st25fl1_lock
|
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
2015-08-26 22:16:45 +02:00
|
|
|
|
static void st25fl1_lock(FAR struct qspi_dev_s *qspi)
|
2015-08-25 17:10:12 +02:00
|
|
|
|
{
|
|
|
|
|
/* On QuadSPI busses where there are multiple devices, it will be necessary to
|
|
|
|
|
* lock QuadSPI to have exclusive access to the busses for a sequence of
|
|
|
|
|
* transfers. The bus should be locked before the chip is selected.
|
|
|
|
|
*
|
|
|
|
|
* This is a blocking call and will not return until we have exclusiv access to
|
|
|
|
|
* the QuadSPI buss. We will retain that exclusive access until the bus is unlocked.
|
|
|
|
|
*/
|
|
|
|
|
|
2015-08-26 01:20:54 +02:00
|
|
|
|
(void)QSPI_LOCK(qspi, true);
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
|
|
|
|
/* After locking the QuadSPI bus, the we also need call the setfrequency, setbits, and
|
|
|
|
|
* setmode methods to make sure that the QuadSPI is properly configured for the device.
|
|
|
|
|
* If the QuadSPI buss is being shared, then it may have been left in an incompatible
|
|
|
|
|
* state.
|
|
|
|
|
*/
|
|
|
|
|
|
2015-08-26 01:20:54 +02:00
|
|
|
|
QSPI_SETMODE(qspi, CONFIG_ST25FL1_QSPIMODE);
|
|
|
|
|
QSPI_SETBITS(qspi, 8);
|
2015-08-30 02:54:20 +02:00
|
|
|
|
(void)QSPI_SETFREQUENCY(qspi, CONFIG_ST25FL1_QSPI_FREQUENCY);
|
2015-08-25 17:10:12 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
|
* Name: st25fl1_unlock
|
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
2015-08-26 22:16:45 +02:00
|
|
|
|
static inline void st25fl1_unlock(FAR struct qspi_dev_s *qspi)
|
2015-08-25 17:10:12 +02:00
|
|
|
|
{
|
2015-08-26 01:20:54 +02:00
|
|
|
|
(void)QSPI_LOCK(qspi, false);
|
2015-08-25 17:10:12 +02:00
|
|
|
|
}
|
|
|
|
|
|
2015-08-26 22:16:45 +02:00
|
|
|
|
/************************************************************************************
|
|
|
|
|
* Name: st25fl1_command
|
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
|
|
static int st25fl1_command(FAR struct qspi_dev_s *qspi, uint8_t cmd)
|
|
|
|
|
{
|
2015-08-28 18:15:39 +02:00
|
|
|
|
struct qspi_cmdinfo_s cmdinfo;
|
2015-08-26 22:16:45 +02:00
|
|
|
|
|
|
|
|
|
fvdbg("CMD: %02x\n", cmd);
|
2015-08-27 22:16:51 +02:00
|
|
|
|
|
2015-08-28 18:15:39 +02:00
|
|
|
|
cmdinfo.flags = 0;
|
|
|
|
|
cmdinfo.addrlen = 0;
|
|
|
|
|
cmdinfo.cmd = cmd;
|
|
|
|
|
cmdinfo.buflen = 0;
|
|
|
|
|
cmdinfo.addr = 0;
|
|
|
|
|
cmdinfo.buffer = NULL;
|
2015-08-27 22:16:51 +02:00
|
|
|
|
|
2015-08-28 18:15:39 +02:00
|
|
|
|
return QSPI_COMMAND(qspi, &cmdinfo);
|
2015-08-27 22:16:51 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
|
* Name: st25fl1_command_address
|
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
|
|
static int st25fl1_command_address(FAR struct qspi_dev_s *qspi, uint8_t cmd,
|
|
|
|
|
off_t addr, uint8_t addrlen)
|
|
|
|
|
{
|
2015-08-28 18:15:39 +02:00
|
|
|
|
struct qspi_cmdinfo_s cmdinfo;
|
2015-08-27 22:16:51 +02:00
|
|
|
|
|
|
|
|
|
fvdbg("CMD: %02x Address: %04lx addrlen=%d\n", cmd, (unsigned long)addr, addrlen);
|
|
|
|
|
|
2015-08-28 18:15:39 +02:00
|
|
|
|
cmdinfo.flags = QSPICMD_ADDRESS;
|
|
|
|
|
cmdinfo.addrlen = addrlen;
|
|
|
|
|
cmdinfo.cmd = cmd;
|
|
|
|
|
cmdinfo.buflen = 0;
|
|
|
|
|
cmdinfo.addr = addr;
|
|
|
|
|
cmdinfo.buffer = NULL;
|
2015-08-27 22:16:51 +02:00
|
|
|
|
|
2015-08-28 18:15:39 +02:00
|
|
|
|
return QSPI_COMMAND(qspi, &cmdinfo);
|
2015-08-26 22:16:45 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
|
* Name: st25fl1_command_read
|
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
|
|
static int st25fl1_command_read(FAR struct qspi_dev_s *qspi, uint8_t cmd,
|
|
|
|
|
FAR void *buffer, size_t buflen)
|
|
|
|
|
{
|
2015-08-28 18:15:39 +02:00
|
|
|
|
struct qspi_cmdinfo_s cmdinfo;
|
2015-08-26 22:16:45 +02:00
|
|
|
|
|
|
|
|
|
fvdbg("CMD: %02x buflen: %lu\n", cmd, (unsigned long)buflen);
|
2015-08-27 22:16:51 +02:00
|
|
|
|
|
2015-08-28 18:15:39 +02:00
|
|
|
|
cmdinfo.flags = QSPICMD_READDATA;
|
|
|
|
|
cmdinfo.addrlen = 0;
|
|
|
|
|
cmdinfo.cmd = cmd;
|
|
|
|
|
cmdinfo.buflen = buflen;
|
|
|
|
|
cmdinfo.addr = 0;
|
|
|
|
|
cmdinfo.buffer = buffer;
|
2015-08-27 22:16:51 +02:00
|
|
|
|
|
2015-08-28 18:15:39 +02:00
|
|
|
|
return QSPI_COMMAND(qspi, &cmdinfo);
|
2015-08-26 22:16:45 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
|
* Name: st25fl1_command_write
|
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
|
|
static int st25fl1_command_write(FAR struct qspi_dev_s *qspi, uint8_t cmd,
|
|
|
|
|
FAR const void *buffer, size_t buflen)
|
|
|
|
|
{
|
2015-08-28 18:15:39 +02:00
|
|
|
|
struct qspi_cmdinfo_s cmdinfo;
|
2015-08-26 22:16:45 +02:00
|
|
|
|
|
|
|
|
|
fvdbg("CMD: %02x buflen: %lu\n", cmd, (unsigned long)buflen);
|
2015-08-27 22:16:51 +02:00
|
|
|
|
|
2015-08-28 18:15:39 +02:00
|
|
|
|
cmdinfo.flags = QSPICMD_WRITEDATA;
|
|
|
|
|
cmdinfo.addrlen = 0;
|
|
|
|
|
cmdinfo.cmd = cmd;
|
|
|
|
|
cmdinfo.buflen = buflen;
|
|
|
|
|
cmdinfo.addr = 0;
|
|
|
|
|
cmdinfo.buffer = (FAR void *)buffer;
|
2015-08-27 22:16:51 +02:00
|
|
|
|
|
2015-08-28 18:15:39 +02:00
|
|
|
|
return QSPI_COMMAND(qspi, &cmdinfo);
|
2015-08-26 22:16:45 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
|
* Name: sf25fl1_read_status1
|
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
|
|
static uint8_t sf25fl1_read_status1(FAR struct qspi_dev_s *qspi)
|
|
|
|
|
{
|
|
|
|
|
uint8_t status;
|
|
|
|
|
|
|
|
|
|
DEBUGVERIFY(st25fl1_command_read(qspi, ST25FL1_READ_STATUS1,
|
|
|
|
|
(FAR void *)&status, 1));
|
|
|
|
|
return status;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
|
* Name: sf25fl1_read_status2
|
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
|
|
static uint8_t sf25fl1_read_status2(FAR struct qspi_dev_s *qspi)
|
|
|
|
|
{
|
|
|
|
|
uint8_t status;
|
|
|
|
|
|
|
|
|
|
DEBUGVERIFY(st25fl1_command_read(qspi, ST25FL1_READ_STATUS2,
|
|
|
|
|
(FAR void *)&status, 1));
|
|
|
|
|
return status;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
|
* Name: sf25fl1_read_status3
|
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
|
|
static uint8_t sf25fl1_read_status3(FAR struct qspi_dev_s *qspi)
|
|
|
|
|
{
|
|
|
|
|
uint8_t status;
|
|
|
|
|
|
|
|
|
|
DEBUGVERIFY(st25fl1_command_read(qspi, ST25FL1_READ_STATUS3,
|
|
|
|
|
(FAR void *)&status, 1));
|
|
|
|
|
return status;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
|
* Name: st25fl1_write_enable
|
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
|
|
static void st25fl1_write_enable(FAR struct qspi_dev_s *qspi)
|
|
|
|
|
{
|
|
|
|
|
uint8_t status;
|
|
|
|
|
|
|
|
|
|
do
|
|
|
|
|
{
|
|
|
|
|
st25fl1_command(qspi, ST25FL1_WRITE_ENABLE);
|
|
|
|
|
status = sf25fl1_read_status1(qspi);
|
|
|
|
|
}
|
|
|
|
|
while ((status & STATUS1_WEL_MASK) != STATUS1_WEL_ENABLED);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
|
* Name: st25fl1_write_disable
|
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
|
|
static void st25fl1_write_disable(FAR struct qspi_dev_s *qspi)
|
|
|
|
|
{
|
|
|
|
|
uint8_t status;
|
|
|
|
|
|
|
|
|
|
do
|
|
|
|
|
{
|
|
|
|
|
st25fl1_command(qspi, ST25FL1_WRITE_DISABLE);
|
|
|
|
|
status = sf25fl1_read_status1(qspi);
|
|
|
|
|
}
|
|
|
|
|
while ((status & STATUS1_WEL_MASK) != STATUS1_WEL_DISABLED);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
|
* Name: st25fl1_write_status
|
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
|
|
static void st25fl1_write_status(FAR struct qspi_dev_s *qspi, uint8_t status[3])
|
|
|
|
|
{
|
|
|
|
|
st25fl1_write_enable(qspi);
|
|
|
|
|
st25fl1_command_write(qspi, ST25FL1_WRITE_STATUS, (FAR const void *)status, 3);
|
|
|
|
|
st25fl1_write_disable(qspi);
|
|
|
|
|
}
|
|
|
|
|
|
2015-08-25 17:10:12 +02:00
|
|
|
|
/************************************************************************************
|
|
|
|
|
* Name: st25fl1_readid
|
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
|
|
static inline int st25fl1_readid(struct st25fl1_dev_s *priv)
|
|
|
|
|
{
|
2015-08-26 22:16:45 +02:00
|
|
|
|
uint8_t jedecid[3];
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
2015-08-26 01:20:54 +02:00
|
|
|
|
/* Lock the QuadSPI bus and configure the bus. */
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
2015-08-26 01:20:54 +02:00
|
|
|
|
st25fl1_lock(priv->qspi);
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
2015-08-26 22:16:45 +02:00
|
|
|
|
/* Read the JEDEC ID */
|
|
|
|
|
|
|
|
|
|
st25fl1_command_read(priv->qspi, ST25FL1_JEDEC_ID, jedecid, 3);
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
2015-08-26 01:20:54 +02:00
|
|
|
|
/* Unlock the bus */
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
2015-08-26 01:20:54 +02:00
|
|
|
|
st25fl1_unlock(priv->qspi);
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
2015-08-26 22:16:45 +02:00
|
|
|
|
fvdbg("Manufacturer: %02x Device Type %02x, Capacity: %02x",
|
|
|
|
|
jedecid[0], jedecid[1], jedecid[2]);
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
2015-08-26 22:16:45 +02:00
|
|
|
|
/* Check for a recognized memory device type */
|
|
|
|
|
|
|
|
|
|
if (jedecid[1] != ST25FL1_JEDEC_DEVICE_TYPE)
|
|
|
|
|
{
|
|
|
|
|
fdbg("ERROR: Unrecognized device type: %02x\n", jedecid[1]);
|
|
|
|
|
return -ENODEV;
|
|
|
|
|
}
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
2015-08-26 22:16:45 +02:00
|
|
|
|
/* Check for a supported capacity */
|
|
|
|
|
|
|
|
|
|
switch (jedecid[2])
|
|
|
|
|
{
|
|
|
|
|
case S25FL116K_JEDEC_CAPACITY:
|
|
|
|
|
priv->sectorshift = S25FL116K_SECTOR_SHIFT;
|
2015-08-28 18:15:39 +02:00
|
|
|
|
priv->pageshift = S25FL116K_PAGE_SHIFT;
|
2015-08-26 22:16:45 +02:00
|
|
|
|
priv->nsectors = S25FL116K_SECTOR_COUNT;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case S25FL132K_JEDEC_CAPACITY:
|
2015-08-28 18:15:39 +02:00
|
|
|
|
priv->sectorshift = S25FL132K_SECTOR_SHIFT;
|
|
|
|
|
priv->pageshift = S25FL116K_PAGE_SHIFT;
|
2015-08-26 22:16:45 +02:00
|
|
|
|
priv->nsectors = S25FL132K_SECTOR_COUNT;
|
|
|
|
|
break;
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
2015-08-26 22:16:45 +02:00
|
|
|
|
case S25FL164K_JEDEC_CAPACITY:
|
|
|
|
|
priv->sectorshift = S25FL164K_SECTOR_SHIFT;
|
2015-08-28 18:15:39 +02:00
|
|
|
|
priv->pageshift = S25FL116K_PAGE_SHIFT;
|
2015-08-26 22:16:45 +02:00
|
|
|
|
priv->nsectors = S25FL164K_SECTOR_COUNT;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
/* Support for this part is not implemented yet */
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
fdbg("ERROR: Unsupported memory capacity: %02x\n", jedecid[2]);
|
|
|
|
|
return -ENODEV;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return OK;
|
2015-08-25 17:10:12 +02:00
|
|
|
|
}
|
|
|
|
|
|
2015-08-29 23:58:54 +02:00
|
|
|
|
/************************************************************************************
|
|
|
|
|
* Name: st25fl1_protect
|
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
|
|
static int st25fl1_protect(FAR struct st25fl1_dev_s *priv,
|
|
|
|
|
off_t startblock, size_t nblocks)
|
|
|
|
|
{
|
|
|
|
|
unsigned char status[3];
|
|
|
|
|
|
|
|
|
|
/* Get the status register value to check the current protection */
|
|
|
|
|
|
|
|
|
|
status[0] = sf25fl1_read_status1(priv->qspi);
|
|
|
|
|
status[1] = sf25fl1_read_status2(priv->qspi);
|
|
|
|
|
status[2] = sf25fl1_read_status3(priv->qspi);
|
|
|
|
|
|
|
|
|
|
if ((status[0] & STATUS1_BP_MASK) == STATUS1_BP_NONE)
|
|
|
|
|
{
|
|
|
|
|
/* Protection already disabled */
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Check if sector protection registers are locked */
|
|
|
|
|
|
|
|
|
|
if ((status[0] & STATUS1_SRP0_MASK) == STATUS1_SRP0_LOCKED)
|
|
|
|
|
{
|
|
|
|
|
/* Yes.. unprotect section protection registers */
|
|
|
|
|
|
|
|
|
|
status[0] &= ~STATUS1_SRP0_MASK;
|
|
|
|
|
st25fl1_write_status(priv->qspi, status);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Set the protection mask to zero.
|
|
|
|
|
* REVISIT: This logic should really just set the BP bits as
|
|
|
|
|
* necessary to protect the range of sectors.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
status[0] |= STATUS1_BP_MASK;
|
|
|
|
|
st25fl1_write_status(priv->qspi, status);
|
|
|
|
|
|
|
|
|
|
/* Check the new status */
|
|
|
|
|
|
|
|
|
|
status[0] = sf25fl1_read_status1(priv->qspi);
|
|
|
|
|
if ((status[0] & STATUS1_BP_MASK) != STATUS1_BP_MASK)
|
|
|
|
|
{
|
|
|
|
|
return -EACCES;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return OK;
|
|
|
|
|
}
|
|
|
|
|
|
2015-08-25 17:10:12 +02:00
|
|
|
|
/************************************************************************************
|
|
|
|
|
* Name: st25fl1_unprotect
|
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
2015-08-29 23:58:54 +02:00
|
|
|
|
static int st25fl1_unprotect(FAR struct st25fl1_dev_s *priv,
|
|
|
|
|
off_t startblock, size_t nblocks)
|
|
|
|
|
{
|
|
|
|
|
unsigned char status[3];
|
|
|
|
|
|
|
|
|
|
/* Get the status register value to check the current protection */
|
|
|
|
|
|
|
|
|
|
status[0] = sf25fl1_read_status1(priv->qspi);
|
|
|
|
|
status[1] = sf25fl1_read_status2(priv->qspi);
|
|
|
|
|
status[2] = sf25fl1_read_status3(priv->qspi);
|
|
|
|
|
|
|
|
|
|
if ((status[0] & STATUS1_BP_MASK) == STATUS1_BP_NONE)
|
|
|
|
|
{
|
|
|
|
|
/* Protection already disabled */
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Check if sector protection registers are locked */
|
|
|
|
|
|
|
|
|
|
if ((status[0] & STATUS1_SRP0_MASK) == STATUS1_SRP0_LOCKED)
|
|
|
|
|
{
|
|
|
|
|
/* Yes.. unprotect section protection registers */
|
|
|
|
|
|
|
|
|
|
status[0] &= ~STATUS1_SRP0_MASK;
|
|
|
|
|
st25fl1_write_status(priv->qspi, status);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Set the protection mask to zero.
|
|
|
|
|
* REVISIT: This logic should really just re-write the BP bits as
|
|
|
|
|
* necessary to unprotect the range of sectors.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
status[0] &= ~STATUS1_BP_MASK;
|
|
|
|
|
st25fl1_write_status(priv->qspi, status);
|
|
|
|
|
|
|
|
|
|
/* Check the new status */
|
|
|
|
|
|
|
|
|
|
status[0] = sf25fl1_read_status1(priv->qspi);
|
|
|
|
|
if ((status[0] & (STATUS1_SRP0_MASK | STATUS1_BP_MASK)) != 0)
|
|
|
|
|
{
|
|
|
|
|
return -EACCES;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return OK;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
|
* Name: st25fl1_isprotected
|
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
|
|
static bool st25fl1_isprotected(FAR struct st25fl1_dev_s *priv, uint8_t status,
|
|
|
|
|
off_t address)
|
2015-08-25 17:10:12 +02:00
|
|
|
|
{
|
2015-08-29 23:58:54 +02:00
|
|
|
|
off_t protstart;
|
|
|
|
|
off_t protend;
|
|
|
|
|
off_t protsize;
|
|
|
|
|
unsigned int bp;
|
|
|
|
|
|
|
|
|
|
/* What is protected? 64 Kb blocks? Or 4Kb sectors? */
|
|
|
|
|
|
|
|
|
|
if ((status & STATUS1_SEC_MASK) == STATUS1_SEC_BLOCK)
|
|
|
|
|
{
|
|
|
|
|
/* 64 Kb block */
|
|
|
|
|
|
|
|
|
|
protsize = 0x00010000;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* 4 Kb sector */
|
|
|
|
|
|
|
|
|
|
protsize = 0x00001000;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* The BP field is the essentially a multiplier on this protection size */
|
|
|
|
|
|
|
|
|
|
bp = (status & STATUS1_BP_MASK) >> STATUS1_BP_SHIFT;
|
|
|
|
|
switch (bp)
|
|
|
|
|
{
|
|
|
|
|
case 0:
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
case 1:
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 6:
|
|
|
|
|
case 7:
|
|
|
|
|
return true;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
protsize <<= (protsize << (bp - 1));
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* The final protection range then depends on if the protection region is
|
|
|
|
|
* configured top-down or bottom up (assuming CMP=0).
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
if ((status & STATUS1_TB_MASK) != 0)
|
|
|
|
|
{
|
|
|
|
|
protstart = 0x00000000;
|
|
|
|
|
protend = protstart + protsize;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
protend = 0x00200000;
|
|
|
|
|
protstart = protend - protsize;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return (address >= protstart && address < protend);
|
2015-08-25 17:10:12 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
2015-08-26 22:16:45 +02:00
|
|
|
|
* Name: st25fl1_erase_sector
|
2015-08-25 17:10:12 +02:00
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
2015-08-26 22:16:45 +02:00
|
|
|
|
static int st25fl1_erase_sector(struct st25fl1_dev_s *priv, off_t sector)
|
2015-08-25 17:10:12 +02:00
|
|
|
|
{
|
2015-08-27 22:16:51 +02:00
|
|
|
|
off_t address;
|
2015-08-26 22:16:45 +02:00
|
|
|
|
uint8_t status;
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
2015-08-26 22:16:45 +02:00
|
|
|
|
fvdbg("sector: %08lx\n", (unsigned long)sector);
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
2015-08-26 22:16:45 +02:00
|
|
|
|
/* Check that the flash is ready and unprotected */
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
2015-08-26 22:16:45 +02:00
|
|
|
|
status = sf25fl1_read_status1(priv->qspi);
|
|
|
|
|
if ((status & STATUS1_BUSY_MASK) != STATUS1_READY)
|
|
|
|
|
{
|
|
|
|
|
fdbg("ERROR: Flash busy: %02x", status);
|
|
|
|
|
return -EBUSY;
|
|
|
|
|
}
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
2015-08-29 23:58:54 +02:00
|
|
|
|
/* Get the address associated with the sector */
|
|
|
|
|
|
|
|
|
|
address = (off_t)sector << priv->sectorshift;
|
|
|
|
|
|
|
|
|
|
if ((status & STATUS1_BP_MASK) != 0 &&
|
|
|
|
|
st25fl1_isprotected(priv, status, address))
|
2015-08-26 22:16:45 +02:00
|
|
|
|
{
|
|
|
|
|
fdbg("ERROR: Flash protected: %02x", status);
|
2015-08-29 23:58:54 +02:00
|
|
|
|
return -EACCES;
|
2015-08-26 22:16:45 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Send the sector erase command */
|
|
|
|
|
|
|
|
|
|
st25fl1_write_enable(priv->qspi);
|
2015-08-27 22:16:51 +02:00
|
|
|
|
st25fl1_command_address(priv->qspi, ST25FL1_SECTOR_ERASE, address, 3);
|
2015-08-26 22:16:45 +02:00
|
|
|
|
|
|
|
|
|
/* Wait for erasure to finish */
|
|
|
|
|
|
|
|
|
|
while ((sf25fl1_read_status1(priv->qspi) & STATUS1_BUSY_MASK) != 0);
|
|
|
|
|
return OK;
|
2015-08-25 17:10:12 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
2015-08-26 22:16:45 +02:00
|
|
|
|
* Name: st25fl1_erase_chip
|
2015-08-25 17:10:12 +02:00
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
2015-08-26 22:16:45 +02:00
|
|
|
|
static int st25fl1_erase_chip(struct st25fl1_dev_s *priv)
|
2015-08-25 17:10:12 +02:00
|
|
|
|
{
|
2015-08-26 22:16:45 +02:00
|
|
|
|
uint8_t status;
|
|
|
|
|
|
|
|
|
|
/* Check if the FLASH is protected */
|
|
|
|
|
|
|
|
|
|
status = sf25fl1_read_status1(priv->qspi);
|
|
|
|
|
if ((status & STATUS1_BP_MASK) != 0)
|
|
|
|
|
{
|
|
|
|
|
fdbg("ERROR: FLASH is Protected: %02x", status);
|
|
|
|
|
return -EACCES;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Erase the whole chip */
|
|
|
|
|
|
|
|
|
|
st25fl1_write_enable(priv->qspi);
|
|
|
|
|
st25fl1_command(priv->qspi, ST25FL1_CHIP_ERASE_2);
|
|
|
|
|
|
|
|
|
|
/* Wait for the erasure to complete */
|
|
|
|
|
|
|
|
|
|
status = sf25fl1_read_status1(priv->qspi);
|
|
|
|
|
while ((status & STATUS1_BUSY_MASK) != 0)
|
|
|
|
|
{
|
|
|
|
|
usleep(200*1000);
|
|
|
|
|
status = sf25fl1_read_status1(priv->qspi);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return OK;
|
2015-08-25 17:10:12 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
2015-08-26 22:16:45 +02:00
|
|
|
|
* Name: st25fl1_read_byte
|
2015-08-25 17:10:12 +02:00
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
2015-08-28 20:01:08 +02:00
|
|
|
|
static int st25fl1_read_byte(FAR struct st25fl1_dev_s *priv, FAR uint8_t *buffer,
|
|
|
|
|
off_t address, size_t buflen)
|
2015-08-25 17:10:12 +02:00
|
|
|
|
{
|
2015-08-28 20:01:08 +02:00
|
|
|
|
struct qspi_meminfo_s meminfo;
|
|
|
|
|
|
2015-08-31 17:25:14 +02:00
|
|
|
|
fvdbg("address: %08lx nbytes: %d\n", (long)address, (int)buflen);
|
2015-08-28 20:01:08 +02:00
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_ST25FL1_SCRAMBLE
|
|
|
|
|
meminfo.flags = QSPIMEM_READ | QSPIMEM_QUADIO | QSPIMEM_SCRAMBLE;
|
|
|
|
|
#else
|
|
|
|
|
meminfo.flags = QSPIMEM_READ | QSPIMEM_QUADIO;
|
|
|
|
|
#endif
|
|
|
|
|
meminfo.addrlen = 3;
|
|
|
|
|
meminfo.dummies = 6;
|
|
|
|
|
meminfo.buflen = buflen;
|
|
|
|
|
meminfo.cmd = ST25FL1_FAST_READ_QUADIO;
|
|
|
|
|
meminfo.addr = address;
|
|
|
|
|
#ifdef CONFIG_ST25FL1_SCRAMBLE
|
|
|
|
|
meminfo.key = CONFIG_ST25FL1_SCRAMBLE_KEY;
|
|
|
|
|
#endif
|
|
|
|
|
meminfo.buffer = buffer;
|
|
|
|
|
|
|
|
|
|
return QSPI_MEMORY(priv->qspi, &meminfo);
|
2015-08-25 17:10:12 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
2015-08-26 22:16:45 +02:00
|
|
|
|
* Name: st25fl1_write_page
|
2015-08-25 17:10:12 +02:00
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
2015-08-28 20:01:08 +02:00
|
|
|
|
static int st25fl1_write_page(struct st25fl1_dev_s *priv, FAR const uint8_t *buffer,
|
|
|
|
|
off_t address, size_t buflen)
|
2015-08-25 17:10:12 +02:00
|
|
|
|
{
|
2015-08-28 20:01:08 +02:00
|
|
|
|
struct qspi_meminfo_s meminfo;
|
|
|
|
|
unsigned int pagesize;
|
|
|
|
|
unsigned int npages;
|
|
|
|
|
int ret;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
fvdbg("address: %08lx buflen: %u\n", (unsigned long)address, (unsigned)buflen);
|
|
|
|
|
|
|
|
|
|
npages = (buflen >> priv->pageshift);
|
|
|
|
|
pagesize = (1 << priv->pageshift);
|
|
|
|
|
|
|
|
|
|
/* Set up non-varying parts of transfer description */
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_ST25FL1_SCRAMBLE
|
|
|
|
|
meminfo.flags = QSPIMEM_WRITE | QSPIMEM_SCRAMBLE;
|
|
|
|
|
#else
|
|
|
|
|
meminfo.flags = QSPIMEM_WRITE;
|
|
|
|
|
#endif
|
|
|
|
|
meminfo.cmd = ST25FL1_PAGE_PROGRAM;
|
|
|
|
|
meminfo.addrlen = 3;
|
|
|
|
|
meminfo.buflen = pagesize;
|
|
|
|
|
#ifdef CONFIG_ST25FL1_SCRAMBLE
|
|
|
|
|
meminfo.key = CONFIG_ST25FL1_SCRAMBLE_KEY;
|
|
|
|
|
#endif
|
|
|
|
|
meminfo.dummies = 0;
|
|
|
|
|
|
|
|
|
|
/* Then write each page */
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < npages; i++)
|
|
|
|
|
{
|
|
|
|
|
/* Set up varying parts of the transfer description */
|
|
|
|
|
|
|
|
|
|
meminfo.addr = address;
|
|
|
|
|
meminfo.buffer = (void *)buffer;
|
|
|
|
|
|
|
|
|
|
/* Write one page */
|
|
|
|
|
|
|
|
|
|
st25fl1_write_enable(priv->qspi);
|
|
|
|
|
ret = QSPI_MEMORY(priv->qspi, &meminfo);
|
|
|
|
|
if (ret < 0)
|
|
|
|
|
{
|
|
|
|
|
fdbg("ERROR: QSPI_MEMORY failed writing address=%06x\n",
|
2015-08-31 17:25:14 +02:00
|
|
|
|
address);
|
2015-08-28 20:01:08 +02:00
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Update for the next time through the loop */
|
|
|
|
|
|
|
|
|
|
buffer += pagesize;
|
|
|
|
|
address += pagesize;
|
|
|
|
|
buflen -= pagesize;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* The transfer should always be an even number of sectors and hence also
|
|
|
|
|
* pages. There should be no remainder.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
DEBUGASSERT(buflen == 0);
|
|
|
|
|
st25fl1_write_disable(priv->qspi);
|
|
|
|
|
return OK;
|
2015-08-25 17:10:12 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
2015-08-26 22:16:45 +02:00
|
|
|
|
* Name: st25fl1_flush_cache
|
2015-08-25 17:10:12 +02:00
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_ST25FL1_SECTOR512
|
2015-08-28 20:01:08 +02:00
|
|
|
|
static int st25fl1_flush_cache(struct st25fl1_dev_s *priv)
|
2015-08-25 17:10:12 +02:00
|
|
|
|
{
|
2015-08-29 23:58:54 +02:00
|
|
|
|
int ret = OK;
|
|
|
|
|
|
2015-08-25 17:10:12 +02:00
|
|
|
|
/* If the cached is dirty (meaning that it no longer matches the old FLASH contents)
|
|
|
|
|
* or was erased (with the cache containing the correct FLASH contents), then write
|
|
|
|
|
* the cached erase block to FLASH.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
if (IS_DIRTY(priv) || IS_ERASED(priv))
|
|
|
|
|
{
|
|
|
|
|
/* Write entire erase block to FLASH */
|
2015-08-29 23:58:54 +02:00
|
|
|
|
|
|
|
|
|
ret = st25fl1_write_page(priv, priv->sector, 1 << priv->sectorshift);
|
|
|
|
|
if (ret < 0)
|
|
|
|
|
{
|
|
|
|
|
fdbg("ERROR: st25fl1_write_page failed: %d\n", ret);
|
|
|
|
|
}
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
|
|
|
|
/* The case is no long dirty and the FLASH is no longer erased */
|
|
|
|
|
|
|
|
|
|
CLR_DIRTY(priv);
|
|
|
|
|
CLR_ERASED(priv);
|
|
|
|
|
}
|
2015-08-28 20:01:08 +02:00
|
|
|
|
|
2015-08-29 23:58:54 +02:00
|
|
|
|
return ret;
|
2015-08-25 17:10:12 +02:00
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
2015-08-26 22:16:45 +02:00
|
|
|
|
* Name: st25fl1_read_cache
|
2015-08-25 17:10:12 +02:00
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_ST25FL1_SECTOR512
|
2015-08-26 22:16:45 +02:00
|
|
|
|
static FAR uint8_t *st25fl1_read_cache(struct st25fl1_dev_s *priv, off_t sector)
|
2015-08-25 17:10:12 +02:00
|
|
|
|
{
|
|
|
|
|
off_t esectno;
|
|
|
|
|
int shift;
|
|
|
|
|
int index;
|
2015-08-28 20:01:08 +02:00
|
|
|
|
int ret;
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
|
|
|
|
/* Convert from the 512 byte sector to the erase sector size of the device. For
|
|
|
|
|
* exmample, if the actual erase sector size if 4Kb (1 << 12), then we first
|
|
|
|
|
* shift to the right by 3 to get the sector number in 4096 increments.
|
|
|
|
|
*/
|
|
|
|
|
|
2015-08-26 22:16:45 +02:00
|
|
|
|
shift = priv->sectorshift - ST25FL1_SECTOR512_SHIFT;
|
2015-08-25 17:10:12 +02:00
|
|
|
|
esectno = sector >> shift;
|
|
|
|
|
fvdbg("sector: %ld esectno: %d shift=%d\n", sector, esectno, shift);
|
|
|
|
|
|
|
|
|
|
/* Check if the requested erase block is already in the cache */
|
|
|
|
|
|
|
|
|
|
if (!IS_VALID(priv) || esectno != priv->esectno)
|
|
|
|
|
{
|
|
|
|
|
/* No.. Flush any dirty erase block currently in the cache */
|
|
|
|
|
|
2015-08-28 20:01:08 +02:00
|
|
|
|
ret = st25fl1_flush_cache(priv);
|
|
|
|
|
if (ret < 0)
|
|
|
|
|
{
|
|
|
|
|
fdbg("ERROR: st25fl1_flush_cache failed: %d\n", ret);
|
|
|
|
|
return NULL;
|
|
|
|
|
}
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
|
|
|
|
/* Read the erase block into the cache */
|
|
|
|
|
|
2015-08-28 20:01:08 +02:00
|
|
|
|
ret = st25fl1_read_byte(priv, priv->sector,
|
|
|
|
|
(esectno << priv->sectorshift)
|
|
|
|
|
(1 << priv->sectorshift));
|
|
|
|
|
if (ret < 0)
|
|
|
|
|
{
|
|
|
|
|
fdbg("ERROR: st25fl1_read_byte failed: %d\n", ret);
|
|
|
|
|
return NULL;
|
|
|
|
|
}
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
|
|
|
|
/* Mark the sector as cached */
|
|
|
|
|
|
|
|
|
|
priv->esectno = esectno;
|
|
|
|
|
|
|
|
|
|
SET_VALID(priv); /* The data in the cache is valid */
|
|
|
|
|
CLR_DIRTY(priv); /* It should match the FLASH contents */
|
|
|
|
|
CLR_ERASED(priv); /* The underlying FLASH has not been erased */
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Get the index to the 512 sector in the erase block that holds the argument */
|
|
|
|
|
|
|
|
|
|
index = sector & ((1 << shift) - 1);
|
|
|
|
|
|
|
|
|
|
/* Return the address in the cache that holds this sector */
|
|
|
|
|
|
|
|
|
|
return &priv->sector[index << ST25FL1_SECTOR512_SHIFT];
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
2015-08-26 22:16:45 +02:00
|
|
|
|
* Name: st25fl1_erase_cache
|
2015-08-25 17:10:12 +02:00
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_ST25FL1_SECTOR512
|
2015-08-26 22:16:45 +02:00
|
|
|
|
static void st25fl1_erase_cache(struct st25fl1_dev_s *priv, off_t sector)
|
2015-08-25 17:10:12 +02:00
|
|
|
|
{
|
|
|
|
|
FAR uint8_t *dest;
|
|
|
|
|
|
|
|
|
|
/* First, make sure that the erase block containing the 512 byte sector is in
|
|
|
|
|
* the cache.
|
|
|
|
|
*/
|
|
|
|
|
|
2015-08-26 22:16:45 +02:00
|
|
|
|
dest = st25fl1_read_cache(priv, sector);
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
|
|
|
|
/* Erase the block containing this sector if it is not already erased.
|
|
|
|
|
* The erased indicated will be cleared when the data from the erase sector
|
|
|
|
|
* is read into the cache and set here when we erase the block.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
if (!IS_ERASED(priv))
|
|
|
|
|
{
|
2015-08-26 22:16:45 +02:00
|
|
|
|
off_t esectno = sector >> (priv->sectorshift - ST25FL1_SECTOR512_SHIFT);
|
2015-08-25 17:10:12 +02:00
|
|
|
|
fvdbg("sector: %ld esectno: %d\n", sector, esectno);
|
|
|
|
|
|
2015-08-26 22:16:45 +02:00
|
|
|
|
DEBUGVERIFY(st25fl1_erase_sector(priv, esectno));
|
2015-08-25 17:10:12 +02:00
|
|
|
|
SET_ERASED(priv);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Put the cached sector data into the erase state and mart the cache as dirty
|
|
|
|
|
* (but don't update the FLASH yet. The caller will do that at a more optimal
|
|
|
|
|
* time).
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
memset(dest, ST25FL1_ERASED_STATE, ST25FL1_SECTOR512_SIZE);
|
|
|
|
|
SET_DIRTY(priv);
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
2015-08-26 22:16:45 +02:00
|
|
|
|
* Name: st25fl1_write_cache
|
2015-08-25 17:10:12 +02:00
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_ST25FL1_SECTOR512
|
2015-08-28 20:01:08 +02:00
|
|
|
|
static int st25fl1_write_cache(FAR struct st25fl1_dev_s *priv,
|
|
|
|
|
FAR const uint8_t *buffer, off_t sector,
|
|
|
|
|
size_t nsectors)
|
2015-08-25 17:10:12 +02:00
|
|
|
|
{
|
|
|
|
|
FAR uint8_t *dest;
|
2015-08-28 20:01:08 +02:00
|
|
|
|
int ret;
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
|
|
|
|
for (; nsectors > 0; nsectors--)
|
|
|
|
|
{
|
|
|
|
|
/* First, make sure that the erase block containing 512 byte sector is in
|
|
|
|
|
* memory.
|
|
|
|
|
*/
|
|
|
|
|
|
2015-08-26 22:16:45 +02:00
|
|
|
|
dest = st25fl1_read_cache(priv, sector);
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
|
|
|
|
/* Erase the block containing this sector if it is not already erased.
|
|
|
|
|
* The erased indicated will be cleared when the data from the erase sector
|
|
|
|
|
* is read into the cache and set here when we erase the sector.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
if (!IS_ERASED(priv))
|
|
|
|
|
{
|
2015-08-26 22:16:45 +02:00
|
|
|
|
off_t esectno = sector >> (priv->sectorshift - ST25FL1_SECTOR512_SHIFT);
|
2015-08-25 17:10:12 +02:00
|
|
|
|
fvdbg("sector: %ld esectno: %d\n", sector, esectno);
|
|
|
|
|
|
2015-08-28 20:01:08 +02:00
|
|
|
|
ret = st25fl1_erase_sector(priv, esectno);
|
|
|
|
|
if (ret < 0)
|
|
|
|
|
{
|
|
|
|
|
fdbg("ERROR: st25fl1_erase_sector failed: %d\n", ret);
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2015-08-25 17:10:12 +02:00
|
|
|
|
SET_ERASED(priv);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Copy the new sector data into cached erase block */
|
|
|
|
|
|
|
|
|
|
memcpy(dest, buffer, ST25FL1_SECTOR512_SIZE);
|
|
|
|
|
SET_DIRTY(priv);
|
|
|
|
|
|
|
|
|
|
/* Set up for the next 512 byte sector */
|
|
|
|
|
|
|
|
|
|
buffer += ST25FL1_SECTOR512_SIZE;
|
|
|
|
|
sector++;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Flush the last erase block left in the cache */
|
|
|
|
|
|
2015-08-28 20:01:08 +02:00
|
|
|
|
return st25fl1_flush_cache(priv);
|
2015-08-25 17:10:12 +02:00
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
|
* Name: st25fl1_erase
|
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
|
|
static int st25fl1_erase(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks)
|
|
|
|
|
{
|
|
|
|
|
FAR struct st25fl1_dev_s *priv = (FAR struct st25fl1_dev_s *)dev;
|
2015-08-26 22:16:45 +02:00
|
|
|
|
size_t blocksleft = nblocks;
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
|
|
|
|
fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
|
|
|
|
|
|
2015-08-26 22:16:45 +02:00
|
|
|
|
/* Lock access to the SPI bus until we complete the erase */
|
|
|
|
|
|
|
|
|
|
st25fl1_lock(priv->qspi);
|
|
|
|
|
|
|
|
|
|
while (blocksleft-- > 0)
|
|
|
|
|
{
|
|
|
|
|
/* Erase each sector */
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_S25FL1_SECTOR512
|
|
|
|
|
st25fl1_erase_cache(priv, startblock);
|
|
|
|
|
#else
|
|
|
|
|
st25fl1_erase_sector(priv, startblock);
|
|
|
|
|
#endif
|
|
|
|
|
startblock++;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_S25FL1_SECTOR512
|
|
|
|
|
/* Flush the last erase block left in the cache */
|
|
|
|
|
|
2015-08-28 20:01:08 +02:00
|
|
|
|
ret = st25fl1_flush_cache(priv);
|
|
|
|
|
if (ret < 0)
|
|
|
|
|
{
|
|
|
|
|
nblocks = ret;
|
|
|
|
|
}
|
2015-08-26 22:16:45 +02:00
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
st25fl1_unlock(priv->qspi);
|
|
|
|
|
return (int)nblocks;
|
2015-08-25 17:10:12 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
|
* Name: st25fl1_bread
|
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
2015-08-26 22:16:45 +02:00
|
|
|
|
static ssize_t st25fl1_bread(FAR struct mtd_dev_s *dev, off_t startblock,
|
|
|
|
|
size_t nblocks, FAR uint8_t *buffer)
|
2015-08-25 17:10:12 +02:00
|
|
|
|
{
|
2015-08-26 22:16:45 +02:00
|
|
|
|
FAR struct st25fl1_dev_s *priv = (FAR struct st25fl1_dev_s *)dev;
|
2015-08-25 17:10:12 +02:00
|
|
|
|
ssize_t nbytes;
|
|
|
|
|
|
|
|
|
|
fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
|
|
|
|
|
|
|
|
|
|
/* On this device, we can handle the block read just like the byte-oriented read */
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_ST25FL1_SECTOR512
|
2015-08-26 22:16:45 +02:00
|
|
|
|
nbytes = st25fl1_read(dev, startblock << ST25FL1_SECTOR512_SHIFT,
|
|
|
|
|
nblocks << ST25FL1_SECTOR512_SHIFT, buffer);
|
2015-08-25 17:10:12 +02:00
|
|
|
|
if (nbytes > 0)
|
|
|
|
|
{
|
|
|
|
|
nbytes >>= ST25FL1_SECTOR512_SHIFT;
|
|
|
|
|
}
|
|
|
|
|
#else
|
2015-08-26 22:16:45 +02:00
|
|
|
|
nbytes = st25fl1_read(dev, startblock << priv->sectorshift,
|
|
|
|
|
nblocks << priv->sectorshift, buffer);
|
2015-08-25 17:10:12 +02:00
|
|
|
|
if (nbytes > 0)
|
|
|
|
|
{
|
2015-08-26 22:16:45 +02:00
|
|
|
|
nbytes >>= priv->sectorshift;
|
2015-08-25 17:10:12 +02:00
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
return nbytes;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
|
* Name: st25fl1_bwrite
|
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
2015-08-26 22:16:45 +02:00
|
|
|
|
static ssize_t st25fl1_bwrite(FAR struct mtd_dev_s *dev, off_t startblock,
|
|
|
|
|
size_t nblocks, FAR const uint8_t *buffer)
|
2015-08-25 17:10:12 +02:00
|
|
|
|
{
|
|
|
|
|
FAR struct st25fl1_dev_s *priv = (FAR struct st25fl1_dev_s *)dev;
|
2015-08-28 20:01:08 +02:00
|
|
|
|
int ret = (int)nblocks;
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
|
|
|
|
fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
|
|
|
|
|
|
|
|
|
|
/* Lock the QuadSPI bus and write all of the pages to FLASH */
|
|
|
|
|
|
2015-08-26 01:20:54 +02:00
|
|
|
|
st25fl1_lock(priv->qspi);
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
|
|
|
|
#if defined(CONFIG_ST25FL1_SECTOR512)
|
2015-08-28 20:01:08 +02:00
|
|
|
|
ret = st25fl1_write_cache(priv, buffer, startblock, nblocks);
|
|
|
|
|
if (ret < 0)
|
|
|
|
|
{
|
|
|
|
|
fdbg("ERROR: st25fl1_write_cache failed: %d\n", ret);
|
|
|
|
|
}
|
|
|
|
|
|
2015-08-25 17:10:12 +02:00
|
|
|
|
#else
|
2015-08-28 20:01:08 +02:00
|
|
|
|
ret = st25fl1_write_page(priv, buffer, startblock << priv->sectorshift,
|
|
|
|
|
nblocks << priv->sectorshift);
|
|
|
|
|
if (ret < 0)
|
|
|
|
|
{
|
|
|
|
|
fdbg("ERROR: st25fl1_write_page failed: %d\n", ret);
|
|
|
|
|
}
|
2015-08-25 17:10:12 +02:00
|
|
|
|
#endif
|
2015-08-28 20:01:08 +02:00
|
|
|
|
|
2015-08-26 01:20:54 +02:00
|
|
|
|
st25fl1_unlock(priv->qspi);
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
2015-08-28 20:01:08 +02:00
|
|
|
|
return ret;
|
2015-08-25 17:10:12 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
|
* Name: st25fl1_read
|
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
|
|
static ssize_t st25fl1_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes,
|
|
|
|
|
FAR uint8_t *buffer)
|
|
|
|
|
{
|
|
|
|
|
FAR struct st25fl1_dev_s *priv = (FAR struct st25fl1_dev_s *)dev;
|
2015-08-28 20:01:08 +02:00
|
|
|
|
int ret;
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
|
|
|
|
fvdbg("offset: %08lx nbytes: %d\n", (long)offset, (int)nbytes);
|
|
|
|
|
|
|
|
|
|
/* Lock the QuadSPI bus and select this FLASH part */
|
|
|
|
|
|
2015-08-26 01:20:54 +02:00
|
|
|
|
st25fl1_lock(priv->qspi);
|
2015-08-28 20:01:08 +02:00
|
|
|
|
ret = st25fl1_read_byte(priv, buffer, offset, nbytes);
|
2015-08-26 01:20:54 +02:00
|
|
|
|
st25fl1_unlock(priv->qspi);
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
2015-08-28 20:01:08 +02:00
|
|
|
|
if (ret < 0)
|
|
|
|
|
{
|
|
|
|
|
fdbg("ERROR: st25fl1_read_byte returned: %d\n", ret);
|
|
|
|
|
return (ssize_t)ret;
|
|
|
|
|
}
|
|
|
|
|
|
2015-08-25 17:10:12 +02:00
|
|
|
|
fvdbg("return nbytes: %d\n", (int)nbytes);
|
2015-08-28 20:01:08 +02:00
|
|
|
|
return (ssize_t)nbytes;
|
2015-08-25 17:10:12 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
|
* Name: st25fl1_ioctl
|
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
|
|
static int st25fl1_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg)
|
|
|
|
|
{
|
|
|
|
|
FAR struct st25fl1_dev_s *priv = (FAR struct st25fl1_dev_s *)dev;
|
|
|
|
|
int ret = -EINVAL; /* Assume good command with bad parameters */
|
|
|
|
|
|
|
|
|
|
fvdbg("cmd: %d \n", cmd);
|
|
|
|
|
|
|
|
|
|
switch (cmd)
|
|
|
|
|
{
|
|
|
|
|
case MTDIOC_GEOMETRY:
|
|
|
|
|
{
|
2015-08-26 22:16:45 +02:00
|
|
|
|
FAR struct mtd_geometry_s *geo =
|
|
|
|
|
(FAR struct mtd_geometry_s *)((uintptr_t)arg);
|
|
|
|
|
|
2015-08-25 17:10:12 +02:00
|
|
|
|
if (geo)
|
|
|
|
|
{
|
|
|
|
|
/* Populate the geometry structure with information need to know
|
|
|
|
|
* the capacity and how to access the device.
|
|
|
|
|
*
|
|
|
|
|
* NOTE: that the device is treated as though it where just an array
|
|
|
|
|
* of fixed size blocks. That is most likely not true, but the client
|
|
|
|
|
* will expect the device logic to do whatever is necessary to make it
|
|
|
|
|
* appear so.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_ST25FL1_SECTOR512
|
|
|
|
|
geo->blocksize = (1 << ST25FL1_SECTOR512_SHIFT);
|
|
|
|
|
geo->erasesize = (1 << ST25FL1_SECTOR512_SHIFT);
|
2015-08-26 22:16:45 +02:00
|
|
|
|
geo->neraseblocks = priv->nsectors << (priv->sectorshift - ST25FL1_SECTOR512_SHIFT);
|
2015-08-25 17:10:12 +02:00
|
|
|
|
#else
|
2015-08-26 22:16:45 +02:00
|
|
|
|
geo->blocksize = (1 << priv->sectorshift);
|
|
|
|
|
geo->erasesize = (1 << priv->sectorshift);
|
2015-08-25 17:10:12 +02:00
|
|
|
|
geo->neraseblocks = priv->nsectors;
|
|
|
|
|
#endif
|
|
|
|
|
ret = OK;
|
|
|
|
|
|
|
|
|
|
fvdbg("blocksize: %d erasesize: %d neraseblocks: %d\n",
|
|
|
|
|
geo->blocksize, geo->erasesize, geo->neraseblocks);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case MTDIOC_BULKERASE:
|
|
|
|
|
{
|
2015-08-26 22:16:45 +02:00
|
|
|
|
/* Erase the entire device */
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
2015-08-26 22:16:45 +02:00
|
|
|
|
st25fl1_lock(priv->qspi);
|
|
|
|
|
ret = st25fl1_erase_chip(priv);
|
|
|
|
|
st25fl1_unlock(priv->qspi);
|
2015-08-25 17:10:12 +02:00
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
2015-08-29 23:58:54 +02:00
|
|
|
|
case MTDIOC_PROTECT:
|
|
|
|
|
{
|
|
|
|
|
FAR const struct mtd_protect_s *prot =
|
|
|
|
|
(FAR const struct mtd_protect_s *)((uintptr_t)arg);
|
|
|
|
|
|
|
|
|
|
DEBUGASSERT(prot);
|
|
|
|
|
ret = st25fl1_protect(priv, prot->startblock, prot->nblocks);
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case MTDIOC_UNPROTECT:
|
|
|
|
|
{
|
|
|
|
|
FAR const struct mtd_protect_s *prot =
|
|
|
|
|
(FAR const struct mtd_protect_s *)((uintptr_t)arg);
|
|
|
|
|
|
|
|
|
|
DEBUGASSERT(prot);
|
|
|
|
|
ret = st25fl1_unprotect(priv, prot->startblock, prot->nblocks);
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
2015-08-25 17:10:12 +02:00
|
|
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default:
|
2015-08-29 23:58:54 +02:00
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|
ret = -ENOTTY; /* Bad/unsupported command */
|
2015-08-25 17:10:12 +02:00
|
|
|
|
break;
|
|
|
|
|
}
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|
|
|
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|
|
|
|
|
fvdbg("return %d\n", ret);
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
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|
|
|
* Public Functions
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|
|
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************************************************************************************/
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|
|
/************************************************************************************
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|
|
|
|
* Name: st25fl1_initialize
|
|
|
|
|
*
|
|
|
|
|
* Description:
|
2015-08-31 17:25:14 +02:00
|
|
|
|
* Create an initialize MTD device instance for the QuadSPI-based ST24FL1
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|
|
|
|
* FLASH part.
|
|
|
|
|
*
|
|
|
|
|
* MTD devices are not registered in the file system, but are created as instances
|
|
|
|
|
* that can be bound to other functions (such as a block or character driver front
|
|
|
|
|
* end).
|
2015-08-25 17:10:12 +02:00
|
|
|
|
*
|
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
2015-08-26 22:16:45 +02:00
|
|
|
|
FAR struct mtd_dev_s *st25fl1_initialize(FAR struct qspi_dev_s *qspi)
|
2015-08-25 17:10:12 +02:00
|
|
|
|
{
|
|
|
|
|
FAR struct st25fl1_dev_s *priv;
|
2015-08-26 22:16:45 +02:00
|
|
|
|
uint8_t status[3];
|
2015-08-25 17:10:12 +02:00
|
|
|
|
int ret;
|
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|
|
|
|
2015-08-26 01:20:54 +02:00
|
|
|
|
fvdbg("qspi: %p\n", qspi);
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
|
|
|
|
/* Allocate a state structure (we allocate the structure instead of using
|
|
|
|
|
* a fixed, static allocation so that we can handle multiple FLASH devices.
|
|
|
|
|
* The current implementation would handle only one FLASH part per QuadSPI
|
2015-08-26 01:20:54 +02:00
|
|
|
|
* device (only because of the QSPIDEV_FLASH definition) and so would have
|
2015-08-25 17:10:12 +02:00
|
|
|
|
* to be extended to handle multiple FLASH parts on the same QuadSPI bus.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
priv = (FAR struct st25fl1_dev_s *)kmm_zalloc(sizeof(struct st25fl1_dev_s));
|
|
|
|
|
if (priv)
|
|
|
|
|
{
|
|
|
|
|
/* Initialize the allocated structure (unsupported methods were
|
|
|
|
|
* nullified by kmm_zalloc).
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
priv->mtd.erase = st25fl1_erase;
|
|
|
|
|
priv->mtd.bread = st25fl1_bread;
|
|
|
|
|
priv->mtd.bwrite = st25fl1_bwrite;
|
|
|
|
|
priv->mtd.read = st25fl1_read;
|
|
|
|
|
priv->mtd.ioctl = st25fl1_ioctl;
|
2015-08-26 01:20:54 +02:00
|
|
|
|
priv->qspi = qspi;
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
|
|
|
|
/* Identify the FLASH chip and get its capacity */
|
|
|
|
|
|
|
|
|
|
ret = st25fl1_readid(priv);
|
|
|
|
|
if (ret != OK)
|
|
|
|
|
{
|
|
|
|
|
/* Unrecognized! Discard all of that work we just did and return NULL */
|
|
|
|
|
|
2015-08-26 22:16:45 +02:00
|
|
|
|
fdbg("ERROR Unrecognized QSPI device\n");
|
2015-08-25 17:10:12 +02:00
|
|
|
|
kmm_free(priv);
|
2015-08-26 22:16:45 +02:00
|
|
|
|
return NULL;
|
2015-08-25 17:10:12 +02:00
|
|
|
|
}
|
2015-08-26 22:16:45 +02:00
|
|
|
|
|
|
|
|
|
/* Enable quad mode */
|
|
|
|
|
|
|
|
|
|
status[0] = sf25fl1_read_status1(priv->qspi);
|
|
|
|
|
status[1] = sf25fl1_read_status2(priv->qspi);
|
|
|
|
|
status[2] = sf25fl1_read_status3(priv->qspi);
|
|
|
|
|
|
|
|
|
|
while ((status[1] & STATUS2_QUAD_ENABLE_MASK) == 0)
|
2015-08-25 17:10:12 +02:00
|
|
|
|
{
|
2015-08-26 22:16:45 +02:00
|
|
|
|
status[1] |= STATUS2_QUAD_ENABLE;
|
|
|
|
|
st25fl1_write_status(priv->qspi, status);
|
|
|
|
|
status[1] = sf25fl1_read_status2(priv->qspi);
|
|
|
|
|
usleep(50*1000);
|
|
|
|
|
}
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_ST25FL1_SECTOR512 /* Simulate a 512 byte sector */
|
2015-08-26 22:16:45 +02:00
|
|
|
|
/* Allocate a buffer for the erase block cache */
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
2015-08-26 22:16:45 +02:00
|
|
|
|
priv->sector = (FAR uint8_t *)kmm_malloc((1 << priv->sectorshift));
|
|
|
|
|
if (!priv->sector)
|
|
|
|
|
{
|
|
|
|
|
/* Allocation failed! Discard all of that work we just did and return NULL */
|
2015-08-25 17:10:12 +02:00
|
|
|
|
|
2015-08-26 22:16:45 +02:00
|
|
|
|
fdbg("ERROR: Allocation failed\n");
|
|
|
|
|
kmm_free(priv);
|
|
|
|
|
return NULL;
|
2015-08-25 17:10:12 +02:00
|
|
|
|
}
|
2015-08-26 22:16:45 +02:00
|
|
|
|
#endif
|
2015-08-25 17:10:12 +02:00
|
|
|
|
}
|
|
|
|
|
|
2015-08-26 15:16:07 +02:00
|
|
|
|
#ifdef CONFIG_MTD_REGISTRATION
|
2015-08-25 17:10:12 +02:00
|
|
|
|
/* Register the MTD with the procfs system if enabled */
|
|
|
|
|
|
|
|
|
|
mtd_register(&priv->mtd, "st25fl1");
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* Return the implementation-specific state structure as the MTD device */
|
|
|
|
|
|
|
|
|
|
fvdbg("Return %p\n", priv);
|
|
|
|
|
return (FAR struct mtd_dev_s *)priv;
|
|
|
|
|
}
|