2020-03-05 03:26:21 +01:00
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/****************************************************************************
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2020-03-06 03:28:03 +01:00
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* libs/libc/machine/xtensa/arch_elf.c
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2020-03-05 03:26:21 +01:00
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*
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2020-03-06 03:33:16 +01:00
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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2020-03-05 03:26:21 +01:00
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*
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2020-03-06 03:33:16 +01:00
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* http://www.apache.org/licenses/LICENSE-2.0
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2020-03-05 03:26:21 +01:00
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*
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2020-03-06 03:33:16 +01:00
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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2020-03-05 03:26:21 +01:00
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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2020-03-05 11:11:32 +01:00
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#include <assert.h>
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2020-03-05 03:26:21 +01:00
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#include <stdlib.h>
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#include <errno.h>
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#include <debug.h>
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#include <nuttx/elf.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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2022-05-14 10:01:52 +02:00
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static bool is_l32r(const unsigned char *p)
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2020-03-05 11:11:32 +01:00
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{
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return (p[0] & 0xf) == 1;
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}
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2020-03-05 03:26:21 +01:00
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_checkarch
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*
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* Description:
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* Given the ELF header in 'hdr', verify that the ELF file is appropriate
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* for the current, configured architecture. Every architecture that uses
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* the ELF loader must provide this function.
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*
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* Input Parameters:
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* hdr - The ELF header read from the ELF file.
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*
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* Returned Value:
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* True if the architecture supports this ELF file.
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*
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****************************************************************************/
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2022-05-14 10:01:52 +02:00
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bool up_checkarch(const Elf32_Ehdr *ehdr)
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2020-03-05 03:26:21 +01:00
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{
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/* Make sure it's an Xtensa executable */
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if (ehdr->e_machine != EM_XTENSA)
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{
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berr("ERROR: Not for Xtensa: e_machine=%04x\n", ehdr->e_machine);
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return false;
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}
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/* Make sure that 32-bit objects are supported */
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if (ehdr->e_ident[EI_CLASS] != ELFCLASS32)
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{
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2020-03-10 07:06:34 +01:00
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berr("ERROR: Need 32-bit objects: e_ident[EI_CLASS]=%02x\n",
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ehdr->e_ident[EI_CLASS]);
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2020-03-05 03:26:21 +01:00
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return false;
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}
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/* Verify endian-ness */
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#ifdef CONFIG_ENDIAN_BIG
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2020-03-05 11:11:32 +01:00
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#error not implemented
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2020-03-05 03:26:21 +01:00
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if (ehdr->e_ident[EI_DATA] != ELFDATA2MSB)
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#else
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if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB)
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#endif
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{
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2020-03-10 07:06:34 +01:00
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berr("ERROR: Wrong endian-ness: e_ident[EI_DATA]=%02x\n",
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ehdr->e_ident[EI_DATA]);
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2020-03-05 03:26:21 +01:00
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return false;
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}
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return true;
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}
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/****************************************************************************
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* Name: up_relocate and up_relocateadd
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*
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* Description:
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2021-03-10 21:13:31 +01:00
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* Perform an architecture-specific ELF relocation. Every architecture
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2020-03-05 03:26:21 +01:00
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* that uses the ELF loader must provide this function.
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*
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* Input Parameters:
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* rel - The relocation type
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* sym - The ELF symbol structure containing the fully resolved value.
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* There are a few relocation types for a few architectures that do
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* not require symbol information. For those, this value will be
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* NULL. Implementations of these functions must be able to handle
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* that case.
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* addr - The address that requires the relocation.
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*
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* Returned Value:
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* Zero (OK) if the relocation was successful. Otherwise, a negated errno
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* value indicating the cause of the relocation failure.
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*
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****************************************************************************/
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riscv/arch_elf.c: Handle PCREL_HI20/LO12_I/S relocations correctly
There is a problem with the current elf loader for risc-v: when a pair of
PCREL_HI20 / LO12 relocations are encountered, it is assumed that these
will follow each other immediately, as follows:
label:
auipc a0, %pcrel_hi(symbol) // R_RISCV_PCREL_HI20
load/store a0, %pcrel_lo(label)(a0) // R_RISCV_PCREL_LO12_I/S
With this assumption, the hi/lo relocations are both done when a hi20
relocation entry is encountered, first to the current instruction (addr)
and to the next instruction (addr + 4).
However, this assumption is wrong. There is nothing in the elf relocation
specification[1] that mandates this. Thus, the hi/lo relocation always
needs to first fixup the hi-part, and when the lo-part is encountered, it
needs to find the corresponding hi relocation entry, via the given "label".
This necessitates (re-)visiting the relocation entries for the current
section as well as looking for "label" in the symbol table.
The NuttX elf loader does not allow such operations to be done in the
machine specific part, so this patch fixes the relocation issue by
introducing an architecture specific cache for the hi20 relocation and
symbol table entries. When a lo12 relocation is encountered, the cache
can be consulted to find the hi20 part.
[1] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc
2023-12-05 11:30:46 +01:00
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int up_relocate(const Elf32_Rel *rel, const Elf32_Sym *sym, uintptr_t addr,
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void *arch_data)
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2020-03-05 03:26:21 +01:00
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{
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unsigned int relotype;
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/* All relocations except NONE depend upon having valid symbol
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* information.
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*/
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relotype = ELF32_R_TYPE(rel->r_info);
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if (sym == NULL && relotype != R_XTENSA_NONE)
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{
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return -EINVAL;
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}
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/* Handle the relocation by relocation type */
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switch (relotype)
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{
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case R_XTENSA_NONE:
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{
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/* No relocation */
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}
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break;
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default:
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2020-03-05 11:11:32 +01:00
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berr("ERROR: Unsupported relocation: %u\n", relotype);
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2020-03-05 03:26:21 +01:00
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return -EINVAL;
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}
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return OK;
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}
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2022-05-14 10:01:52 +02:00
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int up_relocateadd(const Elf32_Rela *rel, const Elf32_Sym *sym,
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riscv/arch_elf.c: Handle PCREL_HI20/LO12_I/S relocations correctly
There is a problem with the current elf loader for risc-v: when a pair of
PCREL_HI20 / LO12 relocations are encountered, it is assumed that these
will follow each other immediately, as follows:
label:
auipc a0, %pcrel_hi(symbol) // R_RISCV_PCREL_HI20
load/store a0, %pcrel_lo(label)(a0) // R_RISCV_PCREL_LO12_I/S
With this assumption, the hi/lo relocations are both done when a hi20
relocation entry is encountered, first to the current instruction (addr)
and to the next instruction (addr + 4).
However, this assumption is wrong. There is nothing in the elf relocation
specification[1] that mandates this. Thus, the hi/lo relocation always
needs to first fixup the hi-part, and when the lo-part is encountered, it
needs to find the corresponding hi relocation entry, via the given "label".
This necessitates (re-)visiting the relocation entries for the current
section as well as looking for "label" in the symbol table.
The NuttX elf loader does not allow such operations to be done in the
machine specific part, so this patch fixes the relocation issue by
introducing an architecture specific cache for the hi20 relocation and
symbol table entries. When a lo12 relocation is encountered, the cache
can be consulted to find the hi20 part.
[1] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc
2023-12-05 11:30:46 +01:00
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uintptr_t addr, void *arch_data)
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2020-03-05 03:26:21 +01:00
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{
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2020-03-05 11:11:32 +01:00
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unsigned int relotype;
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unsigned char *p;
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uint32_t value;
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2020-03-10 10:46:06 +01:00
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/* All relocations except NONE depend upon having valid symbol
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* information.
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*/
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2020-03-05 11:11:32 +01:00
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relotype = ELF32_R_TYPE(rel->r_info);
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2020-03-10 10:46:06 +01:00
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if (sym == NULL)
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{
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if (relotype != R_XTENSA_NONE)
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{
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return -EINVAL;
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}
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}
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else
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{
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value = sym->st_value + rel->r_addend;
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}
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2020-03-05 11:11:32 +01:00
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/* Handle the relocation by relocation type */
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switch (relotype)
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{
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2020-03-10 10:46:06 +01:00
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case R_XTENSA_NONE:
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break;
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2020-03-05 11:11:32 +01:00
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case R_XTENSA_32:
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2022-05-14 10:01:52 +02:00
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(*(uint32_t *)addr) += value;
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2020-03-05 11:11:32 +01:00
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break;
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case R_XTENSA_ASM_EXPAND:
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bwarn("WARNING: Ignoring RELA relocation R_XTENSA_ASM_EXPAND %u\n",
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relotype);
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break;
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case R_XTENSA_SLOT0_OP:
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2022-05-14 10:01:52 +02:00
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p = (unsigned char *)addr;
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2020-03-05 11:11:32 +01:00
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if (is_l32r(p))
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{
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/* Xtensa ISA:
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* L32R forms a virtual address by adding the 16-bit one-extended
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* constant value encoded in the instruction word shifted left by
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* two to the address of the L32R plus three with the two least
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* significant bits cleared.
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*/
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uintptr_t base = (addr + 3) & ~3;
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uint16_t imm = (value - base) >> 2;
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if (base + (0xfffc0000 | ((uint32_t)imm << 2)) != value)
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{
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berr("ERROR: Out of range rellocation at %p\n", p);
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return -EINVAL;
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}
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p[1] = imm & 0xff;
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p[2] = (imm >> 8) & 0xff;
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break;
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}
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bwarn("WARNING: Ignoring RELA relocation R_XTENSA_SLOT0_OP %u\n",
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relotype);
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break;
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default:
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berr("ERROR: RELA relocation %u not supported\n", relotype);
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return -EINVAL;
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}
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return OK;
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2020-03-05 03:26:21 +01:00
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}
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