2017-05-21 22:14:09 +02:00
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/****************************************************************************
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* drivers/audio/cs43l22.h
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*
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* Copyright (C) 2017 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Reference:
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* "CS43L22 Ultra Low Power CODEC for Portable Audio Applications, Pre-
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* Production", September 2012, Rev 3.3, Wolfson Microelectronics
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __DRIVERS_AUDIO_CS43L22_H
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#define __DRIVERS_AUDIO_CS43L22_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/compiler.h>
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#include <pthread.h>
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#include <mqueue.h>
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#include <nuttx/wqueue.h>
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#include <nuttx/fs/ioctl.h>
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#define getreg32(a) (*(volatile uint32_t *)(a))
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#define putreg32(v,a) (*(volatile uint32_t *)(a) = (v))
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#define getreg16(a) (*(volatile uint16_t *)(a))
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#define putreg16(v,a) (*(volatile uint16_t *)(a) = (v))
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#ifdef CONFIG_AUDIO
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/****************************************************************************
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* Pre-Processor Definitions
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****************************************************************************/
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2020-04-21 09:45:24 +02:00
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2017-05-21 22:14:09 +02:00
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/* So far, I have not been able to get FLL lock interrupts. Worse, I have
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* been able to get the FLL to claim that it is locked at all even when
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* polling. What am I doing wrong?
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*
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* Hmmm.. seems unnecessary anyway
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*/
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#undef CS43L22_USE_FFLOCK_INT
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#undef CS43L22_USE_FFLOCK_POLL
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/* Registers Addresses ******************************************************/
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#define CS43L22_ID_REV 0x01 /* Chip I.D. and Revision */
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#define CS43L22_POWER_CTRL1 0x02 /* Power Control 1 */
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#define CS43L22_POWER_CTRL2 0x04 /* Power Control 2 */
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#define CS43L22_CLOCK_CTRL 0x05 /* Clocking Control */
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#define CS43L22_INTERFACE_CTRL1 0x06 /* Interface Control 1 */
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#define CS43L22_INTERFACE_CTRL2 0x07 /* Interface Control 2 */
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#define CS43L22_PASS_SEL_A 0x08 /* Passthrough x Select: PassA */
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#define CS43L22_PASS_SEL_B 0x09 /* Passthrough x Select: PassB */
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#define CS43L22_ANLG_ZC_SR_SEL 0x0A /* Analog ZC and SR Settings */
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#define CS43L22_PASS_GANG_CTRL 0x0C /* Passthrough Gang Control */
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#define CS43L22_PLAYBACK_CTRL1 0x0D /* Playback Control 1 */
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#define CS43L22_MISCLLNS_CTRL 0x0E /* Miscellaneous Controls */
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#define CS43L22_PLAYBACK_CTRL2 0x0F /* Playback Control 2 */
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#define CS43L22_PASS_VOL_A 0x14 /* Passthrough x Volume: PASSAVOL */
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#define CS43L22_PASS_VOL_B 0x15 /* Passthrough x Volume: PASSBVOL */
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#define CS43L22_PCM_VOL_A 0x1A /* PCMx Volume: PCMA */
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#define CS43L22_PCM_VOL_B 0x1B /* PCMx Volume: PCMB */
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#define CS43L22_BP_FREQ_ON_TIME 0x1C /* Beep Frequency & On Time */
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#define CS43L22_BP_VOL_OFF_TIME 0x1D /* Beep Volume & Off Time */
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#define CS43L22_BP_TONE_CFG 0x1E /* Beep & Tone Configuration */
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#define CS43L22_TONE_CTRL 0x1F /* Tone Control */
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#define CS43L22_MS_VOL_CTRL_A 0x20 /* Master Volume Control: MSTA */
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#define CS43L22_MS_VOL_CTRL_B 0x21 /* Master Volume Control: MSTB */
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#define CS43L22_HP_VOL_CTRL_A 0x22 /* Headphone Volume Control: HPA */
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#define CS43L22_HP_VOL_CTRL_B 0x23 /* Headphone Volume Control: HPB */
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#define CS43L22_SPK_VOL_CTRL_A 0x24 /* Speaker Volume Control: SPKA */
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#define CS43L22_SPK_VOL_CTRL_B 0x25 /* Speaker Volume Control: SPKB */
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#define CS43L22_PCM_CH_SWAP 0x26 /* PCM Channel Swap */
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#define CS43L22_LIM_CTRL1 0x27 /* Limiter Control 1, Min/Max Thresholds */
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#define CS43L22_LIM_CTRL2 0x28 /* Limiter Control 2, Release Rate */
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#define CS43L22_LIM_ATTACK_RATE 0x29 /* Limiter Attack Rate */
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#define CS43L22_STATUS 0x2E /* Status */
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#define CS43L22_BAT_COMP 0x2F /* Battery Compensation */
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#define CS43L22_VP_BAT_LEVEL 0x30 /* VP Battery Level */
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#define CS43L22_SPK_STATUS 0x31 /* Speaker Status */
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#define CS43L22_TEMP_MON_CTRL 0x32 /* Temperature Monitor Control */
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#define CS43L22_THERMAL_FOLDBACK 0x33 /* Thermal Foldback */
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#define CS43L22_CHRG_PUMP_FREQ 0x34 /* Charge Pump Frequency */
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#define CS43L22_HPBMUTE (1 << 7)
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#define CS43L22_HPAMUTE (1 << 6)
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#define CS43L22_SPKBMUTE (1 << 5)
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#define CS43L22_SPKAMUTE (1 << 4)
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/* Register Default Values **************************************************/
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2020-04-21 09:45:24 +02:00
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/* Registers have some undocumented bits set on power up.
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* These probably should be retained on writes (?).
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2017-05-21 22:14:09 +02:00
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*/
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#define CS43L22_ID_REV_DEFAULT 0xe3 /* Chip I.D. and Revision */
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#define CS43L22_POWER_CTRL1_DEFAULT 0x01 /* Power Control 1 */
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#define CS43L22_POWER_CTRL2_DEFAULT 0x05 /* Power Control 2 */
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#define CS43L22_CLOCK_CTRL_DEFAULT 0xa0 /* Clocking Control */
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#define CS43L22_INTERFACE_CTRL1_DEFAULT 0x00 /* Interface Control 1 */
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#define CS43L22_INTERFACE_CTRL2_DEFAULT 0x00 /* Interface Control 2 */
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#define CS43L22_PASS_SEL_A_DEFAULT 0x81 /* Passthrough x Select: PassA */
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#define CS43L22_PASS_SEL_B_DEFAULT 0x81 /* Passthrough x Select: PassB */
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#define CS43L22_ANLG_ZC_SR_SEL_DEFAULT 0xa5 /* Analog ZC and SR Settings */
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#define CS43L22_PASS_GANG_CTRL_DEFAULT 0x00 /* Passthrough Gang Control */
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#define CS43L22_PLAYBACK_CTRL1_DEFAULT 0x60 /* Playback Control 1 */
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#define CS43L22_MISCLLNS_CTRL_DEFAULT 0x02 /* Miscellaneous Controls */
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#define CS43L22_PLAYBACK_CTRL2_DEFAULT 0x00 /* Playback Control 2 */
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#define CS43L22_PASS_VOL_A_DEFAULT 0x00 /* Passthrough x Volume: PASSAVOL */
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#define CS43L22_PASS_VOL_B_DEFAULT 0x00 /* Passthrough x Volume: PASSBVOL */
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#define CS43L22_PCM_VOL_A_DEFAULT 0x00 /* PCMx Volume: PCMA */
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#define CS43L22_PCM_VOL_B_DEFAULT 0x00 /* PCMx Volume: PCMB */
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#define CS43L22_BP_FREQ_ON_TIME_DEFAULT 0x00 /* Beep Frequency & On Time */
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#define CS43L22_BP_VOL_OFF_TIME_DEFAULT 0x00 /* Beep Volume & Off Time */
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#define CS43L22_BP_TONE_CFG_DEFAULT 0x00 /* Beep & Tone Configuration */
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#define CS43L22_TONE_CTRL_DEFAULT 0x88 /* Tone Control */
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#define CS43L22_MS_VOL_CTRL_A_DEFAULT 0x00 /* Master Volume Control: MSTA */
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#define CS43L22_MS_VOL_CTRL_B_DEFAULT 0x00 /* Master Volume Control: MSTB */
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#define CS43L22_HP_VOL_CTRL_A_DEFAULT 0x00 /* Headphone Volume Control: HPA */
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#define CS43L22_HP_VOL_CTRL_B_DEFAULT 0x00 /* Headphone Volume Control: HPB */
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#define CS43L22_SPK_VOL_CTRL_A_DEFAULT 0x00 /* Speaker Volume Control: SPKA */
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#define CS43L22_SPK_VOL_CTRL_B_DEFAULT 0x00 /* Speaker Volume Control: SPKB */
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#define CS43L22_PCM_CH_SWAP_DEFAULT 0x00 /* PCM Channel Swap */
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#define CS43L22_LIM_CTRL1_DEFAULT 0x00 /* Limiter Control 1, Min/Max Thresholds */
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#define CS43L22_LIM_CTRL2_DEFAULT 0x7f /* Limiter Control 2, Release Rate */
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#define CS43L22_LIM_ATTACK_RATE_DEFAULT 0xc0 /* Limiter Attack Rate */
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#define CS43L22_STATUS_DEFAULT 0x00 /* Status */
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#define CS43L22_BAT_COMP_DEFAULT 0x00 /* Battery Compensation */
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#define CS43L22_VP_BAT_LEVEL_DEFAULT 0x00 /* VP Battery Level */
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#define CS43L22_SPK_STATUS_DEFAULT 0x00 /* Speaker Status */
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#define CS43L22_TEMP_MON_CTRL_DEFAULT 0x3b /* Temperature Monitor Control */
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#define CS43L22_THERMAL_FOLDBACK_DEFAULT 0x00 /* Thermal Foldback */
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#define CS43L22_CHRG_PUMP_FREQ_DEFAULT 0x5f /* Charge Pump Frequency */
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/* Register Bit Definitions *************************************************/
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/* 0x01 Chip I.D. and Revision (Read Only) */
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#define CS43L22_DEV_ID_REV (0xe3)
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#define CS43L22_ID_SHIFT (3)
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#define CS43L22_ID_MASK (0x1f << CS43L22_ID_SHIFT)
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#define CS43L22_REV_SHIFT (0)
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#define CS43L22_REV_MASK (0x07 << CS43L22_REV_SHIFT)
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/* 0x02 Power Control 1 */
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#define CS43L22_POWER_DOWN (0x01) /* Powered Down */
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#define CS43L22_POWER_UP (0x9e) /* Powered Up */
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/* 0x04 Power Control 2 */
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#define CS43L22_PDN_HPB_SHIFT (6) /* Bits 6-7: Headphone channel B Control */
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#define CS43L22_PDN_HPB_ON_HW_PIN_LO (0 << CS43L22_PDN_HPB_SHIFT) /* PDN_HPx[1:0] 00 Headphone channel is ON when the SPK/HP_SW pin, 6, is LO
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2020-04-21 09:45:24 +02:00
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* Headphone channel is OFF when the SPK/HP_SW pin, 6, is HI
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*/
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2017-05-21 22:14:09 +02:00
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#define CS43L22_PDN_HPB_ON_HW_PIN_HI (1 << CS43L22_PDN_HPB_SHIFT) /* PDN_HPx[1:0] 01 Headphone channel is ON when the SPK/HP_SW pin, 6, is HI
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2020-04-21 09:45:24 +02:00
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* Headphone channel is OFF when the SPK/HP_SW pin, 6, is LO
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*/
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2017-05-21 22:14:09 +02:00
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#define CS43L22_PDN_HPB_ON (2 << CS43L22_PDN_HPB_SHIFT) /* PDN_HPx[1:0] 10 Headphone channel is always ON */
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#define CS43L22_PDN_HPB_OFF (3 << CS43L22_PDN_HPB_SHIFT) /* PDN_HPx[1:0] 11 Headphone channel is always OFF */
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#define CS43L22_PDN_HPA_SHIFT (4) /* Bits 4-5: Headphone channel A Control */
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#define CS43L22_PDN_HPA_ON_HW_PIN_LO (0 << CS43L22_PDN_HPA_SHIFT) /* PDN_HPx[1:0] 00 Headphone channel is ON when the SPK/HP_SW pin, 6, is LO
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2020-04-21 09:45:24 +02:00
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* Headphone channel is OFF when the SPK/HP_SW pin, 6, is HI */
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2017-05-21 22:14:09 +02:00
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#define CS43L22_PDN_HPA_ON_HW_PIN_HI (1 << CS43L22_PDN_HPA_SHIFT) /* PDN_HPx[1:0] 01 Headphone channel is ON when the SPK/HP_SW pin, 6, is HI
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2020-04-21 09:45:24 +02:00
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* Headphone channel is OFF when the SPK/HP_SW pin, 6, is LO
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*/
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2017-05-21 22:14:09 +02:00
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#define CS43L22_PDN_HPA_ON (2 << CS43L22_PDN_HPA_SHIFT) /* PDN_HPx[1:0] 10 Headphone channel is always ON */
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#define CS43L22_PDN_HPA_OFF (3 << CS43L22_PDN_HPA_SHIFT) /* PDN_HPx[1:0] 11 Headphone channel is always OFF */
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#define CS43L22_PDN_SPKB_SHIFT (2) /* Bits 2-3: Speaker channel B Control */
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#define CS43L22_PDN_SPKB_ON_HW_PIN_LO (0 << CS43L22_PDN_SPKB_SHIFT) /* PDN_HPx[1:0] 00 Speaker channel is ON when the SPK/HP_SW pin, 6, is LO
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2020-04-21 09:45:24 +02:00
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* Speaker channel is OFF when the SPK/HP_SW pin, 6, is HI
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*/
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2017-05-21 22:14:09 +02:00
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#define CS43L22_PDN_SPKB_ON_HW_PIN_HI (1 << CS43L22_PDN_SPKB_SHIFT) /* PDN_HPx[1:0] 01 Speaker channel is ON when the SPK/HP_SW pin, 6, is HI
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2020-04-21 09:45:24 +02:00
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* Speaker channel is OFF when the SPK/HP_SW pin, 6, is LO
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*/
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2017-05-21 22:14:09 +02:00
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#define CS43L22_PDN_SPKB_ON (2 << CS43L22_PDN_SPKB_SHIFT) /* PDN_HPx[1:0] 10 Speaker channel is always ON */
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#define CS43L22_PDN_SPKB_OFF (3 << CS43L22_PDN_SPKB_SHIFT) /* PDN_HPx[1:0] 11 Speaker channel is always OFF */
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#define CS43L22_PDN_SPKA_SHIFT (0) /* Bits 0-1: Speaker channel A Control */
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#define CS43L22_PDN_SPKA_ON_HW_PIN_LO (0 << CS43L22_PDN_SPKA_SHIFT) /* PDN_HPx[1:0] 00 Speaker channel is ON when the SPK/HP_SW pin, 6, is LO
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2020-04-21 09:45:24 +02:00
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* Speaker channel is OFF when the SPK/HP_SW pin, 6, is HI
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*/
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2017-05-21 22:14:09 +02:00
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#define CS43L22_PDN_SPKA_ON_HW_PIN_HI (1 << CS43L22_PDN_SPKA_SHIFT) /* PDN_HPx[1:0] 01 Speaker channel is ON when the SPK/HP_SW pin, 6, is HI
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2020-04-21 09:45:24 +02:00
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* Speaker channel is OFF when the SPK/HP_SW pin, 6, is LO
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*/
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2017-05-21 22:14:09 +02:00
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#define CS43L22_PDN_SPKA_ON (2 << CS43L22_PDN_SPKA_SHIFT) /* PDN_HPx[1:0] 10 Speaker channel is always ON */
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#define CS43L22_PDN_SPKA_OFF (3 << CS43L22_PDN_SPKA_SHIFT) /* PDN_HPx[1:0] 11 Speaker channel is always OFF */
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/* 0x05 Clocking Control */
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#define CS43L22_AUTO_DETECT_ENABLE (1 << 7) /* Auto-detection of speed mode enable */
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#define CS43L22_SPEED_SHIFT (5) /* Bits 5-6: Speed mode */
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#define CS43L22_SPEED_DOUBLE (0 << CS43L22_SPEED_SHIFT) /* Slave: Double-Speed Mode (DSM - 50 kHz -100 kHz Fs) Master: MCLK=512 SCLK=64*/
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#define CS43L22_SPEED_SINGLE (1 << CS43L22_SPEED_SHIFT) /* Slave: Single-Speed Mode (SSM - 4 kHz -50 kHz Fs) Master: MCLK=256 SCLK=64*/
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#define CS43L22_SPEED_HALF (2 << CS43L22_SPEED_SHIFT) /* Slave: Half-Speed Mode (HSM - 12.5kHz -25 kHz Fs) Master: MCLK=128 SCLK=64*/
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#define CS43L22_SPEED_QUARTER (3 << CS43L22_SPEED_SHIFT) /* Slave: Quarter-Speed Mode (QSM - 4 kHz -12.5 kHz Fs)Master: MCLK=128 SCLK=64*/
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#define CS43L22_32k_GROUP_ENABLE (1 << 4) /* Bit 4: Specifies whether or not the input/output sample rate is 8 kHz, 16 kHz or 32 kHz */
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#define CS43L22_VIDEOCLK_ENABLE (1 << 3) /* Bit 3: Specifies whether or not the external MCLK frequency is 27 MHz */
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#define CS43L22_MCLK_LRCK_RATIO_SHIFT (1) /* Bits 1-2: Internal MCLK/LRCK Ratio */
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2020-04-21 09:45:24 +02:00
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2017-05-21 22:14:09 +02:00
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#define CS43L22_RATIO_128_64 (0 << CS43L22_MCLK_LRCK_RATIO_SHIFT) /* RATIO[1:0] Internal MCLK Cycles per LRCK=128, SCLK/LRCK=64 Ratio in Master Mode */
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#define CS43L22_RATIO_125_62 (1 << CS43L22_MCLK_LRCK_RATIO_SHIFT) /* RATIO[1:0] Internal MCLK Cycles per LRCK=125, SCLK/LRCK=62 Ratio in Master Mode */
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#define CS43L22_RATIO_132_66 (2 << CS43L22_MCLK_LRCK_RATIO_SHIFT) /* RATIO[1:0] Internal MCLK Cycles per LRCK=132, SCLK/LRCK=66 Ratio in Master Mode */
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#define CS43L22_RATIO_136_68 (3 << CS43L22_MCLK_LRCK_RATIO_SHIFT) /* RATIO[1:0] Internal MCLK Cycles per LRCK=136, SCLK/LRCK=68 Ratio in Master Mode */
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#define CS43L22_CLKDIV2_ENABLE (1 << 0) /* Bit 0: Divided by 2 */
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/* 0x06 Interface Control 1 */
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#define CS43L22_MODE_MASTER (1 << 7) /* Configures the serial port I/O clocking */
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#define CS43L22_SCLK_POLARITY_INVERT (1 << 6) /* Configures the polarity of the SCLK signal */
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#define CS43L22_DSP_MODE_ENABLE (1 << 4) /* Configures a data-packed interface format for the DAC */
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2020-04-21 09:45:24 +02:00
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#define CS43L22_DAC_IF_FORMAT_SHIFT (2) /* Bits 2-3: Configures the digital interface format for data on SDIN */
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2017-05-21 22:14:09 +02:00
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#define CS43L22_DAC_IF_LEFT_JUSTIFIED (0 << CS43L22_DAC_IF_FORMAT_SHIFT) /* DACDIF[1:0] Left Justified, up to 24-bit data */
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#define CS43L22_DAC_IF_I2S (1 << CS43L22_DAC_IF_FORMAT_SHIFT) /* DACDIF[1:0] I2S, up to 24-bit data */
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#define CS43L22_DAC_IF_RIGHT_JUSTIFIED (2 << CS43L22_DAC_IF_FORMAT_SHIFT) /* DACDIF[1:0] Right Justified */
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#define CS43L22_DAC_IF_RESERVED (3 << CS43L22_DAC_IF_FORMAT_SHIFT) /* DACDIF[1:0] Reserved */
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2020-04-21 09:45:24 +02:00
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#define CS43L22_AUDIO_WORD_LENGHT_SHIFT (0) /* Bits 0-1: Configures the audio sample word length used for the data into SDIN */
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#define CS43L22_AWL_DSP_32_RJ_24 (0 << CS43L22_AUDIO_WORD_LENGHT_SHIFT) /* AWL[1:0] DSP Mode: 32-bit data, Right Justified: 24-bit data */
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#define CS43L22_AWL_DSP_24_RJ_20 (1 << CS43L22_AUDIO_WORD_LENGHT_SHIFT) /* AWL[1:0] DSP Mode: 24-bit data, Right Justified: 20-bit data */
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#define CS43L22_AWL_DSP_20_RJ_18 (2 << CS43L22_AUDIO_WORD_LENGHT_SHIFT) /* AWL[1:0] DSP Mode: 20-bit data, Right Justified: 18-bit data */
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#define CS43L22_AWL_DSP_16_RJ_16 (3 << CS43L22_AUDIO_WORD_LENGHT_SHIFT) /* AWL[1:0] DSP Mode: 16 bit data, Right Justified: 16-bit data */
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2017-05-21 22:14:09 +02:00
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/* 0x0E Miscellaneous Controls */
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#define CS43L22_FREEZE (1 << 3) /* Configures a hold on all register settings */
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#define CS43L22_DEEMPHASIS_ENABLE (1 << 2) /* Configures a 15μs/50μs digital de-emphasis filter response on the headphone/line and speaker outputs */
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/* 0x1F Tone Control */
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#define CS43L22_TREB_GAIN_SHIFT (4) /* Sets the gain of the treble shelving filter */
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#define CS43L22_TREB_GAIN(a) ((a) << CS43L22_TREB_GAIN_SHIFT)
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2020-04-21 09:45:24 +02:00
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/* TREB[3:0] Gain Setting: */
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2017-05-21 22:14:09 +02:00
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/* 0000 +12.0 dB */
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/* ··· ··· */
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/* 0111 +1.5 dB */
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/* 1000 0 dB */
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/* 1001 -1.5 dB */
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/* 1111 -10.5 dB */
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/* Step Size: 1.5 dB */
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#define CS43L22_BASS_GAIN_SHIFT (0) /* Sets the gain of the bass shelving filter */
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#define CS43L22_BASS_GAIN(a) ((a) << CS43L22_BASS_GAIN_SHIFT)
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2020-04-21 09:45:24 +02:00
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/* BASS[3:0] Gain Setting: */
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2017-05-21 22:14:09 +02:00
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/* 0000 +12.0 dB */
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/* ··· ··· */
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/* 0111 +1.5 dB */
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/* 1000 0 dB */
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/* 1001 -1.5 dB */
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/* 1111 -10.5 dB */
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/* Step Size: 1.5 dB */
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2020-04-21 09:45:24 +02:00
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/* FLL Configuration ********************************************************/
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2017-05-21 22:14:09 +02:00
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/* Default FLL configuration */
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#define CS43L22_DEFAULT_SAMPRATE 11025 /* Initial sample rate */
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#define CS43L22_DEFAULT_NCHANNELS 1 /* Initial number of channels */
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#define CS43L22_DEFAULT_BPSAMP 16 /* Initial bits per sample */
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#define CS43L22_NFLLRATIO 5 /* Number of FLL_RATIO values */
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#define CS43L22_MINOUTDIV 4 /* Minimum FLL_OUTDIV divider */
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#define CS43L22_MAXOUTDIV 64 /* Maximum FLL_OUTDIV divider */
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#define CS43L22_BCLK_MAXDIV 20 /* Maximum BCLK divider */
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#define CS43L22_FRAMELEN8 14 /* Bits per frame for 8-bit data */
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#define CS43L22_FRAMELEN16 32 /* Bits per frame for 16-bit data */
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/* Commonly defined and redefined macros */
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#ifndef MIN
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# define MIN(a,b) (((a) < (b)) ? (a) : (b))
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#endif
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#ifndef MAX
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# define MAX(a,b) (((a) > (b)) ? (a) : (b))
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#endif
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/****************************************************************************
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* Public Types
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****************************************************************************/
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struct cs43l22_dev_s
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{
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/* We are an audio lower half driver (We are also the upper "half" of
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* the CS43L22 driver with respect to the board lower half driver).
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*
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2020-04-21 09:45:24 +02:00
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* Terminology:
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* Our "lower" half audio instances will be called dev for the publicly
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* visible version and "priv" for the version that only this driver
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2017-05-21 22:14:09 +02:00
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* knows. From the point of view of this driver, it is the board lower
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* "half" that is referred to as "lower".
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*/
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struct audio_lowerhalf_s dev; /* CS43L22 audio lower half (this device) */
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/* Our specific driver data goes here */
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const FAR struct cs43l22_lower_s *lower; /* Pointer to the board lower functions */
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FAR struct i2c_master_s *i2c; /* I2C driver to use */
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FAR struct i2s_dev_s *i2s; /* I2S driver to use */
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struct dq_queue_s pendq; /* Queue of pending buffers to be sent */
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struct dq_queue_s doneq; /* Queue of sent buffers to be returned */
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2020-12-24 13:53:17 +01:00
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struct file mq; /* Message queue for receiving messages */
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2017-05-21 22:14:09 +02:00
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char mqname[16]; /* Our message queue name */
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pthread_t threadid; /* ID of our thread */
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uint32_t bitrate; /* Actual programmed bit rate */
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sem_t pendsem; /* Protect pendq */
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#ifdef CS43L22_USE_FFLOCK_INT
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struct work_s work; /* Interrupt work */
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#endif
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uint16_t samprate; /* Configured samprate (samples/sec) */
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#ifndef CONFIG_AUDIO_EXCLUDE_VOLUME
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#ifndef CONFIG_AUDIO_EXCLUDE_BALANCE
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uint16_t balance; /* Current balance level (b16) */
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2020-01-31 19:07:39 +01:00
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#endif /* CONFIG_AUDIO_EXCLUDE_BALANCE */
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2017-05-21 22:14:09 +02:00
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uint8_t volume; /* Current volume level {0..63} */
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2020-01-31 19:07:39 +01:00
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#endif /* CONFIG_AUDIO_EXCLUDE_VOLUME */
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2017-05-21 22:14:09 +02:00
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uint8_t nchannels; /* Number of channels (1 or 2) */
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uint8_t bpsamp; /* Bits per sample (8 or 16) */
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volatile uint8_t inflight; /* Number of audio buffers in-flight */
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#ifdef CS43L22_USE_FFLOCK_INT
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volatile bool locked; /* FLL is locked */
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#endif
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bool running; /* True: Worker thread is running */
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bool paused; /* True: Playing is paused */
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bool mute; /* True: Output is muted */
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#ifndef CONFIG_AUDIO_EXCLUDE_STOP
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bool terminating; /* True: Stop requested */
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#endif
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bool reserved; /* True: Device is reserved */
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volatile int result; /* The result of the last transfer */
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};
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifdef CONFIG_CS43L22_CLKDEBUG
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2020-04-21 09:45:24 +02:00
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extern const uint8_t g_sysclk_scaleb1[CS43L22_BCLK_MAXDIV + 1];
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2017-05-21 22:14:09 +02:00
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extern const uint8_t g_fllratio[CS43L22_NFLLRATIO];
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: cs43l22_readreg
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*
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2018-02-01 19:03:55 +01:00
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* Description:
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2017-05-21 22:14:09 +02:00
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* Read the specified 8-bit register from the CS43L22 device.
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*
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****************************************************************************/
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#if defined(CONFIG_CS43L22_REGDUMP) || defined(CONFIG_CS43L22_CLKDEBUG)
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struct cs43l22_dev_s;
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uint8_t cs43l22_readreg(FAR struct cs43l22_dev_s *priv, uint8_t regaddr);
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#endif
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#endif /* CONFIG_AUDIO */
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#endif /* __DRIVERS_AUDIO_CS43L22_H */
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