61 lines
1.1 KiB
INI
61 lines
1.1 KiB
INI
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#
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# Copyright 2022 NXP
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#
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# NXP S32K144 - 1x ARM Cortex-M4 @ up to 80 MHz
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#
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adapter_khz 1000
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transport select swd
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME s32k144
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}
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#
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# M4 JTAG mode TAP
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#
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if { [info exists M4_JTAG_TAPID] } {
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set _M4_JTAG_TAPID $M4_JTAG_TAPID
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} else {
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set _M4_JTAG_TAPID 0x4ba00477
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}
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#
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# M4 SWD mode TAP
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#
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if { [info exists M4_SWD_TAPID] } {
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set _M4_SWD_TAPID $M4_SWD_TAPID
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} else {
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set _M4_SWD_TAPID 0x2ba01477
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}
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source [find target/swj-dp.tcl]
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if { [using_jtag] } {
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set _M4_TAPID $_M4_JTAG_TAPID
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} else {
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set _M4_TAPID $_M4_SWD_TAPID
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}
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swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
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-expected-id $_M4_TAPID
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target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4
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# S32K144 has 32+28 KB contiguous SRAM
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0xF000
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}
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$_CHIPNAME.m4 configure -work-area-phys 0x1FFF8000 \
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-work-area-size $_WORKAREASIZE -work-area-backup 0
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$_CHIPNAME.m4 configure -rtos nuttx
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if { ![using_hla] } {
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cortex_m reset_config vectreset
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}
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