2014-06-06 20:37:36 +02:00
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README
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======
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This README file describes the port of NuttX to the SAMA4D4-EK
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development board. This board features the Atmel SAMA5D44 microprocessor.
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See http://www.atmel.com for further information.
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2014-06-29 15:40:37 +02:00
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This port was actually performed on a board designated SAMA5D4-MB. This
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board should be equivalent to the SAMA5D4-EK. However, care should be
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taken when I refer to PIO, Connector, or Jumper Usage in this document.
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Please consult the schematic for your actual board-in-hand to verify that
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information.
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SAMA5D44
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--------
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2014-06-07 17:37:17 +02:00
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---------------------------- -------------
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2014-06-06 20:37:36 +02:00
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PARAMETER SAMA5D44
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---------------------------- -------------
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CPU Cortex-A5
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ARM TrustZone Yes
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NEON Multimedia Architecture Yes
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Pin Count 361
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Data Cache 32KiB
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Instruction Cache 32KiB
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L2 Cache 128KiB
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Max. Operating Frequency 533MHz
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SRAM 128KiB
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Max I/O Pins 138
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USB Transceiver 3
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USB Speed Hi-Speed
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USB Interface Host, Device
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SPI 3
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TWI (I2C) 4
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UART 7
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LIN 4
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SSC 2
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Ethernet 2 10/100Mbps
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SD / eMMC 2
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Graphic LCD Yes
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Camera Interface Yes
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Video Decoder Yes
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Soft Modem Yes
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ADC channels 5
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Resistive Touch Screen Yes
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Capacitive Touch Module Yes
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Crypto Engine SHA/AES/TDES
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TRNG Yes
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External Bus Interface 1
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DRAM Memory DDR2/LPDDR,
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SDRAM/LPSDR,
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32-bit
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NAND Interface Yes
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FPU Yes
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MPU / MMU No/Yes
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Timers 9
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Output Compare channels 9
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Input Capture Channels 9
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PWM Channels 4
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32kHz RTC Yes
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Package BGA361
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2014-06-07 17:37:17 +02:00
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---------------------------- -------------
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2014-06-06 20:37:36 +02:00
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Contents
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========
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- Development Environment
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- GNU Toolchain Options
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- IDEs
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- NuttX EABI "buildroot" Toolchain
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- NXFLAT Toolchain
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- Loading Code into SRAM with J-Link
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- Writing to FLASH using SAM-BA
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2014-06-27 00:42:06 +02:00
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- Creating and Using DRAMBOOT
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2014-06-28 17:57:00 +02:00
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- Creating and Using AT25BOOT
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2014-06-06 20:37:36 +02:00
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- Running NuttX from SDRAM
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2014-06-07 17:37:17 +02:00
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- PIO Usage
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2014-06-06 20:37:36 +02:00
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- Buttons and LEDs
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- Serial Console
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- Networking
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- AT25 Serial FLASH
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- HSMCI Card Slots
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- USB Ports
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- USB High-Speed Device
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- USB High-Speed Host
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- SDRAM Support
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- NAND Support
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- I2C Tool
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- SAMA5 ADC Support
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- SAMA5 PWM Support
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- RTC
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- Watchdog Timer
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- TRNG and /dev/random
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- I2S Audio Support
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- SAMA4D4-EK Configuration Options
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- Configurations
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- To-Do List
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Development Environment
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=======================
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2014-06-11 22:45:01 +02:00
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Several possible development environments may be used:
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2014-06-06 20:37:36 +02:00
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- Linux or OSX native
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- Cygwin unders Windows
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- MinGW + MSYS under Windows
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- Windows native (with GNUMake from GNUWin32).
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All testing has been performed using Cygwin under Windows.
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The source has been built only using the GNU toolchain (see below). Other
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toolchains will likely cause problems.
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GNU Toolchain Options
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=====================
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The NuttX make system will support the several different toolchain options.
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All testing has been conducted using the CodeSourcery GCC toolchain. To use
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a different toolchain, you simply need to add change to one of the following
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configuration options to your .config (or defconfig) file:
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CONFIG_ARMV7A_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows
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CONFIG_ARMV7A_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux
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CONFIG_ARMV7A_TOOLCHAIN_ATOLLIC=y : Atollic toolchain for Windos
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CONFIG_ARMV7A_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows
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CONFIG_ARMV7A_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default)
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CONFIG_ARMV7A_TOOLCHAIN_GNU_EABIL=y : Generic GCC ARM EABI toolchain for Linux
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CONFIG_ARMV7A_TOOLCHAIN_GNU_EABIW=y : Generic GCC ARM EABI toolchain for Windows
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The CodeSourcery GCC toolchain is selected with
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CONFIG_ARMV7A_TOOLCHAIN_CODESOURCERYW=y and setting the PATH variable
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appropriately.
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NOTE about Windows native toolchains
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------------------------------------
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There are several limitations to using a Windows based toolchain in a
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Cygwin environment. The three biggest are:
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1. The Windows toolchain cannot follow Cygwin paths. Path conversions are
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performed automatically in the Cygwin makefiles using the 'cygpath'
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utility but you might easily find some new path problems. If so, check
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out 'cygpath -w'
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2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic
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links are used in Nuttx (e.g., include/arch). The make system works
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around these problems for the Windows tools by copying directories
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instead of linking them. But this can also cause some confusion for
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you: For example, you may edit a file in a "linked" directory and find
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that your changes had no effect. That is because you are building the
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copy of the file in the "fake" symbolic directory. If you use a\
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Windows toolchain, you should get in the habit of making like this:
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make clean_context all
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An alias in your .bashrc file might make that less painful.
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3. Dependencies are not made when using Windows versions of the GCC. This is
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because the dependencies are generated using Windows paths which do not
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work with the Cygwin make.
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MKDEP = $(TOPDIR)/tools/mknulldeps.sh
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IDEs
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====
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NuttX is built using command-line make. It can be used with an IDE, but some
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effort will be required to create the project.
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Makefile Build
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--------------
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Under Eclipse, it is pretty easy to set up an "empty makefile project" and
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simply use the NuttX makefile to build the system. That is almost for free
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under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty
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makefile project in order to work with Windows (Google for "Eclipse Cygwin" -
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there is a lot of help on the internet).
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Native Build
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------------
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Here are a few tips before you start that effort:
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1) Select the toolchain that you will be using in your .config file
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2) Start the NuttX build at least one time from the Cygwin command line
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before trying to create your project. This is necessary to create
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certain auto-generated files and directories that will be needed.
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3) Set up include pathes: You will need include/, arch/arm/src/sam34,
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arch/arm/src/common, arch/arm/src/armv7-m, and sched/.
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4) All assembly files need to have the definition option -D __ASSEMBLY__
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on the command line.
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Startup files will probably cause you some headaches. The NuttX startup file
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is arch/arm/src/sam34/sam_vectors.S. You may need to build NuttX
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one time from the Cygwin command line in order to obtain the pre-built
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startup object needed by an IDE.
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NuttX EABI "buildroot" Toolchain
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================================
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A GNU GCC-based toolchain is assumed. The files */setenv.sh should
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be modified to point to the correct path to the Cortex-M3 GCC toolchain (if
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different from the default in your PATH variable).
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If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX
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SourceForge download site (https://sourceforge.net/projects/nuttx/files/buildroot/).
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This GNU toolchain builds and executes in the Linux or Cygwin environment.
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1. You must have already configured Nuttx in <some-dir>/nuttx.
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cd tools
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./configure.sh sama5d4-ek/<sub-dir>
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2. Download the latest buildroot package into <some-dir>
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3. unpack the buildroot tarball. The resulting directory may
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have versioning information on it like buildroot-x.y.z. If so,
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rename <some-dir>/buildroot-x.y.z to <some-dir>/buildroot.
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4. cd <some-dir>/buildroot
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5. Copy the configuration file from the configs/ sub-directory to the
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top-level build directory:
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cp configs/cortexa8-eabi-defconfig-4.8.2 .config
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6a. You may wish to modify the configuration before you build it. For
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example, it is recommended that you build the kconfig-frontends tools,
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generomfs, and the NXFLAT tools as well. You may also want to change
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the selected toolchain. These reconfigurations can all be done with
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make menuconfig
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6b. If you chose to make the configuration with no changes, then you
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should still do the following to make certain that the build
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configuration is up-to-date:
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make oldconfig
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7. make
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8. Edit setenv.h, if necessary, so that the PATH variable includes
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the path to the newly built binaries.
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See the file configs/README.txt in the buildroot source tree. That has more
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details PLUS some special instructions that you will need to follow if you are
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building a Cortex-M3 toolchain for Cygwin under Windows.
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NXFLAT Toolchain
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================
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If you are *not* using the NuttX buildroot toolchain and you want to use
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the NXFLAT tools, then you will still have to build a portion of the buildroot
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tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can
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be downloaded from the NuttX SourceForge download site
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(https://sourceforge.net/projects/nuttx/files/).
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This GNU toolchain builds and executes in the Linux or Cygwin environment.
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1. You must have already configured Nuttx in <some-dir>/nuttx.
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cd tools
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./configure.sh sama5d4-ek/<sub-dir>
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2. Download the latest buildroot package into <some-dir>
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3. unpack the buildroot tarball. The resulting directory may
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have versioning information on it like buildroot-x.y.z. If so,
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rename <some-dir>/buildroot-x.y.z to <some-dir>/buildroot.
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4. cd <some-dir>/buildroot
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5. cp configs/cortexm3-defconfig-nxflat .config
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6. make oldconfig
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7. make
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8. Edit setenv.h, if necessary, so that the PATH variable includes
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the path to the newly built NXFLAT binaries.
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NOTE: There are some known incompatibilities with 4.6.3 EABI toolchain
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and the NXFLAT tools. See the top-level TODO file (under "Binary
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loaders") for more information about this problem. If you plan to use
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NXFLAT, please do not use the GCC 4.6.3 EABI toochain.
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Loading Code into SRAM with J-Link
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==================================
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Loading code with the Segger tools and GDB
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------------------------------------------
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1) Change directories into the directory where you built NuttX.
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2) Start the GDB server and wait until it is ready to accept GDB
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connections.
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3) Then run GDB like this:
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$ arm-none-eabi-gdb
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(gdb) target remote localhost:2331
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(gdb) mon reset
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(gdb) load nuttx
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(gdb) ... start debugging ...
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Loading code using J-Link Commander
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----------------------------------
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J-Link> r
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J-Link> loadbin <file> <address>
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J-Link> setpc <address of __start>
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J-Link> ... start debugging ...
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Writing to FLASH using SAM-BA
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=============================
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Assumed starting configuration:
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1. You have installed the J-Link CDC USB driver (Windows only, there is
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no need to install a driver on any regular Linux distribution),
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2. You have the USB connected to DBGU port (J23)
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3. Terminal configuration: 115200 8N1
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Using SAM-BA to write to FLASH:
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1. Exit the terminal emulation program and remove the USB cable from
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the DBGU port (J23)
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2. Connect the USB cable to the device USB port (J6)
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3. JP9 must open (BMS == 1) to boot from on-chip Boot ROM.
|
|
|
|
|
4. Press and maintain PB4 CS_BOOT button and power up the board. PB4
|
|
|
|
|
CS_BOOT button prevents booting from Nand or serial Flash by
|
|
|
|
|
disabling Flash Chip Selects after having powered the board, you can
|
|
|
|
|
release the PB4 BS_BOOT button.
|
|
|
|
|
5. On Windows you may need to wait for a device driver to be installed.
|
|
|
|
|
6. Start the SAM-BA application, selecting (1) the correct USB serial
|
|
|
|
|
port, and (2) board = at91sama5d4-ek.
|
|
|
|
|
7. The SAM-BA menu should appear.
|
|
|
|
|
8. Select the FLASH bank that you want to use and the address to write
|
|
|
|
|
to and "Execute"
|
|
|
|
|
9. When you are finished writing to FLASH, remove the USB cable from J6
|
|
|
|
|
and re-connect the serial link on USB CDC / DBGU connector (J23) and
|
|
|
|
|
re-open the terminal emulator program.
|
|
|
|
|
10. Power cycle the board.
|
|
|
|
|
|
2014-06-27 00:42:06 +02:00
|
|
|
Creating and Using DRAMBOOT
|
|
|
|
|
===========================
|
|
|
|
|
|
|
|
|
|
In order to have more control of debugging code that runs out of DARM,
|
|
|
|
|
I created the sama5d4-ek/dramboot configuration. That configuration is
|
|
|
|
|
described below under "Configurations."
|
|
|
|
|
|
|
|
|
|
Here are some general instructions on how to build an use dramboot:
|
|
|
|
|
|
|
|
|
|
Building:
|
|
|
|
|
1. Remove any old configurations (if applicable).
|
|
|
|
|
|
|
|
|
|
cd <nuttx>
|
|
|
|
|
make distclean
|
|
|
|
|
|
|
|
|
|
2. Install and build the dramboot configuration. This steps will establish
|
|
|
|
|
the dramboot configuration and setup the PATH variable in order to do
|
|
|
|
|
the build:
|
|
|
|
|
|
|
|
|
|
cd tools
|
|
|
|
|
./configure.sh sama5d4-ek/dramboot
|
|
|
|
|
cd -
|
|
|
|
|
. ./setenv.sh
|
|
|
|
|
|
|
|
|
|
Before sourcing the setenv.sh file above, you should examine it and
|
|
|
|
|
perform edits as necessary so that TOOLCHAIN_BIN is the correct path
|
|
|
|
|
to the directory than holds your toolchain binaries.
|
|
|
|
|
|
|
|
|
|
NOTE: Be aware that the default dramboot also disables the watchdog.
|
|
|
|
|
Since you will not be able to re-enable the watchdog later, you may
|
|
|
|
|
need to set CONFIG_SAMA5_WDT=y in the NuttX configuration file.
|
|
|
|
|
|
|
|
|
|
Then make dramboot:
|
|
|
|
|
|
|
|
|
|
make
|
|
|
|
|
|
|
|
|
|
This will result in an ELF binary called 'nuttx' and also HEX and
|
|
|
|
|
binary versions called 'nuttx.hex' and 'nuttx.bin'.
|
|
|
|
|
|
|
|
|
|
3. Rename the binaries. Since you will need two versions of NuttX: this
|
|
|
|
|
dramboot version that runs in internal SRAM and another under test in
|
|
|
|
|
NOR FLASH, I rename the resulting binary files so that they can be
|
|
|
|
|
distinguished:
|
|
|
|
|
|
|
|
|
|
mv nuttx dramboot
|
|
|
|
|
mv nuttx.hex dramboot.hex
|
|
|
|
|
mv nuttx.bin dramboot.bin
|
|
|
|
|
|
|
|
|
|
4. Build the "real" DRAM configuration. This will create the nuttx.hex
|
2014-06-27 01:04:53 +02:00
|
|
|
that you will load using dramboot. Note that you must select
|
|
|
|
|
CONFIG_SAMA5D4EK_DRAM_BOOT=y. This controls the origin at which the
|
|
|
|
|
code is linked and positions it correctly for the DRAMBOOT program.
|
2014-06-27 00:42:06 +02:00
|
|
|
|
2014-06-27 01:04:53 +02:00
|
|
|
5. Restart the system holding DIS_BOOT. You should see the RomBOOT
|
2014-06-27 00:42:06 +02:00
|
|
|
prompt on the 115200 8N1 serial console (and nothing) more. Hit
|
|
|
|
|
the ENTER key with the focus on your terminal window a few time.
|
|
|
|
|
This will enable JTAG.
|
|
|
|
|
|
|
|
|
|
6. Then start the J-Link GDB server and GDB. In GDB, I do the following:
|
|
|
|
|
|
|
|
|
|
(gdb) mon heal # Halt the CPU
|
|
|
|
|
(gdb) load dramboot # Load dramboot into internal SRAM
|
|
|
|
|
(gdb) mon go # Start dramboot
|
|
|
|
|
|
|
|
|
|
You should see this message:
|
|
|
|
|
|
|
|
|
|
Send Intel HEX file now
|
|
|
|
|
|
|
|
|
|
Load your program by sending the nuttx.hex via the terminal program.
|
|
|
|
|
Then:
|
|
|
|
|
|
|
|
|
|
(gdb) mon halt # Break in
|
|
|
|
|
(gdb) mon reg pc = 0x20000040 # Set the PC to DRAM entry point
|
|
|
|
|
(gdb) mon go # And jump into DRAM
|
|
|
|
|
|
|
|
|
|
The dramboot program can also be configured to jump directly into
|
|
|
|
|
DRAM without requiring the final halt and go by setting
|
|
|
|
|
CONFIG_SAMA5D4EK_DRAM_START=y in the NuttX configuration. However,
|
|
|
|
|
since I have been debugging the early boot sequence, the above
|
|
|
|
|
sequence has been most convenient for me since it allows me to
|
|
|
|
|
step into the program in SDRAM.
|
|
|
|
|
|
|
|
|
|
7. An option is to use the SAM-BA tool to write the DRAMBOOT image into
|
|
|
|
|
Serial FLASH. Then, the system will boot from Serial FLASH by
|
|
|
|
|
copying the DRAMBOOT image in SRAM which will run, download the nuttx.hex
|
|
|
|
|
file, and then start the image loaded into DRAM automatically. This is
|
|
|
|
|
a very convenient usage!
|
|
|
|
|
|
|
|
|
|
NOTES: (1) There is that must be closed to enable use of the AT25
|
|
|
|
|
Serial Flash. (2) If using SAM-BA, make sure that you load the DRAM
|
2014-06-28 17:57:00 +02:00
|
|
|
boot program into the boot area via the pull-down menu. (3) If
|
|
|
|
|
you don't have SAM-BA, an alternative is to use the AT25BOOT program
|
|
|
|
|
described in the next section.
|
|
|
|
|
|
2014-06-28 20:38:41 +02:00
|
|
|
STATUS: I don't have a working SAM-BA at the moment and there are issues
|
|
|
|
|
with my AT25BOOT (see below). I currently work around these issues by
|
|
|
|
|
putting DRAMBOOT on a microSD card (as boot.bin). The RomBOOT loader does
|
|
|
|
|
boot that image without issue.
|
|
|
|
|
|
2014-06-28 17:57:00 +02:00
|
|
|
Creating and Using AT25BOOT
|
|
|
|
|
===========================
|
|
|
|
|
|
|
|
|
|
To work around some SAM-BA availability issues that I had at one time,
|
|
|
|
|
I created the AT25BOOT program. AT25BOOT is a tiny program that runs in
|
|
|
|
|
ISRAM. AT25BOOT will enable SDRAM and configure the AT25 Serial FLASH.
|
|
|
|
|
It will prompt and then load an Intel HEX program into SDRAM over the
|
|
|
|
|
serial console. If the program is successfully loaded in SDRAM, AT25BOOT
|
|
|
|
|
will copy the program at the beginning of the AT26 Serial FLASH.
|
|
|
|
|
If the jumpering is set correctly, the SAMA5D4 RomBOOT loader will
|
|
|
|
|
then boot the program from the serial FLASH the next time that it
|
|
|
|
|
reset.
|
|
|
|
|
|
|
|
|
|
The AT25BOOT configuration is described below under "Configurations."
|
|
|
|
|
|
|
|
|
|
Here are some general instructions on how to build an use AT25BOOT:
|
|
|
|
|
|
|
|
|
|
Building:
|
|
|
|
|
1. Remove any old configurations (if applicable).
|
|
|
|
|
|
|
|
|
|
cd <nuttx>
|
|
|
|
|
make distclean
|
|
|
|
|
|
|
|
|
|
2. Install and build the AT25BOOT configuration. This steps will establish
|
|
|
|
|
the AT25BOOT configuration and setup the PATH variable in order to do
|
|
|
|
|
the build:
|
|
|
|
|
|
|
|
|
|
cd tools
|
|
|
|
|
./configure.sh sama5d4-ek/at25boot
|
|
|
|
|
cd -
|
|
|
|
|
. ./setenv.sh
|
|
|
|
|
|
|
|
|
|
Before sourcing the setenv.sh file above, you should examine it and
|
|
|
|
|
perform edits as necessary so that TOOLCHAIN_BIN is the correct path
|
|
|
|
|
to the directory than holds your toolchain binaries.
|
|
|
|
|
|
|
|
|
|
Then make AT25BOOT:
|
|
|
|
|
|
|
|
|
|
make
|
|
|
|
|
|
|
|
|
|
This will result in an ELF binary called 'nuttx' and also HEX and
|
|
|
|
|
binary versions called 'nuttx.hex' and 'nuttx.bin'.
|
|
|
|
|
|
|
|
|
|
3. Rename the binaries. If you want to save this version of AT25BOOT so
|
|
|
|
|
that it does not get clobbered later, you may want to rename the
|
|
|
|
|
binaries:
|
|
|
|
|
|
|
|
|
|
mv nuttx at25boot
|
|
|
|
|
mv nuttx.hex at25boot.hex
|
|
|
|
|
mv nuttx.bin at25boot.bin
|
|
|
|
|
|
|
|
|
|
4. Build the "real" DRAMBOOT configuration. This will create the
|
|
|
|
|
dramboot.hex that you will write to the AT25 FLASH using AT25BOOT. See
|
|
|
|
|
the section above entitled "Creating and Using AT25BOOT" for more
|
|
|
|
|
information.
|
|
|
|
|
|
|
|
|
|
5. Restart the system holding DIS_BOOT. You should see the RomBOOT
|
|
|
|
|
prompt on the 115200 8N1 serial console (and nothing) more. Hit
|
|
|
|
|
the ENTER key with the focus on your terminal window a few time.
|
|
|
|
|
This will enable JTAG.
|
|
|
|
|
|
|
|
|
|
6. Then start the J-Link GDB server and GDB. In GDB, I do the following:
|
|
|
|
|
|
|
|
|
|
(gdb) mon heal # Halt the CPU
|
|
|
|
|
(gdb) load at25boot # Load AT25BOOT into internal SRAM
|
|
|
|
|
(gdb) mon go # Start AT25BOOT
|
|
|
|
|
|
|
|
|
|
You should see this message:
|
|
|
|
|
|
|
|
|
|
Send Intel HEX file now
|
|
|
|
|
|
|
|
|
|
Load DRAMBOOT by sending the dramboot.hex via the terminal program.
|
|
|
|
|
At this point you will get messages indicated whether or not the write
|
|
|
|
|
to the AT25 FLASH was successful or not. When you reset the board,
|
|
|
|
|
it should then boot from the AT25 Serial FLASH and you should again
|
|
|
|
|
get the prompt:
|
|
|
|
|
|
|
|
|
|
Send Intel HEX file now
|
|
|
|
|
|
|
|
|
|
But now you are being prompted to load the DRAM program under test
|
|
|
|
|
(See the section above entitled "Creating and Using AT25BOOT").
|
|
|
|
|
|
|
|
|
|
7. An better option, if available, is to use the SAM-BA tool to write the
|
|
|
|
|
DRAMBOOT image into Serial FLASH.
|
|
|
|
|
|
|
|
|
|
NOTES: (1) There is that must be closed to enable use of the AT25
|
|
|
|
|
Serial Flash. (2) If using SAM-BA, make sure that you load the DRAM
|
|
|
|
|
boot program into the boot area via the pull-down menu.
|
2014-06-27 00:42:06 +02:00
|
|
|
|
2014-06-28 20:38:41 +02:00
|
|
|
STATUS: While this program works great and appears to correctly write
|
|
|
|
|
the binary image onto the AT25 Serial FLASH, the RomBOOT loader will
|
|
|
|
|
not boot it! I believe that is because the secure boot loader has some
|
|
|
|
|
undocumented requirements that I am unaware of. (2014-6-28)
|
|
|
|
|
|
2014-06-06 20:37:36 +02:00
|
|
|
Running NuttX from SDRAM
|
|
|
|
|
========================
|
|
|
|
|
|
|
|
|
|
NuttX may be executed from SDRAM. But this case means that the NuttX
|
|
|
|
|
binary must reside on some other media (typically NAND FLASH, Serial
|
2014-06-27 00:42:06 +02:00
|
|
|
FLASH) or transferred over some interface (perhaps a UARt or even a
|
|
|
|
|
TFTP server). In these cases, an intermediate bootloader such as U-Boot
|
|
|
|
|
or Barebox must be used to configure the SAMA5D4 clocks and SDRAM and
|
|
|
|
|
then to copy the NuttX binary into SDRAM.
|
|
|
|
|
|
|
|
|
|
The SRAMBOOT program is another option (see above). But this section
|
|
|
|
|
will focus on U-Boot.
|
2014-06-06 20:37:36 +02:00
|
|
|
|
|
|
|
|
- NuttX Configuration
|
|
|
|
|
- Boot sequence
|
|
|
|
|
- NAND FLASH Memory Map
|
|
|
|
|
- Programming the AT91Boostrap Binary
|
|
|
|
|
- Programming U-Boot
|
|
|
|
|
- Load NuttX with U-Boot on AT91 boards
|
|
|
|
|
|
|
|
|
|
TODO: Some drivers may require some adjustments to run from SDRAM. That
|
|
|
|
|
is because in this case macros like BOARD_MCK_FREQUENCY are not constants
|
|
|
|
|
but are instead function calls: The MCK clock frequency is not known in
|
|
|
|
|
advance but instead has to be calculated from the bootloader PLL configuration.
|
|
|
|
|
See the TODO list at the end of this file for further information.
|
|
|
|
|
|
|
|
|
|
NuttX Configuration
|
|
|
|
|
-------------------
|
|
|
|
|
|
|
|
|
|
In order to run from SDRAM, NuttX must be built at origin 0x20008000 in
|
|
|
|
|
SDRAM (skipping over SDRAM memory used by the bootloader). The following
|
|
|
|
|
configuration option is required:
|
|
|
|
|
|
|
|
|
|
CONFIG_SAMA5_BOOT_SDRAM=y
|
|
|
|
|
CONFIG_BOOT_RUNFROMSDRAM=y
|
|
|
|
|
|
|
|
|
|
These options tell the NuttX code that it will be booting and running from
|
|
|
|
|
SDRAM. In this case, the start-logic will do to things: (1) it will not
|
|
|
|
|
configure the SAMA5D4 clocking. Rather, it will use the clock configuration
|
|
|
|
|
as set up by the bootloader. And (2) it will not attempt to configure the
|
|
|
|
|
SDRAM. Since NuttX is already running from SDRAM, it must accept the SDRAM
|
|
|
|
|
configuration as set up by the bootloader.
|
|
|
|
|
|
|
|
|
|
Boot sequence
|
|
|
|
|
-------------
|
|
|
|
|
|
|
|
|
|
Reference: http://www.at91.com/linux4sam/bin/view/Linux4SAM/GettingStarted
|
|
|
|
|
|
|
|
|
|
Several pieces of software are involved to boot a Nutt5X into SDRAM. First
|
|
|
|
|
is the primary bootloader in ROM which is in charge to check if a valid
|
|
|
|
|
application is present on supported media (NOR FLASH, Serial DataFlash,
|
|
|
|
|
NAND FLASH, SD card).
|
|
|
|
|
|
|
|
|
|
The boot sequence of linux4SAM is done in several steps :
|
|
|
|
|
|
|
|
|
|
1. The ROM bootloader checks if a valid application is present in FLASH
|
|
|
|
|
and if it is the case downloads it into internal SRAM. This program
|
|
|
|
|
is usually a second level bootloader called AT91BootStrap.
|
|
|
|
|
|
|
|
|
|
2. AT91Bootstrap is the second level bootloader. It is in charge of the
|
|
|
|
|
hardware configuration. It downloads U-Boot / Barebox binary from
|
|
|
|
|
FLASH to SDRAM / DDRAM and starts the third level bootloader
|
|
|
|
|
(U-Boot / Barebox)
|
|
|
|
|
|
|
|
|
|
(see http://www.at91.com/linux4sam/bin/view/Linux4SAM/AT91Bootstrap).
|
|
|
|
|
|
|
|
|
|
3. The third level bootloader is either U-Boot or Barebox. The third
|
|
|
|
|
level bootloader is in charge of downloading NuttX binary from FLASH,
|
|
|
|
|
network, SD card, etc. It then starts NuttX.
|
|
|
|
|
|
|
|
|
|
4. Then NuttX runs from SDRAM
|
|
|
|
|
|
|
|
|
|
NAND FLASH Memory Map
|
|
|
|
|
---------------------
|
|
|
|
|
|
|
|
|
|
Reference: http://www.at91.com/linux4sam/bin/view/Linux4SAM/GettingStarted
|
|
|
|
|
|
|
|
|
|
0x0000:0000 - 0x0003:ffff: AT91BootStrap
|
|
|
|
|
0x0004:0000 - 0x000b:ffff: U-Boot
|
|
|
|
|
0x000c:0000 - 0x000f:ffff: U-Boot environment
|
|
|
|
|
0x0010:0000 - 0x0017:ffff: U-Boot environement redundant
|
|
|
|
|
0x0018:0000 - 0x001f:ffff: Device tree (DTB)
|
|
|
|
|
0x0020:0000 - 0x007f:ffff: NuttX
|
|
|
|
|
0x0080:0000 - end: Available for use as a NAND file system
|
|
|
|
|
|
|
|
|
|
Programming the AT91Boostrap Binary
|
|
|
|
|
-----------------------------------
|
|
|
|
|
|
|
|
|
|
Reference: http://www.at91.com/linux4sam/bin/view/Linux4SAM/AT91Bootstrap
|
|
|
|
|
|
|
|
|
|
This section describes how to program AT91Bootstrap binary into the boot
|
|
|
|
|
media with SAM-BA tool using NandFlash as boot media.
|
|
|
|
|
|
|
|
|
|
1. Get AT91BootStrap binaries. Build instructions are available here:
|
|
|
|
|
|
|
|
|
|
http://www.at91.com/linux4sam/bin/view/Linux4SAM/AT91Bootstrap#Build_AT91Bootstrap_from_sources
|
|
|
|
|
|
|
|
|
|
A pre-built AT91BootStrap binary is available here:
|
|
|
|
|
|
|
|
|
|
ftp://www.at91.com/pub/at91bootstrap/AT91Bootstrap3.6.1/sama5d3_xplained-nandflashboot-uboot-3.6.1.bin
|
|
|
|
|
|
|
|
|
|
2. Start the SAM-BA GUI Application:
|
|
|
|
|
|
|
|
|
|
- Connect the USB Device interface to your host machine using the USB
|
|
|
|
|
Device Cable.
|
|
|
|
|
- Make sure that the chip can execute the SAM-BA Monitor.
|
|
|
|
|
- Start SAM-BA GUI application.
|
|
|
|
|
- Select the board in the drop-down menu and choose the USB connection.
|
|
|
|
|
|
|
|
|
|
3. In the SAM-BA GUI Application:
|
|
|
|
|
|
|
|
|
|
- Choose the "NandFlash" tab in the SAM-BA GUI interface.
|
|
|
|
|
- Initialize the NandFlash by choosing the "Enable NandFlash" action in
|
|
|
|
|
the Scripts rolling menu, then press "Execute" button.
|
|
|
|
|
- Erase the NandFlash device by choosing the "Erase All" action, then
|
|
|
|
|
press "Execute" button.
|
|
|
|
|
- Enable the PMECC by choosing the "Enable OS PMECC parameters" action,
|
|
|
|
|
then press "Execute" button.
|
|
|
|
|
|
|
|
|
|
PMECC
|
|
|
|
|
Number of sectors per page: 4
|
|
|
|
|
Spare Size: 64
|
|
|
|
|
Number of ECC bits required: 4
|
|
|
|
|
Size of the ECC sector: 512
|
|
|
|
|
ECC offset: 36
|
|
|
|
|
|
|
|
|
|
- Choose "Send Boot File" action, then press Execute button to select the
|
|
|
|
|
at91bootstrap binary file and to program the binary to the NandFlash.
|
|
|
|
|
- Close SAM-BA, remove the USB Device cable.
|
|
|
|
|
|
|
|
|
|
Programming U-Boot
|
|
|
|
|
-------------------
|
|
|
|
|
|
|
|
|
|
Reference http://www.at91.com/linux4sam/bin/view/Linux4SAM/U-Boot
|
|
|
|
|
|
|
|
|
|
1. Get U-Boot Binaries. Build instructions are available here:
|
|
|
|
|
|
|
|
|
|
http://www.at91.com/linux4sam/bin/view/Linux4SAM/U-Boot#Build_U_Boot_from_sources
|
|
|
|
|
|
|
|
|
|
A pre-Built binay image is available here:
|
|
|
|
|
|
|
|
|
|
ftp://www.at91.com/pub/uboot/u-boot-v2013.07/u-boot-sama5d3_xplained-v2013.07-at91-r1.bin
|
|
|
|
|
|
|
|
|
|
2. Start the SAM-BA GUI Application:
|
|
|
|
|
|
|
|
|
|
- Connect the USB Device interface to your host machine using the USB
|
|
|
|
|
Device Cable.
|
|
|
|
|
- Make sure that the chip can execute the SAM-BA Monitor.
|
|
|
|
|
- Start SAM-BA GUI application.
|
|
|
|
|
- Select the board in the drop-down menu and choose the USB connection.
|
|
|
|
|
|
|
|
|
|
3. In the SAM-BA GUI Application:
|
|
|
|
|
|
|
|
|
|
- Choose the NandFlash tab in the SAM-BA GUI interface.
|
|
|
|
|
- Initialize the NandFlash by choosing the "Enable NandFlash" action in
|
|
|
|
|
the Scripts rolling menu, then press Execute button.
|
|
|
|
|
- Enable the PMECC by choosing the "Enable OS PMECC parameters" action,
|
|
|
|
|
then press Execute button.
|
|
|
|
|
|
|
|
|
|
PMECC
|
|
|
|
|
Number of sectors per page: 4
|
|
|
|
|
Spare Size: 64
|
|
|
|
|
Number of ECC bits required: 4
|
|
|
|
|
Size of the ECC sector: 512
|
|
|
|
|
ECC offset: 36
|
|
|
|
|
|
|
|
|
|
- Press the "Send File Name" Browse button
|
|
|
|
|
- Choose u-boot.bin binary file and press Open
|
|
|
|
|
- Enter the proper address on media in the Address text field:
|
|
|
|
|
0x00040000
|
|
|
|
|
- Press the "Send File" button
|
|
|
|
|
- Close SAM-BA, remove the USB Device cable.
|
|
|
|
|
|
|
|
|
|
You should now be able to interrupt with U-Boot vie the DBGU interface.
|
|
|
|
|
|
|
|
|
|
Load NuttX with U-Boot on AT91 boards
|
|
|
|
|
-------------------------------------
|
|
|
|
|
|
|
|
|
|
Reference http://www.at91.com/linux4sam/bin/view/Linux4SAM/U-Boot
|
|
|
|
|
|
|
|
|
|
Preparing NuttX image
|
|
|
|
|
|
|
|
|
|
U-Boot does not support normal binary images. Instead you have to
|
|
|
|
|
create an uImage file with the mkimage tool which encapsulates kernel
|
|
|
|
|
image with header information, CRC32 checksum, etc.
|
|
|
|
|
|
|
|
|
|
mkimage comes in source code with U-Boot distribution and it is built
|
|
|
|
|
during U-Boot compilation (u-boot-source-dir/tools/mkimage). There
|
|
|
|
|
are also sites where you can download pre-built mkimage binaries. For
|
|
|
|
|
example: http://www.trimslice.com/wiki/index.php/U-Boot_images
|
|
|
|
|
|
|
|
|
|
See the U-Boot README file for more information. More information is
|
|
|
|
|
also available in the mkimage man page (for example,
|
|
|
|
|
http://linux.die.net/man/1/mkimage).
|
|
|
|
|
|
|
|
|
|
Command to generate an uncompressed uImage file (4) :
|
|
|
|
|
|
|
|
|
|
mkimage -A arm -O linux -C none -T kernel -a 20008000 -e 20008000 \
|
|
|
|
|
-n nuttx -d nuttx.bin uImage
|
|
|
|
|
|
|
|
|
|
Where:
|
|
|
|
|
|
|
|
|
|
-A arm: Set architecture to ARM
|
|
|
|
|
-O linux: Select operating system. bootm command of u-boot changes
|
|
|
|
|
boot method by os type.
|
|
|
|
|
-T kernel: Set image type.
|
|
|
|
|
-C none: Set compression type.
|
|
|
|
|
-a 20008000: Set load address.
|
|
|
|
|
-e 20008000: Set entry point.
|
|
|
|
|
-n nuttx: Set image name.
|
|
|
|
|
-d nuttx.bin: Use image data from nuttx.bin.
|
|
|
|
|
|
|
|
|
|
This will generate a binary called uImage. If you have the path to
|
|
|
|
|
mkimage in your PATH variable, then you can automatically build the
|
|
|
|
|
uImage file by adding the following to your .config file:
|
|
|
|
|
|
|
|
|
|
CONFIG_RAW_BINARY=y
|
|
|
|
|
CONFIG_UBOOT_UIMAGE=y
|
|
|
|
|
CONFIG_UIMAGE_LOAD_ADDRESS=0x20008000
|
|
|
|
|
CONFIG_UIMAGE_ENTRY_POINT=0x20008040
|
|
|
|
|
|
|
|
|
|
The uImage file can them be loaded into memory from a variety of sources
|
|
|
|
|
(serial, SD card, JFFS2 on NAND, TFTP).
|
|
|
|
|
|
|
|
|
|
STATUS:
|
|
|
|
|
2014-4-1: So far, I am unable to get U-Boot to execute the uImage
|
|
|
|
|
file. I get the following error messages (in this case
|
|
|
|
|
trying to load from an SD card):
|
|
|
|
|
|
|
|
|
|
U-Boot> fatload mmc 0 0x22000000 uimage
|
|
|
|
|
reading uimage
|
|
|
|
|
97744 bytes read in 21 ms (4.4 MiB/s)
|
|
|
|
|
|
|
|
|
|
U-Boot> bootm 0x22000000
|
|
|
|
|
## Booting kernel from Legacy Image at 0x22000000 ...
|
|
|
|
|
Image Name: nuttx
|
|
|
|
|
Image Type: ARM Linux Kernel Image (uncompressed)
|
|
|
|
|
Data Size: 97680 Bytes = 95.4 KiB
|
|
|
|
|
Load Address: 20008000
|
|
|
|
|
Entry Point: 20008040
|
|
|
|
|
Verifying Checksum ... OK
|
|
|
|
|
XIP Kernel Image ... OK
|
|
|
|
|
FDT and ATAGS support not compiled in - hanging
|
|
|
|
|
### ERROR ### Please RESET the board ###
|
|
|
|
|
|
|
|
|
|
This, however, appears to be a usable workaround:
|
|
|
|
|
|
|
|
|
|
U-Boot> fatload mmc 0 0x20008000 nuttx.bin
|
|
|
|
|
mci: setting clock 257812 Hz, block size 512
|
|
|
|
|
mci: setting clock 257812 Hz, block size 512
|
|
|
|
|
mci: setting clock 257812 Hz, block size 512
|
|
|
|
|
gen_atmel_mci: CMDR 00001048 ( 8) ARGR 000001aa (SR: 0c100025) Command Time Out
|
|
|
|
|
mci: setting clock 257812 Hz, block size 512
|
|
|
|
|
mci: setting clock 22000000 Hz, block size 512
|
|
|
|
|
reading nuttx.bin
|
|
|
|
|
108076 bytes read in 23 ms (4.5 MiB/s)
|
|
|
|
|
|
|
|
|
|
U-Boot> go 0x20008040
|
|
|
|
|
## Starting application at 0x20008040 ...
|
|
|
|
|
|
|
|
|
|
NuttShell (NSH) NuttX-7.2
|
|
|
|
|
nsh>
|
|
|
|
|
|
|
|
|
|
Loading through network
|
|
|
|
|
|
|
|
|
|
On a development system, it is useful to get the kernel and root file
|
|
|
|
|
system through the network. U-Boot provides support for loading
|
|
|
|
|
binaries from a remote host on the network using the TFTP protocol.
|
|
|
|
|
|
|
|
|
|
To manage to use TFTP with U-Boot, you will have to configure a TFTP
|
|
|
|
|
server on your host machine. Check your distribution manual or Internet
|
|
|
|
|
resources to configure a Linux or Windows TFTP server on your host:
|
|
|
|
|
|
|
|
|
|
- U-Boot documentation on a Linux host:
|
|
|
|
|
http://www.denx.de/wiki/view/DULG/SystemSetup#Section_4.6.
|
|
|
|
|
|
|
|
|
|
- Another TFTP configuration reference:
|
|
|
|
|
http://www.linuxhomenetworking.com/wiki/index.php/Quick_HOWTO_:_Ch16_:_Telnet%2C_TFTP%2C_and_xinetd#TFTP
|
|
|
|
|
|
|
|
|
|
On the U-Boot side, you will have to setup the networking parameters:
|
|
|
|
|
|
|
|
|
|
1. Setup an Ethernet address (MAC address)
|
|
|
|
|
Check this U-Boot network BuildRootFAQ entry to choose a proper MAC
|
|
|
|
|
address: http://www.denx.de/wiki/DULG/EthernetDoesNotWork
|
|
|
|
|
|
|
|
|
|
setenv ethaddr 00:e0:de:ad:be:ef
|
|
|
|
|
|
|
|
|
|
2. Setup IP parameters:
|
|
|
|
|
The board ip address
|
|
|
|
|
|
|
|
|
|
setenv ipaddr 10.0.0.2
|
|
|
|
|
|
|
|
|
|
The server ip address where the TFTP server is running
|
|
|
|
|
|
|
|
|
|
setenv serverip 10.0.0.1
|
|
|
|
|
|
|
|
|
|
3. saving Environment to flash
|
|
|
|
|
|
|
|
|
|
saveenv
|
|
|
|
|
|
|
|
|
|
4. If Ethernet Phy has not been detected during former bootup, reset
|
|
|
|
|
the board to reload U-Boot : the Ethernet address and Phy
|
|
|
|
|
initialization shall be ok, now
|
|
|
|
|
|
|
|
|
|
5. Download the NuttX uImage and the root file system to a ram location
|
|
|
|
|
using the U-Boot tftp command (Cf. U-Boot script capability chapter).
|
|
|
|
|
|
|
|
|
|
6. Launch NuttX issuing a bootm or boot command.
|
|
|
|
|
|
|
|
|
|
If the board has both emac and gmac, you can use following to choose
|
|
|
|
|
which one to use:
|
|
|
|
|
|
|
|
|
|
setenv ethact macb0,gmacb0
|
|
|
|
|
setenv ethprime gmacb0
|
|
|
|
|
|
|
|
|
|
STATUS:
|
|
|
|
|
2014-3-30: These instructions were adapted from the Linux4SAM website
|
|
|
|
|
but have not yet been used.
|
2014-06-07 17:37:17 +02:00
|
|
|
PIO Usage
|
|
|
|
|
=========
|
|
|
|
|
|
|
|
|
|
Rev. B. 0111A
|
|
|
|
|
------------------------------ ------------------- -------------------------
|
|
|
|
|
SAMA5D4 PIO SIGNAL USAGE
|
|
|
|
|
------------------------------ ------------------- -------------------------
|
|
|
|
|
PA0/LCDDAT0/TMS PA0 LCDDAT0, TMS
|
|
|
|
|
PA1/LCDDAT1 PA1 LCDDAT1
|
|
|
|
|
PA2/LCDDAT2/G1_TXCK PA LCDDAT2, G1_TXCK
|
|
|
|
|
PA3/LCDDAT3/G1_RXCK PA3 LCDDAT3
|
|
|
|
|
PA4/LCDDAT4/G1_TXEN PA4 LCDDAT4, G1_TXEN
|
|
|
|
|
PA5/LCDDAT5/G1_TXER PA5 LCDDAT5
|
|
|
|
|
PA6/LCDDAT6/G1_CRS PA6 LCDDAT6
|
|
|
|
|
PA7/LCDDAT7 PA7 LCDDAT7
|
|
|
|
|
PA8/LCDDAT8/TCK PA8 LCDDAT8, TCK
|
|
|
|
|
PA9/LCDDAT9/G1_COL PA9 LCDDAT9
|
|
|
|
|
PA10/LCDDAT10/G1_RXDV PA10 LCDDAT10, G1_RXDV
|
|
|
|
|
PA11/LCDDAT11/G1_RXER PA11 LCDDAT11, G1_RXER
|
|
|
|
|
PA12/LCDDAT12/G1_RX0 PA12 LCDDAT12, G1_RX0
|
|
|
|
|
PA13/LCDDAT13/G1_RX1 PA13 LCDDAT13, G1_RX1
|
|
|
|
|
PA14/LCDDAT14/G1_TX0 PA14 LCDDAT14, G1_TX0
|
|
|
|
|
PA15/LCDDAT15/G1_TX1 PA15 LCDDAT15, G1_TX1
|
|
|
|
|
PA16/LCDDAT16/NTRST PA16 LCDDAT16, NTRST
|
|
|
|
|
PA17/LCDDAT17 PA17 LCDDAT17
|
|
|
|
|
PA18/LCDDAT18/G1_RX2 PA18 LCDDAT18
|
|
|
|
|
PA19/LCDDAT19/G1_RX3 PA19 LCDDAT19
|
|
|
|
|
PA20/LCDDAT20/G1_TX2 PA20 LCDDAT20
|
|
|
|
|
PA21/LCDDAT21/G1_TX3 PA21 LCDDAT21
|
|
|
|
|
PA22/LCDDAT22/G1_MDC PA22 LCDDAT22, G1_MDC
|
|
|
|
|
PA23/LCDDAT23/G1_MDIO PA23 LCDDAT23, G1_MDIO
|
|
|
|
|
PA24/LCDPWM/PCK0 PA24 LCDPWM, EXP
|
|
|
|
|
PA25/LCDDISP/TD0 PA25 LCDDISP, EXP
|
|
|
|
|
PA26/LCDVSYNC/PWMH0/SPI1_NPCS1 PA26 LCDVSYNC
|
|
|
|
|
PA27/LCDHSYNC/PWML0/SPI1_NPCS2 PA27 LCDHSYNC
|
|
|
|
|
PA28/LCDPCK/PWMH1/SPI1_NPCS3 PA28 LCDPCK
|
|
|
|
|
PA29/LCDDEN/PWML1 PA29 LCDDEN
|
|
|
|
|
PA30/TWD0 PA30 TWD0
|
|
|
|
|
PA31/TWCK0 PA31 TWCK0
|
|
|
|
|
------------------------------ ------------------- -------------------------
|
|
|
|
|
PB0/G0_TXCK PB0 G0_TXCK, EXP
|
|
|
|
|
PB1/G0_RXCK/SCK2/ISI_PCK ISI_PCK_PB1 ISI_PCK
|
|
|
|
|
PB2/G0_TXEN PB2 G0_TXEN,EXP
|
|
|
|
|
PB3/G0_TXER/CTS2/ISI_VSYNC ISI_VSYNC_PB3 ISI_VSYNC
|
|
|
|
|
PB4/G0_CRS/RXD2/ISI_HSYNC ISI_HSYNC_PB4 ISI_HSYNC
|
|
|
|
|
PB5/G0_COL/TXD2/PCK2 ISI_PWD_PB5 ISI_PWD
|
|
|
|
|
PB6/G0_RXDV PB6 G0_RXDV, EXP
|
|
|
|
|
PB7/G0_RXER PB7 G0_RXER, EXP
|
|
|
|
|
PB8/G0_RX0 PB8 G0_RX0, EXP
|
|
|
|
|
PB9/G0_RX1 PB9 G0_RX1, EXP
|
|
|
|
|
PB10/G0_RX2/PCK2/PWML1 PB10 AUDIO_PCK2, EXP
|
|
|
|
|
PB11/G0_RX3/RTS2/PWMH1 ISI_RST_PB11 ISI_RST
|
|
|
|
|
PB12/G0_TX0 PB12 G0_TX0, EXP
|
|
|
|
|
PB13/G0_TX1 PB13 G0_TX1, EXP
|
|
|
|
|
PB14/G0_TX2/SPI2_NPCS1/PWMH0 ZIG_SPI2_NPCS1 ZIG_SPI2_NPCS1
|
|
|
|
|
PB15/G0_TX3/SPI2_NPCS2/PWML0 HDMI_RST_PB15 HDMI_RST
|
|
|
|
|
PB16/G0_MDC PB16 G0_MDC, EXP
|
|
|
|
|
PB17/G0_MDIO PB17 G0_MDIO, EXP
|
|
|
|
|
PB18/SPI1_MISO/D8 LCD_SPI1_SO LCD_SPI1_SO
|
|
|
|
|
PB19/SPI1_MOSI/D9 LCD_SPI1_SI LCD_SPI1_SI
|
|
|
|
|
PB20/SPI1_SPCK/D10 LCD_SPI1_CLK LCD_SPI1_CLK
|
|
|
|
|
PB21/SPI1_NPCS0/D11 EXP_PB21 EXP
|
|
|
|
|
PB22/SPI1_NPCS1/D12 EXP_PB22 EXP
|
|
|
|
|
PB23/SPI1_NPCS2/D13 LCD_SPI1_CS2 LCD_SPI1_NPCS2
|
|
|
|
|
PB24/DRXD/D14/TDI PB24 TDI, EXP
|
|
|
|
|
PB25/DTXD/D15/TDO PB25 TDO, EXP
|
|
|
|
|
PB26/PCK0/RK0/PWMH0 PB26 AUDIO_RK0
|
|
|
|
|
PB27/SPI1_NPCS3/TK0/PWML0 PB27 AUDIO, HDMI_TK0, EXP
|
|
|
|
|
PB28/SPI2_NPCS3/TD0/PWMH1 PB28 AUDIO, HDMI_TD0, EXP
|
|
|
|
|
PB29/TWD2/RD0/PWML1 PB29 AUDIO_RD0, ZIG_TWD2
|
|
|
|
|
PB30/TWCK2/RF0 PB30 AUDIO_RF, ZIG_TWCK2
|
|
|
|
|
PB31/TF0 PB31 AUDIO, HDMI_TF0, EXP
|
|
|
|
|
------------------------------ ------------------- -------------------------
|
|
|
|
|
PC0/SPI0_MISO/PWMH2/ISI_D8 PC0 AT25_SPI0_SO, ISI_D8
|
|
|
|
|
PC1/SPI0_MOSI/PWML2/ISI_D9 PC1 AT25_SPI0_SI, ISI_D9
|
|
|
|
|
PC2/SPI0_SPCK/PWMH3/ISI_D10 PC2 AT25_SPI0_SPCK, ISI_D10,
|
|
|
|
|
ZIG_PWMH3_PC2
|
|
|
|
|
PC3/SPI0_NPCS0/PWML3/ISI_D11 PC3 AT25_SPI0_NCPS0, ISI_D11,
|
|
|
|
|
ZIG_PWML3_PC3 (See JP6)
|
|
|
|
|
PC4/SPI0_NPCS1/MCI0_CK/PCK1 PC4 MCI0_CK, ISI_MCK, EXP
|
|
|
|
|
PC5/D0/MCI0_CDA PC5 MCI0_CDA, NAND_IO0
|
|
|
|
|
PC6/D1/MCI0_DA0 PC6 MCI0_DA0, NAND_IO1
|
|
|
|
|
PC7/D2/MCI0_DA1 PC7 MCI0_DA1, NAND_IO2
|
|
|
|
|
PC8/D3/MCI0_DA2 PC8 MCI0_DA2, NAND_IO3
|
|
|
|
|
PC9/D4/MCI0_DA3 PC9 MCI0_DA3, NAND_IO4
|
|
|
|
|
PC10/D5/MCI0_DA4 PC10 MCI0_DA4, NAND_IO5
|
|
|
|
|
PC11/D6/MCI0_DA5 PC11 MCI0_DA5, NAND_IO6
|
|
|
|
|
PC12/D7/MCI0_DA6 PC12 MCI0_DA6, NAND_IO7
|
|
|
|
|
PC13/NRD/NANDOE/MCI0_DA7 PC13 MCI0_DA7, NAND_RE
|
|
|
|
|
PC14/NWE/NANDWE NAND_WEn NWE, NANDWE
|
|
|
|
|
PC15/NCS3 NAND_NCS3 NAND_NCS3
|
|
|
|
|
PC16/NANDRDY NAND_RDY NANDRDY
|
|
|
|
|
PC17/A21/NANDALE NAND_ALE NAND_ALE
|
|
|
|
|
PC18/A22/NANDCLE NAND_CLE NAND_CLE
|
|
|
|
|
PC19/ISI_D0/TK1 PC19 ISI_D0
|
|
|
|
|
PC20/ISI_D1/TF1 PC20 ISI_D1
|
|
|
|
|
PC21/ISI_D2/TD1 PC21 ISI_D2
|
|
|
|
|
PC22/ISI_D3/RF1 PC22 ISI_D3
|
|
|
|
|
PC23/ISI_D4/RD1 PC23 ISI_D4
|
|
|
|
|
PC24/ISI_D5/RK1/PCK1 PC24 ISI_D5
|
|
|
|
|
PC25/ISI_D6/TWD3/URXD1 PC25 AUDIO_TWD3, ISI_D6
|
|
|
|
|
PC26/ISI_D7/TWCK3/UTXD1 PC26 AUDIO_TWCK3, ISI_D7
|
|
|
|
|
PC27/AD0/SPI0_NPCS1/PWML0 AD0_XP AD0_XP
|
|
|
|
|
PC28/AD1/SPI0_NPCS2/PWML1 AD1_XM AD1_XM
|
|
|
|
|
PC29/AD2/SPI0_NPCS3/PWMFI0 AD2_YP AD2_YP
|
|
|
|
|
PC30/AD3/PWMH0 AD3_YM AD3_YM
|
|
|
|
|
PC31/AD4/PWMH1 AD4_LR AD4_LR, ADC_INPUT
|
|
|
|
|
------------------------------ ------------------- -------------------------
|
|
|
|
|
PD8/PCK0 PD8 EXP_PCK0
|
|
|
|
|
PD9/FIQ USB_OVCUR_PD9 USB_OVCUR_PD9
|
|
|
|
|
PD10/CTS0/CDETA ZIG_CTS0_PD10 ZIG_CTS0
|
|
|
|
|
PD11/RTS0/SPI2_MISO ZIG_SPI2_MISO_RTS0 ZIG_SPI2_MISO_RTS0
|
|
|
|
|
PD12/RXD0/DCENA ZIG_RXD0_PD12 ZIG_RXD0
|
|
|
|
|
PD13/TXD0/SPI2_MOSI ZIG_SPI2_MOSI_TXD0 ZIG_SPI2_MOSI_TXD0
|
|
|
|
|
PD14/CTS1/CDETB ZIG_CTS1_PD14 ZIG_CTS1
|
|
|
|
|
PD15/RTS1/SPI2_SPCK ZIG_SPI2_SPCK_RTS1 ZIG_SPI2_SPCK_RTS
|
|
|
|
|
PD16/RXD1/DCENB ZIG_RXD1_PD16 ZIG_RXD1_PD16
|
|
|
|
|
PD17/TXD1/SPI2_NPCS0 ZIG_SPI2_NPCS0_TXD1 ZIG_SPI2_NPCS0_TXD
|
|
|
|
|
PD18/SENSE0 SENSE0_PD18 SENSE0
|
|
|
|
|
PD19/SENSE1 SENSE1_PD19 SENSE1
|
|
|
|
|
PD20/SENSE2 SENSE2_PD20 SENSE2
|
|
|
|
|
PD21/SENSE3 SENSE3_PD21 SENSE3
|
|
|
|
|
PD22/SENSE4 SENSE4_PD22 SENSE4
|
|
|
|
|
PD23/SENSE5 N/C N/C
|
|
|
|
|
PD24/SENSE6 N/C N/C
|
|
|
|
|
PD25/SENSE7 N/C N/C
|
|
|
|
|
PD26/SENSE8 N/C N/C
|
|
|
|
|
PD27/SENSE9 N/C N/C
|
|
|
|
|
PD28/SCK0 N/C PD28
|
|
|
|
|
PD29/SCK1 SENSE_DISCH_PD29 SENSE_DISCH
|
|
|
|
|
PD30 EXP_PD30 EXP
|
|
|
|
|
PD31/SPI0_NPCS2/PCK1 EXP_PD31 EXP
|
|
|
|
|
------------------------------ ------------------- -------------------------
|
|
|
|
|
PE0/A0/NBS0/MCI0_CDB/CTS4 PMIC_IRQ_PE0 PMIC_IRQ
|
|
|
|
|
PE1/A1/MCI0_DB0 G0_IRQ_PE1 G0_IRQ
|
|
|
|
|
PE2/A2/MCI0_DB1 G1_IRQ_PE2 G1_IRQ
|
|
|
|
|
PE3/A3/MCI0_DB2 HDMI_IRQ_PE3 HDMI_IRQ
|
|
|
|
|
PE4/A4/MCI0_DB3 AUDIO_IRQ_PE4 AUDIO_IRQ
|
|
|
|
|
PE5/A5/CTS3 MCI0_CD_PE5 MCI0_CD
|
|
|
|
|
PE6/A6/TIOA3 MCI1_CD_PE6 MCI1_CD
|
2014-06-11 22:45:01 +02:00
|
|
|
PE7/A7/TIOB3/PWMFI1 EXP_PE7 EXP
|
2014-06-07 17:37:17 +02:00
|
|
|
PE8/A8/TCLK3/PWML3 LED_USER_PE8 LED_USER (D10)
|
|
|
|
|
PE9/A9/TIOA2 LED_POWER_PE9 LED_POWER (D9, Red)
|
|
|
|
|
PE10/A10/TIOB2 USBA_EN5V_PE10 EN5V_USBA
|
|
|
|
|
PE11/A11/TCLK2 USBB_EN5V_PE11 EN5V_USBB
|
|
|
|
|
PE12/A12/TIOA1/PWMH2 USBC_EN5V_PE12 EN5V_USBC
|
|
|
|
|
PE13/A13/TIOB1/PWML2 PB_USER1_PE13 PB_USER1
|
2014-06-29 19:26:41 +02:00
|
|
|
PE14/A14/TCLK1/PWMH3 MCI1_CD_PE14 MCI1_CD ???
|
2014-06-07 17:37:17 +02:00
|
|
|
PE15/A15/SCK3/TIOA0 MCI1_PWR_PE15 MCI1_PWR
|
|
|
|
|
PE16/A16/RXD3/TIOB0 DBGU_RXD3_PE16 DBGU_RXD3 (See JP19)
|
|
|
|
|
PE17/A17/TXD3/TCLK0 DBGU_TXD3_PE17 DBGU_TXD3 (See JP20)
|
|
|
|
|
PE18/A18/TIOA5/MCI1_CK PE18 MCI1_CK, EXP
|
|
|
|
|
PE19/A19/TIOB5/MCI1_CDA PE19 MCI1_CDA, EXP
|
|
|
|
|
PE20/A20/TCLK5/MCI1_DA0 PE20 MCI1_DA0, EXP
|
|
|
|
|
PE21/A23/TIOA4/MCI1_DA1 PE21 MCI1_DA1, EXP
|
|
|
|
|
PE22/A24/TIOB4/MCI1_DA2 PE22 MCI1_DA2, EXP
|
|
|
|
|
PE23/A25/TCLK4/MCI1_DA3 PE23 MCI1_DA3, EXP
|
|
|
|
|
PE24/NCS0/RTS3 LCD_PE24 LCD_PE24
|
|
|
|
|
PE25/NCS1/SCK4/IRQ LCD_PE25 LCD_PE25
|
|
|
|
|
PE26/NCS2/RXD4/A18 RXD4_PE26 RXD4
|
|
|
|
|
PE27/NWR1/NBS1/TXD4 TXD4_PE27 TXD4
|
|
|
|
|
PE28/NWAIT/RTS4/A19 1Wire_PE28 1-WIRE ROM, LCD, D8 (green)
|
|
|
|
|
PE29/DIBP/URXD0/TWD1 SMD_DIBP_PE29 DIBP
|
|
|
|
|
PE30/DIBN/UTXD0/TWCK1 SMD_DIBN_PE30 DIBP
|
|
|
|
|
PE31/ADTRG USBA_VBUS_PE31 USBA_VBUS_PE31
|
|
|
|
|
------------------------------ ------------------- -------------------------
|
2014-06-06 20:37:36 +02:00
|
|
|
|
|
|
|
|
Buttons and LEDs
|
|
|
|
|
================
|
|
|
|
|
|
|
|
|
|
Buttons
|
|
|
|
|
-------
|
2014-06-07 17:37:17 +02:00
|
|
|
A single button, PB_USER1 (PB2), is available on the SAMA5D4-EK:
|
2014-06-06 20:37:36 +02:00
|
|
|
|
2014-06-07 17:37:17 +02:00
|
|
|
------------------------------ ------------------- -------------------------
|
|
|
|
|
SAMA5D4 PIO SIGNAL USAGE
|
|
|
|
|
------------------------------ ------------------- -------------------------
|
|
|
|
|
PE13/A13/TIOB1/PWML2 PB_USER1_PE13 PB_USER1
|
|
|
|
|
------------------------------ ------------------- -------------------------
|
2014-06-06 20:37:36 +02:00
|
|
|
|
2014-06-07 17:37:17 +02:00
|
|
|
Closing JP2 will bring PE13 to ground so 1) PE13 should have a weak pull-up,
|
|
|
|
|
and 2) when PB2 is pressed, a low value will be senses.
|
2014-06-06 20:37:36 +02:00
|
|
|
|
|
|
|
|
LEDs
|
|
|
|
|
----
|
2014-06-07 17:37:17 +02:00
|
|
|
There are 3 LEDs on the SAMA5D4-EK:
|
|
|
|
|
|
|
|
|
|
------------------------------ ------------------- -------------------------
|
|
|
|
|
SAMA5D4 PIO SIGNAL USAGE
|
|
|
|
|
------------------------------ ------------------- -------------------------
|
|
|
|
|
PE28/NWAIT/RTS4/A19 1Wire_PE28 1-WIRE ROM, LCD, D8 (green)
|
|
|
|
|
PE8/A8/TCLK3/PWML3 LED_USER_PE8 LED_USER (D10)
|
|
|
|
|
PE9/A9/TIOA2 LED_POWER_PE9 LED_POWER (D9, Red)
|
|
|
|
|
------------------------------ ------------------- -------------------------
|
|
|
|
|
|
|
|
|
|
- D8: D8 is shared with other functions and cannot be used if the 1-Wire ROM
|
|
|
|
|
is used. I am not sure of the LCD function, but the LED may not be available
|
|
|
|
|
if the LCD is used either. We will avoid using D8 just for simplicity.
|
|
|
|
|
- D10: Nothing special here. A low output illuminates.
|
|
|
|
|
- D9: The Power ON LED. Connects to the via an IRLML2502 MOSFET. This LED will
|
|
|
|
|
be on when power is applied but otherwise a low output value will turn it
|
|
|
|
|
off.
|
2014-06-06 20:37:36 +02:00
|
|
|
|
|
|
|
|
These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
|
|
|
|
|
defined. In that case, the usage by the board port is defined in
|
|
|
|
|
include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related
|
|
|
|
|
events as follows:
|
|
|
|
|
|
|
|
|
|
SYMBOL Meaning LED state
|
2014-06-07 17:37:17 +02:00
|
|
|
USER D10 POWER D9
|
2014-06-06 20:37:36 +02:00
|
|
|
------------------- ----------------------- -------- --------
|
2014-06-07 17:37:17 +02:00
|
|
|
LED_STARTED NuttX has been started OFF ON
|
|
|
|
|
LED_HEAPALLOCATE Heap has been allocated OFF ON
|
|
|
|
|
LED_IRQSENABLED Interrupts enabled OFF ON
|
|
|
|
|
LED_STACKCREATED Idle stack created ON ON
|
2014-06-06 20:37:36 +02:00
|
|
|
LED_INIRQ In an interrupt No change
|
|
|
|
|
LED_SIGNAL In a signal handler No change
|
|
|
|
|
LED_ASSERTION An assertion failed No change
|
|
|
|
|
LED_PANIC The system has crashed OFF Blinking
|
|
|
|
|
LED_IDLE MCU is is sleep mode Not used
|
|
|
|
|
|
2014-06-07 17:37:17 +02:00
|
|
|
Thus if the D0 and D9 are statically on, NuttX has successfully booted and
|
|
|
|
|
is, apparently, running normally. If the red D9 LED is flashing at
|
2014-06-06 20:37:36 +02:00
|
|
|
approximately 2Hz, then a fatal error has been detected and the system
|
|
|
|
|
has halted.
|
|
|
|
|
|
|
|
|
|
Serial Console
|
|
|
|
|
==============
|
|
|
|
|
|
2014-06-14 16:02:58 +02:00
|
|
|
Two UART ports are available:
|
|
|
|
|
|
|
|
|
|
Virtual COM / DBGU Port (J24). Either may be driven by USART3, depending
|
|
|
|
|
upon the setting of JP19 and JP20:
|
2014-06-06 20:37:36 +02:00
|
|
|
|
2014-06-07 17:37:17 +02:00
|
|
|
------------------------------ ------------------- -------------------------
|
|
|
|
|
SAMA5D4 PIO SIGNAL USAGE
|
|
|
|
|
------------------------------ ------------------- -------------------------
|
|
|
|
|
PE16/A16/RXD3/TIOB0 DBGU_RXD3_PE16 DBGU_RXD3 (See JP19)
|
|
|
|
|
PE17/A17/TXD3/TCLK0 DBGU_TXD3_PE17 DBGU_TXD3 (See JP20)
|
|
|
|
|
------------------------------ ------------------- -------------------------
|
|
|
|
|
|
2014-06-14 16:02:58 +02:00
|
|
|
In one jumper position UART3 connects to the SAM3U which will, in turn,
|
|
|
|
|
provide the serial output over a USB virtual COM port. In other other
|
|
|
|
|
jumper position, UART3 will connect the RS-232 port labelled DBGU (J24).
|
|
|
|
|
|
|
|
|
|
I personally prefer the RS-2323 port because my terminal software does not
|
|
|
|
|
lose the USB Virtual COM everytime I reset or power-cycle the board.
|
2014-06-07 17:37:17 +02:00
|
|
|
|
|
|
|
|
USART4 TTL-Level
|
|
|
|
|
------------------------------ ------------------- -------------------------
|
|
|
|
|
SAMA5D4 PIO SIGNAL USAGE
|
|
|
|
|
------------------------------ ------------------- -------------------------
|
|
|
|
|
PE26/NCS2/RXD4/A18 RXD4_PE26 RXD4
|
|
|
|
|
PE27/NWR1/NBS1/TXD4 TXD4_PE27 TXD4
|
|
|
|
|
------------------------------ ------------------- -------------------------
|
2014-06-06 20:37:36 +02:00
|
|
|
|
2014-06-07 17:37:17 +02:00
|
|
|
A TTL-to-RS232 converter is required to use this USART for a serial console.
|
2014-06-06 20:37:36 +02:00
|
|
|
|
2014-06-07 17:37:17 +02:00
|
|
|
- RXD4/PE26 is available at Expansion Interface, J19C pin 59
|
|
|
|
|
- TXD4/PE27 is available at Expansion Interface, J19C pin 60
|
|
|
|
|
- VCC_3V3 is also available at Expansion Interface, J19B pins 21 and 22
|
|
|
|
|
- GND is available J19A pin 11, J19B pin 31, and J19C pin 51
|
2014-06-06 20:37:36 +02:00
|
|
|
|
2014-06-14 16:02:58 +02:00
|
|
|
By default the RS-232 DBGU port on USART3 is used as the NuttX serial
|
|
|
|
|
console in all configurations (unless otherwise noted). USART4, however,
|
|
|
|
|
is the also available.
|
2014-06-06 20:37:36 +02:00
|
|
|
|
|
|
|
|
Networking
|
|
|
|
|
==========
|
|
|
|
|
|
|
|
|
|
Networking support via the can be added to NSH by selecting the following
|
2014-06-07 17:37:17 +02:00
|
|
|
configuration options. The SAMA5D44 supports two different 10/100Base-T
|
|
|
|
|
Ethernet MAC peripherals.
|
|
|
|
|
|
|
|
|
|
------------------------------ ------------------- -------------------------
|
|
|
|
|
SAMA5D4 PIO SIGNAL USAGE
|
|
|
|
|
------------------------------ ------------------- -------------------------
|
|
|
|
|
PB0/G0_TXCK PB0 G0_TXCK, EXP
|
|
|
|
|
PB1/G0_RXCK/SCK2/ISI_PCK ISI_PCK_PB1 ISI_PCK
|
|
|
|
|
PB2/G0_TXEN PB2 G0_TXEN,EXP
|
|
|
|
|
PB3/G0_TXER/CTS2/ISI_VSYNC ISI_VSYNC_PB3 ISI_VSYNC
|
|
|
|
|
PB4/G0_CRS/RXD2/ISI_HSYNC ISI_HSYNC_PB4 ISI_HSYNC
|
|
|
|
|
PB5/G0_COL/TXD2/PCK2 ISI_PWD_PB5 ISI_PWD
|
|
|
|
|
PB6/G0_RXDV PB6 G0_RXDV, EXP
|
|
|
|
|
PB7/G0_RXER PB7 G0_RXER, EXP
|
|
|
|
|
PB8/G0_RX0 PB8 G0_RX0, EXP
|
|
|
|
|
PB9/G0_RX1 PB9 G0_RX1, EXP
|
|
|
|
|
PB10/G0_RX2/PCK2/PWML1 PB10 AUDIO_PCK2, EXP
|
|
|
|
|
PB11/G0_RX3/RTS2/PWMH1 ISI_RST_PB11 ISI_RST
|
|
|
|
|
PB12/G0_TX0 PB12 G0_TX0, EXP
|
|
|
|
|
PB13/G0_TX1 PB13 G0_TX1, EXP
|
|
|
|
|
PB14/G0_TX2/SPI2_NPCS1/PWMH0 ZIG_SPI2_NPCS1 ZIG_SPI2_NPCS1
|
|
|
|
|
PB15/G0_TX3/SPI2_NPCS2/PWML0 HDMI_RST_PB15 HDMI_RST
|
|
|
|
|
PB16/G0_MDC PB16 G0_MDC, EXP
|
|
|
|
|
PB17/G0_MDIO PB17 G0_MDIO, EXP
|
|
|
|
|
PE1/A1/MCI0_DB0 G0_IRQ_PE1 G0_IRQ
|
|
|
|
|
------------------------------ ------------------- -------------------------
|
|
|
|
|
PA2/LCDDAT2/G1_TXCK PA LCDDAT2, G1_TXCK
|
|
|
|
|
PA3/LCDDAT3/G1_RXCK PA3 LCDDAT3
|
|
|
|
|
PA4/LCDDAT4/G1_TXEN PA4 LCDDAT4, G1_TXEN
|
|
|
|
|
PA5/LCDDAT5/G1_TXER PA5 LCDDAT5
|
|
|
|
|
PA6/LCDDAT6/G1_CRS PA6 LCDDAT6
|
|
|
|
|
PA9/LCDDAT9/G1_COL PA9 LCDDAT9
|
|
|
|
|
PA10/LCDDAT10/G1_RXDV PA10 LCDDAT10, G1_RXDV
|
|
|
|
|
PA11/LCDDAT11/G1_RXER PA11 LCDDAT11, G1_RXER
|
|
|
|
|
PA12/LCDDAT12/G1_RX0 PA12 LCDDAT12, G1_RX0
|
|
|
|
|
PA13/LCDDAT13/G1_RX1 PA13 LCDDAT13, G1_RX1
|
|
|
|
|
PA14/LCDDAT14/G1_TX0 PA14 LCDDAT14, G1_TX0
|
|
|
|
|
PA15/LCDDAT15/G1_TX1 PA15 LCDDAT15, G1_TX1
|
|
|
|
|
PA18/LCDDAT18/G1_RX2 PA18 LCDDAT18
|
|
|
|
|
PA19/LCDDAT19/G1_RX3 PA19 LCDDAT19
|
|
|
|
|
PA20/LCDDAT20/G1_TX2 PA20 LCDDAT20
|
|
|
|
|
PA21/LCDDAT21/G1_TX3 PA21 LCDDAT21
|
|
|
|
|
PA22/LCDDAT22/G1_MDC PA22 LCDDAT22, G1_MDC
|
|
|
|
|
PA23/LCDDAT23/G1_MDIO PA23 LCDDAT23, G1_MDIO
|
|
|
|
|
PE2/A2/MCI0_DB1 G1_IRQ_PE2 G1_IRQ
|
|
|
|
|
------------------------------ ------------------- -------------------------
|
|
|
|
|
|
|
|
|
|
EMAC2 connects (directly) to a KSZ8081RNB PHY (U10) and is available at
|
|
|
|
|
the ETH0 connector.
|
|
|
|
|
|
|
|
|
|
EMAC1 connects (indirectly) to another KSZ8081RNB PHY (U7) and is available
|
|
|
|
|
at the ETH1 connector. The ETH1 signals go through a line driver that is
|
|
|
|
|
enabled via LCD_ETH1_CONFIG when an LCD is detected:
|
|
|
|
|
|
|
|
|
|
- LCD_ETH1_CONFIG = 0: LCD 5v disable
|
|
|
|
|
- LCD_ETH1_CONFIG = 1 & LCD_DETECT# =0: LCD 5v enable
|
|
|
|
|
|
|
|
|
|
But where does LCD_ETH1_CONFIG come from?
|
2014-06-06 20:37:36 +02:00
|
|
|
|
|
|
|
|
Selecting the EMAC0 peripheral
|
|
|
|
|
-----------------------------
|
|
|
|
|
|
|
|
|
|
System Type -> SAMA5 Peripheral Support
|
|
|
|
|
CONFIG_SAMA5_EMAC0=y : Enable the EMAC peripheral
|
|
|
|
|
|
|
|
|
|
System Type -> EMAC device driver options
|
|
|
|
|
CONFIG_SAMA5_EMAC0_NRXBUFFERS=16 : Set aside some RS and TX buffers
|
|
|
|
|
CONFIG_SAMA5_EMAC0_NTXBUFFERS=4
|
2014-06-07 17:37:17 +02:00
|
|
|
CONFIG_SAMA5_EMAC0_PHYADDR=1 : KSZ8081 PHY is at address 1
|
2014-06-06 20:37:36 +02:00
|
|
|
CONFIG_SAMA5_EMAC0_AUTONEG=y : Use autonegotiation
|
|
|
|
|
CONFIG_SAMA5_EMAC0_RMII=y : Either MII or RMII interface should work
|
2014-06-07 17:37:17 +02:00
|
|
|
CONFIG_SAMA5_EMAC0_PHYSR=30 : Address of PHY status register on KSZ8081
|
|
|
|
|
CONFIG_SAMA5_EMAC0_PHYSR_ALTCONFIG=y : Needed for KSZ8081
|
2014-06-06 20:37:36 +02:00
|
|
|
CONFIG_SAMA5_EMAC0_PHYSR_ALTMODE=0x7 : " " " " " "
|
|
|
|
|
CONFIG_SAMA5_EMAC0_PHYSR_10HD=0x1 : " " " " " "
|
|
|
|
|
CONFIG_SAMA5_EMAC0_PHYSR_100HD=0x2 : " " " " " "
|
|
|
|
|
CONFIG_SAMA5_EMAC0_PHYSR_10FD=0x5 : " " " " " "
|
|
|
|
|
CONFIG_SAMA5_EMAC0_PHYSR_100FD=0x6 : " " " " " "
|
|
|
|
|
|
|
|
|
|
PHY selection. Later in the configuration steps, you will need to select
|
2014-06-07 17:37:17 +02:00
|
|
|
the KSZ8081 PHY for EMAC (See below)
|
2014-06-06 20:37:36 +02:00
|
|
|
|
2014-06-07 17:37:17 +02:00
|
|
|
Selecting the EMAC1 peripheral
|
2014-06-06 20:37:36 +02:00
|
|
|
-----------------------------
|
|
|
|
|
|
|
|
|
|
System Type -> SAMA5 Peripheral Support
|
2014-06-07 17:37:17 +02:00
|
|
|
CONFIG_SAMA5_EMAC0=y : Enable the EMAC peripheral
|
2014-06-06 20:37:36 +02:00
|
|
|
|
2014-06-07 17:37:17 +02:00
|
|
|
System Type -> EMAC device driver options
|
|
|
|
|
CONFIG_SAMA5_EMAC0_NRXBUFFERS=16 : Set aside some RS and TX buffers
|
|
|
|
|
CONFIG_SAMA5_EMAC0_NTXBUFFERS=4
|
|
|
|
|
CONFIG_SAMA5_EMAC0_PHYADDR=1 : KSZ8081 PHY is at address 1
|
|
|
|
|
CONFIG_SAMA5_EMAC0_AUTONEG=y : Use autonegotiation
|
|
|
|
|
CONFIG_SAMA5_EMAC0_RMII=y : Either MII or RMII interface should work
|
|
|
|
|
CONFIG_SAMA5_EMAC0_PHYSR=30 : Address of PHY status register on KSZ8081
|
|
|
|
|
CONFIG_SAMA5_EMAC0_PHYSR_ALTCONFIG=y : Needed for KSZ8081
|
|
|
|
|
CONFIG_SAMA5_EMAC0_PHYSR_ALTMODE=0x7 : " " " " " "
|
|
|
|
|
CONFIG_SAMA5_EMAC0_PHYSR_10HD=0x1 : " " " " " "
|
|
|
|
|
CONFIG_SAMA5_EMAC0_PHYSR_100HD=0x2 : " " " " " "
|
|
|
|
|
CONFIG_SAMA5_EMAC0_PHYSR_10FD=0x5 : " " " " " "
|
|
|
|
|
CONFIG_SAMA5_EMAC0_PHYSR_100FD=0x6 : " " " " " "
|
|
|
|
|
|
|
|
|
|
PHY selection. Later in the configuration steps, you will need to select
|
|
|
|
|
the KSZ8081 PHY for EMAC (See below)
|
2014-06-06 20:37:36 +02:00
|
|
|
|
2014-06-07 17:37:17 +02:00
|
|
|
If both EMAC0 and EMAC1 are selected, you will also need:
|
2014-06-06 20:37:36 +02:00
|
|
|
|
2014-06-07 17:37:17 +02:00
|
|
|
CONFIG_SAMA5_EMAC0_ISETH0=y : EMAC0 is "eth0"; EMAC1 is "eth1"
|
2014-06-06 20:37:36 +02:00
|
|
|
|
|
|
|
|
PHY selection. Later in the configuration steps, you will need to select
|
|
|
|
|
the KSZ9081 PHY for GMAC (See below)
|
|
|
|
|
|
|
|
|
|
Common configuration settings
|
|
|
|
|
-----------------------------
|
|
|
|
|
|
|
|
|
|
Networking Support
|
|
|
|
|
CONFIG_NET=y : Enable Neworking
|
|
|
|
|
CONFIG_NET_SOCKOPTS=y : Enable socket operations
|
|
|
|
|
CONFIG_NET_BUFSIZE=562 : Maximum packet size (MTD) 1518 is more standard
|
|
|
|
|
CONFIG_NET_RECEIVE_WINDOW=562 : Should be the same as CONFIG_NET_BUFSIZE
|
|
|
|
|
CONFIG_NET_TCP=y : Enable TCP/IP networking
|
|
|
|
|
CONFIG_NET_TCPBACKLOG=y : Support TCP/IP backlog
|
|
|
|
|
CONFIG_NET_TCP_READAHEAD_BUFSIZE=562 : Read-ahead buffer size
|
|
|
|
|
CONFIG_NET_UDP=y : Enable UDP networking
|
|
|
|
|
CONFIG_NET_ICMP=y : Enable ICMP networking
|
|
|
|
|
CONFIG_NET_ICMP_PING=y : Needed for NSH ping command
|
|
|
|
|
: Defaults should be okay for other options
|
|
|
|
|
Device drivers -> Network Device/PHY Support
|
|
|
|
|
CONFIG_NETDEVICES=y : Enabled PHY selection
|
|
|
|
|
CONFIG_ETH0_PHY_KSZ8081=y : Select the KSZ8081 PHY (for EMAC), OR
|
|
|
|
|
CONFIG_ETH0_PHY_KSZ90x1=y : Select the KSZ9031 PHY (for GMAC)
|
|
|
|
|
|
|
|
|
|
Application Configuration -> Network Utilities
|
|
|
|
|
CONFIG_NETUTILS_DNSCLIENT=y : Enable host address resolution
|
|
|
|
|
CONFIG_NETUTILS_TELNETD=y : Enable the Telnet daemon
|
|
|
|
|
CONFIG_NETUTILS_TFTPC=y : Enable TFTP data file transfers for get and put commands
|
|
|
|
|
CONFIG_NETUTILS_UIPLIB=y : Network library support is needed
|
|
|
|
|
CONFIG_NETUTILS_WEBCLIENT=y : Needed for wget support
|
|
|
|
|
: Defaults should be okay for other options
|
|
|
|
|
Application Configuration -> NSH Library
|
|
|
|
|
CONFIG_NSH_TELNET=y : Enable NSH session via Telnet
|
|
|
|
|
CONFIG_NSH_IPADDR=0x0a000002 : Select an IP address
|
|
|
|
|
CONFIG_NSH_DRIPADDR=0x0a000001 : IP address of gateway/host PC
|
|
|
|
|
CONFIG_NSH_NETMASK=0xffffff00 : Netmask
|
|
|
|
|
CONFIG_NSH_NOMAC=y : Need to make up a bogus MAC address
|
|
|
|
|
: Defaults should be okay for other options
|
|
|
|
|
|
|
|
|
|
Using the network with NSH
|
|
|
|
|
--------------------------
|
|
|
|
|
|
|
|
|
|
So what can you do with this networking support? First you see that
|
|
|
|
|
NSH has several new network related commands:
|
|
|
|
|
|
|
|
|
|
ifconfig, ifdown, ifup: Commands to help manage your network
|
|
|
|
|
get and put: TFTP file transfers
|
|
|
|
|
wget: HTML file transfers
|
|
|
|
|
ping: Check for access to peers on the network
|
|
|
|
|
Telnet console: You can access the NSH remotely via telnet.
|
|
|
|
|
|
|
|
|
|
You can also enable other add on features like full FTP or a Web
|
|
|
|
|
Server or XML RPC and others. There are also other features that
|
|
|
|
|
you can enable like DHCP client (or server) or network name
|
|
|
|
|
resolution.
|
|
|
|
|
|
|
|
|
|
By default, the IP address of the SAMA4D4-EK will be 10.0.0.2 and
|
|
|
|
|
it will assume that your host is the gateway and has the IP address
|
|
|
|
|
10.0.0.1.
|
|
|
|
|
|
|
|
|
|
nsh> ifconfig
|
|
|
|
|
eth0 HWaddr 00:e0:de:ad:be:ef at UP
|
|
|
|
|
IPaddr:10.0.0.2 DRaddr:10.0.0.1 Mask:255.255.255.0
|
|
|
|
|
|
|
|
|
|
You can use ping to test for connectivity to the host (Careful,
|
|
|
|
|
Window firewalls usually block ping-related ICMP traffic). On the
|
|
|
|
|
target side, you can:
|
|
|
|
|
|
|
|
|
|
nsh> ping 10.0.0.1
|
|
|
|
|
PING 10.0.0.1 56 bytes of data
|
|
|
|
|
56 bytes from 10.0.0.1: icmp_seq=1 time=0 ms
|
|
|
|
|
56 bytes from 10.0.0.1: icmp_seq=2 time=0 ms
|
|
|
|
|
56 bytes from 10.0.0.1: icmp_seq=3 time=0 ms
|
|
|
|
|
56 bytes from 10.0.0.1: icmp_seq=4 time=0 ms
|
|
|
|
|
56 bytes from 10.0.0.1: icmp_seq=5 time=0 ms
|
|
|
|
|
56 bytes from 10.0.0.1: icmp_seq=6 time=0 ms
|
|
|
|
|
56 bytes from 10.0.0.1: icmp_seq=7 time=0 ms
|
|
|
|
|
56 bytes from 10.0.0.1: icmp_seq=8 time=0 ms
|
|
|
|
|
56 bytes from 10.0.0.1: icmp_seq=9 time=0 ms
|
|
|
|
|
56 bytes from 10.0.0.1: icmp_seq=10 time=0 ms
|
|
|
|
|
10 packets transmitted, 10 received, 0% packet loss, time 10100 ms
|
|
|
|
|
|
|
|
|
|
NOTE: In this configuration is is normal to have packet loss > 0%
|
|
|
|
|
the first time you ping due to the default handling of the ARP
|
|
|
|
|
table.
|
|
|
|
|
|
|
|
|
|
On the host side, you should also be able to ping the SAMA4D4-EK:
|
|
|
|
|
|
|
|
|
|
$ ping 10.0.0.2
|
|
|
|
|
|
|
|
|
|
You can also log into the NSH from the host PC like this:
|
|
|
|
|
|
|
|
|
|
$ telnet 10.0.0.2
|
|
|
|
|
Trying 10.0.0.2...
|
|
|
|
|
Connected to 10.0.0.2.
|
|
|
|
|
Escape character is '^]'.
|
|
|
|
|
sh_telnetmain: Session [3] Started
|
|
|
|
|
|
|
|
|
|
NuttShell (NSH) NuttX-6.31
|
|
|
|
|
nsh> help
|
|
|
|
|
help usage: help [-v] [<cmd>]
|
|
|
|
|
|
|
|
|
|
[ echo ifconfig mkdir mw sleep
|
|
|
|
|
? exec ifdown mkfatfs ping test
|
|
|
|
|
cat exit ifup mkfifo ps umount
|
|
|
|
|
cp free kill mkrd put usleep
|
|
|
|
|
cmp get losetup mh rm wget
|
|
|
|
|
dd help ls mount rmdir xd
|
|
|
|
|
df hexdump mb mv sh
|
|
|
|
|
|
|
|
|
|
Builtin Apps:
|
|
|
|
|
nsh>
|
|
|
|
|
|
|
|
|
|
NOTE: If you enable this feature, you experience a delay on booting.
|
|
|
|
|
That is because the start-up logic waits for the network connection
|
|
|
|
|
to be established before starting NuttX. In a real application, you
|
|
|
|
|
would probably want to do the network bringup on a separate thread
|
|
|
|
|
so that access to the NSH prompt is not delayed.
|
|
|
|
|
|
|
|
|
|
This delay will be especially long if the board is not connected to
|
|
|
|
|
a network.
|
|
|
|
|
|
|
|
|
|
AT25 Serial FLASH
|
|
|
|
|
=================
|
|
|
|
|
|
|
|
|
|
Connections
|
|
|
|
|
-----------
|
|
|
|
|
|
|
|
|
|
The SAMA4D4-EK board supports an options Serial DataFlash connected
|
|
|
|
|
at MN8. The SPI connection is as follows:
|
|
|
|
|
|
2014-06-07 17:37:17 +02:00
|
|
|
------------------------------ ------------------- -------------------------
|
|
|
|
|
SAMA5D4 PIO SIGNAL USAGE
|
|
|
|
|
------------------------------ ------------------- -------------------------
|
|
|
|
|
PC0/SPI0_MISO/PWMH2/ISI_D8 PC0 AT25_SPI0_SO, ISI_D8
|
|
|
|
|
PC1/SPI0_MOSI/PWML2/ISI_D9 PC1 AT25_SPI0_SI, ISI_D9
|
|
|
|
|
PC2/SPI0_SPCK/PWMH3/ISI_D10 PC2 AT25_SPI0_SPCK, ISI_D10,
|
|
|
|
|
ZIG_PWMH3_PC2
|
|
|
|
|
PC3/SPI0_NPCS0/PWML3/ISI_D11 PC3 AT25_SPI0_NCPS0, ISI_D11,
|
|
|
|
|
ZIG_PWML3_PC3 (See JP6)
|
|
|
|
|
------------------------------ ------------------- -------------------------
|
2014-06-06 20:37:36 +02:00
|
|
|
|
|
|
|
|
Configuration
|
|
|
|
|
-------------
|
|
|
|
|
|
|
|
|
|
System Type -> SAMA5 Peripheral Support
|
|
|
|
|
CONFIG_SAMA5_SPI0=y : Enable SPI0
|
|
|
|
|
CONFIG_SAMA5_DMAC0=y : Enable DMA controller 0
|
|
|
|
|
|
|
|
|
|
System Type -> SPI device driver options
|
|
|
|
|
CONFIG_SAMA5_SPI_DMA=y : Use DMA for SPI transfers
|
|
|
|
|
CONFIG_SAMA5_SPI_DMATHRESHOLD=4 : Don't DMA for small transfers
|
|
|
|
|
|
|
|
|
|
Device Drivers -> SPI Driver Support
|
|
|
|
|
CONFIG_SPI=y : Enable SPI support
|
|
|
|
|
CONFIG_SPI_EXCHANGE=y : Support the exchange method
|
|
|
|
|
|
|
|
|
|
Device Drivers -> Memory Technology Device (MTD) Support
|
|
|
|
|
CONFIG_MTD=y : Enable MTD support
|
|
|
|
|
CONFIG_MTD_AT25=y : Enable the AT25 driver
|
|
|
|
|
CONFIG_AT25_SPIMODE=0 : Use SPI mode 0
|
|
|
|
|
CONFIG_AT25_SPIFREQUENCY=10000000 : Use SPI frequency 10MHz
|
|
|
|
|
|
|
|
|
|
The AT25 is capable of higher SPI rates than this. I have not experimented
|
|
|
|
|
a lot, but at 20MHz, the behavior is not the same with all CM modules. This
|
|
|
|
|
lower rate gives more predictable performance.
|
|
|
|
|
|
|
|
|
|
Application Configuration -> NSH Library
|
|
|
|
|
CONFIG_NSH_ARCHINIT=y : NSH board-initialization
|
|
|
|
|
|
|
|
|
|
Board Selection
|
|
|
|
|
CONFIG_SAMA5D4EK_AT25_AUTOMOUNT=y : Mounts AT25 for NSH
|
|
|
|
|
CONFIG_SAMA5D4EK_AT25_FTL=y : Create block driver for FAT
|
|
|
|
|
|
|
|
|
|
NOTE: that you must close JP6 in order to enable the AT25 FLASH chip select.
|
|
|
|
|
|
|
|
|
|
You can then format the AT25 FLASH for a FAT file system and mount the
|
|
|
|
|
file system at /mnt/at25 using these NSH commands:
|
|
|
|
|
|
|
|
|
|
nsh> mkfatfs /dev/mtdblock0
|
|
|
|
|
nsh> mount -t vfat /dev/mtdblock0 /mnt/at25
|
|
|
|
|
|
|
|
|
|
Then you an use the FLASH as a normal FAT file system:
|
|
|
|
|
|
|
|
|
|
nsh> echo "This is a test" >/mnt/at25/atest.txt
|
|
|
|
|
nsh> ls -l /mnt/at25
|
|
|
|
|
/mnt/at25:
|
|
|
|
|
-rw-rw-rw- 16 atest.txt
|
|
|
|
|
nsh> cat /mnt/at25/atest.txt
|
|
|
|
|
This is a test
|
|
|
|
|
|
|
|
|
|
HSMCI Card Slots
|
|
|
|
|
================
|
|
|
|
|
|
|
|
|
|
Physical Slots
|
|
|
|
|
--------------
|
|
|
|
|
|
|
|
|
|
The SAMA4D4-EK provides a two SD memory card slots: (1) a full size SD
|
|
|
|
|
card slot (J10), and (2) a microSD memory card slot (J11).
|
|
|
|
|
|
2014-06-11 22:45:01 +02:00
|
|
|
HSMCI0
|
|
|
|
|
------
|
2014-06-06 20:37:36 +02:00
|
|
|
The full size SD card slot connects via HSMCI0. The card detect discrete
|
2014-06-11 22:45:01 +02:00
|
|
|
is available on PE5 (pulled high). The write protect discrete is tied to
|
|
|
|
|
ground and is not available to software. The slot supports 8-bit wide
|
2014-06-06 20:37:36 +02:00
|
|
|
transfer mode, but the NuttX driver currently uses only the 4-bit wide
|
|
|
|
|
transfer mode
|
|
|
|
|
|
2014-06-11 22:45:01 +02:00
|
|
|
------------------------------ ------------------- -------------------------
|
|
|
|
|
SAMA5D4 PIO SIGNAL USAGE
|
|
|
|
|
------------------------------ ------------------- -------------------------
|
|
|
|
|
PC4/SPI0_NPCS1/MCI0_CK/PCK1 PC4 MCI0_CK, ISI_MCK, EXP
|
|
|
|
|
PC5/D0/MCI0_CDA PC5 MCI0_CDA, NAND_IO0
|
|
|
|
|
PC6/D1/MCI0_DA0 PC6 MCI0_DA0, NAND_IO1
|
|
|
|
|
PC7/D2/MCI0_DA1 PC7 MCI0_DA1, NAND_IO2
|
|
|
|
|
PC8/D3/MCI0_DA2 PC8 MCI0_DA2, NAND_IO3
|
|
|
|
|
PC9/D4/MCI0_DA3 PC9 MCI0_DA3, NAND_IO4
|
|
|
|
|
PC10/D5/MCI0_DA4 PC10 MCI0_DA4, NAND_IO5
|
|
|
|
|
PC11/D6/MCI0_DA5 PC11 MCI0_DA5, NAND_IO6
|
|
|
|
|
PC12/D7/MCI0_DA6 PC12 MCI0_DA6, NAND_IO7
|
|
|
|
|
PC13/NRD/NANDOE/MCI0_DA7 PC13 MCI0_DA7, NAND_RE
|
|
|
|
|
PE5/A5/CTS3 MCI0_CD_PE5 MCI0_CD
|
|
|
|
|
------------------------------ ------------------- -------------------------
|
2014-06-06 20:37:36 +02:00
|
|
|
|
2014-06-11 22:45:01 +02:00
|
|
|
HSMCI1
|
|
|
|
|
------
|
2014-06-06 20:37:36 +02:00
|
|
|
The microSD connects vi HSMCI1. The card detect discrete is available on
|
2014-06-29 19:26:41 +02:00
|
|
|
PE6 (pulled high). NOTE that PE15 must be controlled to provide power
|
2014-06-11 22:57:14 +02:00
|
|
|
to the HSMCI1 slot (the HSMCI0 slot is always powered).
|
2014-06-06 20:37:36 +02:00
|
|
|
|
2014-06-11 22:45:01 +02:00
|
|
|
------------------------------ ------------------- -------------------------
|
|
|
|
|
SAMA5D4 PIO SIGNAL USAGE
|
|
|
|
|
------------------------------ ------------------- -------------------------
|
2014-06-29 19:26:41 +02:00
|
|
|
PE14/A14/TCLK1/PWMH3 MCI1_CD_PE14 MCI1_CD ???
|
2014-06-11 22:45:01 +02:00
|
|
|
PE15/A15/SCK3/TIOA0 MCI1_PWR_PE15 MCI1_PWR
|
|
|
|
|
PE18/A18/TIOA5/MCI1_CK PE18 MCI1_CK, EXP
|
|
|
|
|
PE19/A19/TIOB5/MCI1_CDA PE19 MCI1_CDA, EXP
|
|
|
|
|
PE20/A20/TCLK5/MCI1_DA0 PE20 MCI1_DA0, EXP
|
|
|
|
|
PE21/A23/TIOA4/MCI1_DA1 PE21 MCI1_DA1, EXP
|
|
|
|
|
PE22/A24/TIOB4/MCI1_DA2 PE22 MCI1_DA2, EXP
|
|
|
|
|
PE23/A25/TCLK4/MCI1_DA3 PE23 MCI1_DA3, EXP
|
|
|
|
|
PE6/A6/TIOA3 MCI1_CD_PE6 MCI1_CD
|
|
|
|
|
------------------------------ ------------------- -------------------------
|
2014-06-06 20:37:36 +02:00
|
|
|
|
|
|
|
|
Configuration Settings
|
|
|
|
|
----------------------
|
|
|
|
|
|
|
|
|
|
Enabling HSMCI support. The SAMA4D4-EK provides a two SD memory card
|
|
|
|
|
slots: (1) a full size SD card slot (J10), and (2) a microSD memory card
|
|
|
|
|
slot (J11). The full size SD card slot connects via HSMCI0; the microSD
|
|
|
|
|
connects via HSMCI1. Support for both SD slots can be enabled with the
|
|
|
|
|
following settings:
|
|
|
|
|
|
|
|
|
|
System Type->ATSAMA5 Peripheral Support
|
|
|
|
|
CONFIG_SAMA5_HSMCI0=y : Enable HSMCI0 support
|
|
|
|
|
CONFIG_SAMA5_HSMCI1=y : Enable HSMCI1 support
|
2014-06-29 19:26:41 +02:00
|
|
|
CONFIG_SAMA5_XDMAC1=y : XDMAC1 is needed by HSMCI0/1
|
2014-06-06 20:37:36 +02:00
|
|
|
|
|
|
|
|
System Type
|
|
|
|
|
CONFIG_SAMA5_PIO_IRQ=y : PIO interrupts needed
|
2014-06-29 19:26:41 +02:00
|
|
|
CONFIG_SAMA5_PIOE_IRQ=y : Card detect pins are on PE5 and PE6
|
2014-06-06 20:37:36 +02:00
|
|
|
|
|
|
|
|
Device Drivers -> MMC/SD Driver Support
|
|
|
|
|
CONFIG_MMCSD=y : Enable MMC/SD support
|
|
|
|
|
CONFIG_MMSCD_NSLOTS=1 : One slot per driver instance
|
|
|
|
|
CONFIG_MMCSD_HAVECARDDETECT=y : Supports card-detect PIOs
|
|
|
|
|
CONFIG_MMCSD_MMCSUPPORT=n : Interferes with some SD cards
|
|
|
|
|
CONFIG_MMCSD_SPI=n : No SPI-based MMC/SD support
|
|
|
|
|
CONFIG_MMCSD_SDIO=y : SDIO-based MMC/SD support
|
|
|
|
|
CONFIG_SDIO_DMA=y : Use SDIO DMA
|
|
|
|
|
CONFIG_SDIO_BLOCKSETUP=y : Needs to know block sizes
|
|
|
|
|
|
|
|
|
|
Library Routines
|
|
|
|
|
CONFIG_SCHED_WORKQUEUE=y : Driver needs work queue support
|
|
|
|
|
|
|
|
|
|
Application Configuration -> NSH Library
|
|
|
|
|
CONFIG_NSH_ARCHINIT=y : NSH board-initialization
|
|
|
|
|
|
|
|
|
|
Using the SD card
|
|
|
|
|
-----------------
|
|
|
|
|
|
|
|
|
|
1) After booting, the HSCMI devices will appear as /dev/mmcsd0
|
|
|
|
|
and /dev/mmcsd1.
|
|
|
|
|
|
|
|
|
|
2) If you try mounting an SD card with nothing in the slot, the
|
|
|
|
|
mount will fail:
|
|
|
|
|
|
|
|
|
|
nsh> mount -t vfat /dev/mmcsd1 /mnt/sd1
|
|
|
|
|
nsh: mount: mount failed: 19
|
|
|
|
|
|
|
|
|
|
NSH can be configured to provide errors as strings instead of
|
|
|
|
|
numbers. But in this case, only the error number is reported. The
|
|
|
|
|
error numbers can be found in nuttx/include/errno.h:
|
|
|
|
|
|
|
|
|
|
#define ENODEV 19
|
|
|
|
|
#define ENODEV_STR "No such device"
|
|
|
|
|
|
|
|
|
|
So the mount command is saying that there is no device or, more
|
|
|
|
|
correctly, that there is no card in the SD card slot.
|
|
|
|
|
|
|
|
|
|
3) Inserted the SD card. Then the mount should succeed.
|
|
|
|
|
|
|
|
|
|
nsh> mount -t vfat /dev/mmcsd1 /mnt/sd1
|
|
|
|
|
nsh> ls /mnt/sd1
|
|
|
|
|
/mnt/sd1:
|
|
|
|
|
atest.txt
|
|
|
|
|
nsh> cat /mnt/sd1/atest.txt
|
|
|
|
|
This is a test
|
|
|
|
|
|
|
|
|
|
4) Before removing the card, you must umount the file system. This is
|
|
|
|
|
equivalent to "ejecting" or "safely removing" the card on Windows: It
|
|
|
|
|
flushes any cached data to the card and makes the SD card unavailable
|
|
|
|
|
to the applications.
|
|
|
|
|
|
|
|
|
|
nsh> umount -t /mnt/sd1
|
|
|
|
|
|
|
|
|
|
It is now safe to remove the card. NuttX provides into callbacks
|
|
|
|
|
that can be used by an application to automatically unmount the
|
|
|
|
|
volume when it is removed. But those callbacks are not used in
|
|
|
|
|
these configurations.
|
|
|
|
|
|
|
|
|
|
USB Ports
|
|
|
|
|
=========
|
|
|
|
|
|
|
|
|
|
The SAMA4D4-EK features three USB communication ports:
|
|
|
|
|
|
|
|
|
|
* Port A Host High Speed (EHCI) and Full Speed (OHCI) multiplexed with
|
2014-06-07 17:37:17 +02:00
|
|
|
USB Device High Speed Micro AB connector, J1
|
2014-06-06 20:37:36 +02:00
|
|
|
|
|
|
|
|
* Port B Host High Speed (EHCI) and Full Speed (OHCI) standard type A
|
2014-06-07 17:37:17 +02:00
|
|
|
connector, J5 upper port
|
2014-06-06 20:37:36 +02:00
|
|
|
|
2014-06-07 17:37:17 +02:00
|
|
|
* Port C Host Full Speed (OHCI) and Full Speed (OHCI) standard type A
|
|
|
|
|
connector, J5 lower port
|
2014-06-06 20:37:36 +02:00
|
|
|
|
2014-06-07 17:37:17 +02:00
|
|
|
The three USB host ports are equipped with 500-mA high-side power
|
2014-06-06 20:37:36 +02:00
|
|
|
switch for self-powered and bus-powered applications.
|
|
|
|
|
|
2014-06-07 17:37:17 +02:00
|
|
|
The USB device port A (J5) features a VBUS insert detection function.
|
2014-06-06 20:37:36 +02:00
|
|
|
|
|
|
|
|
Port A
|
|
|
|
|
------
|
|
|
|
|
|
2014-06-07 17:37:17 +02:00
|
|
|
PIO Signal Name Function
|
|
|
|
|
---- -------------- -------------------------------------------------------
|
|
|
|
|
PE10 EN5V_USBA VBus power enable (via MN2 power switch) to VBus pin of
|
|
|
|
|
the OTG connector (host)
|
|
|
|
|
PE31 USBA_VBUS_PE31 VBus sensing from the VBus pin of the OTG connector (device)
|
2014-06-06 20:37:36 +02:00
|
|
|
|
|
|
|
|
Port B
|
|
|
|
|
------
|
|
|
|
|
|
2014-06-07 17:37:17 +02:00
|
|
|
PIO Signal Name Function
|
|
|
|
|
---- -------------- -------------------------------------------------------
|
|
|
|
|
PE11 EN5V_USBB VBus power enable (via MN4 power switch). To the A1
|
|
|
|
|
pin of J5 Dual USB A connector
|
2014-06-06 20:37:36 +02:00
|
|
|
|
|
|
|
|
Port C
|
|
|
|
|
------
|
|
|
|
|
|
2014-06-07 17:37:17 +02:00
|
|
|
PIO Signal Name Function
|
|
|
|
|
---- -------------- -------------------------------------------------------
|
|
|
|
|
PE12 EN5V_USBC VBus power enable (via MN4 power switch). To the B1
|
|
|
|
|
pin of J5 Dual USB A connector
|
2014-06-06 20:37:36 +02:00
|
|
|
|
|
|
|
|
Both Ports B and C
|
|
|
|
|
------------------
|
|
|
|
|
|
|
|
|
|
PIO Signal Name Function
|
|
|
|
|
---- ----------- -------------------------------------------------------
|
|
|
|
|
PE5 OVCUR_USB Combined over-current indication from port A and B
|
|
|
|
|
|
|
|
|
|
USB High-Speed Device
|
|
|
|
|
=====================
|
|
|
|
|
|
|
|
|
|
Basic USB High-Speed Device Configuration
|
|
|
|
|
-----------------------------------------
|
|
|
|
|
|
|
|
|
|
Support the USB high-speed device (UDPHS) driver can be enabled with these
|
|
|
|
|
NuttX configuration settings.
|
|
|
|
|
|
|
|
|
|
Device Drivers -> USB Device Driver Support
|
|
|
|
|
CONFIG_USBDEV=y : Enable USB device support
|
|
|
|
|
CONFIG_USBDEV_DUALSPEED=y : Device support High and Full Speed
|
|
|
|
|
CONFIG_USBDEV_DMA=y : Device uses DMA
|
|
|
|
|
|
|
|
|
|
System Type -> ATSAMA5 Peripheral Support
|
|
|
|
|
CONFIG_SAMA5_UDPHS=y : Enable UDPHS High Speed USB device
|
|
|
|
|
|
|
|
|
|
Application Configuration -> NSH Library
|
|
|
|
|
CONFIG_NSH_ARCHINIT=y : NSH board-initialization
|
|
|
|
|
|
|
|
|
|
Mass Storage Class
|
|
|
|
|
------------------
|
|
|
|
|
|
|
|
|
|
The Mass Storage Class (MSC) class driver is selected for use with
|
|
|
|
|
UDPHS:
|
|
|
|
|
|
|
|
|
|
Device Drivers -> USB Device Driver Support
|
|
|
|
|
CONFIG_USBMSC=y : Enable the USB MSC class driver
|
|
|
|
|
CONFIG_USBMSC_EPBULKOUT=1 : Use EP1 for the BULK OUT endpoint
|
|
|
|
|
CONFIG_USBMSC_EPBULKIN=2 : Use EP2 for the BULK IN endpoint
|
|
|
|
|
|
|
|
|
|
The following setting enables an add-on that can can be used to control
|
|
|
|
|
the USB MSC device. It will add two new NSH commands:
|
|
|
|
|
|
|
|
|
|
a. msconn will connect the USB serial device and export the AT25
|
|
|
|
|
to the host, and
|
|
|
|
|
b. msdis which will disconnect the USB serial device.
|
|
|
|
|
|
|
|
|
|
Application Configuration -> System Add-Ons:
|
|
|
|
|
CONFIG_SYSTEM_USBMSC=y : Enable the USBMSC add-on
|
|
|
|
|
CONFIG_SYSTEM_USBMSC_NLUNS=1 : One LUN
|
|
|
|
|
CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 : Minor device zero
|
|
|
|
|
CONFIG_SYSTEM_USBMSC_DEVPATH1="/dev/mtdblock0"
|
|
|
|
|
: Use a single, LUN: The AT25
|
|
|
|
|
: block driver.
|
|
|
|
|
|
|
|
|
|
NOTES:
|
|
|
|
|
|
|
|
|
|
a. To prevent file system corruption, make sure that the AT25 is un-
|
|
|
|
|
mounted *before* exporting the mass storage device to the host:
|
|
|
|
|
|
|
|
|
|
nsh> umount /mnt/at25
|
|
|
|
|
nsh> mscon
|
|
|
|
|
|
|
|
|
|
The AT25 can be re-mounted after the mass storage class is disconnected:
|
|
|
|
|
|
|
|
|
|
nsh> msdis
|
|
|
|
|
nsh> mount -t vfat /dev/mtdblock0 /mnt/at25
|
|
|
|
|
|
|
|
|
|
b. If you change the value CONFIG_SYSTEM_USBMSC_DEVPATH1, then you
|
|
|
|
|
can export other file systems:
|
|
|
|
|
|
|
|
|
|
"/dev/mmcsd1" will export the HSMCI1 microSD
|
|
|
|
|
"/dev/mmcsd0" will export the HSMCI0 full-size SD slot
|
|
|
|
|
"/dev/ram0" could even be used to export a RAM disk. But you would
|
|
|
|
|
first have to use mkrd to create the RAM disk and mkfatfs to put
|
|
|
|
|
a FAT file system on it.
|
|
|
|
|
|
|
|
|
|
CDC/ACM Serial Device Class
|
|
|
|
|
---------------------------
|
|
|
|
|
|
|
|
|
|
This will select the CDC/ACM serial device. Defaults for the other
|
|
|
|
|
options should be okay.
|
|
|
|
|
|
|
|
|
|
Device Drivers -> USB Device Driver Support
|
|
|
|
|
CONFIG_CDCACM=y : Enable the CDC/ACM device
|
|
|
|
|
CONFIG_CDCACM_BULKIN_REQLEN=768 : Default too small for high-speed
|
|
|
|
|
|
|
|
|
|
The following setting enables an example that can can be used to control
|
|
|
|
|
the CDC/ACM device. It will add two new NSH commands:
|
|
|
|
|
|
|
|
|
|
a. sercon will connect the USB serial device (creating /dev/ttyACM0), and
|
|
|
|
|
b. serdis which will disconnect the USB serial device (destroying
|
|
|
|
|
/dev/ttyACM0).
|
|
|
|
|
|
|
|
|
|
Application Configuration -> Examples:
|
|
|
|
|
CONFIG_SYSTEM_CDCACM=y : Enable an CDC/ACM example
|
|
|
|
|
|
|
|
|
|
Debugging USB Device
|
|
|
|
|
--------------------
|
|
|
|
|
|
|
|
|
|
There is normal console debug output available that can be enabled with
|
|
|
|
|
CONFIG_DEBUG + CONFIG_DEBUG_USB. However, USB device operation is very
|
|
|
|
|
time critical and enabling this debug output WILL interfere with the
|
|
|
|
|
operation of the UDPHS. USB device tracing is a less invasive way to get
|
|
|
|
|
debug information: If tracing is enabled, the USB device will save
|
|
|
|
|
encoded trace output in in-memory buffer; if the USB monitor is also
|
|
|
|
|
enabled, that trace buffer will be periodically emptied and dumped to the
|
|
|
|
|
system logging device (the serial console in this configuration):
|
|
|
|
|
|
|
|
|
|
Device Drivers -> "USB Device Driver Support:
|
|
|
|
|
CONFIG_USBDEV_TRACE=y : Enable USB trace feature
|
|
|
|
|
CONFIG_USBDEV_TRACE_NRECORDS=256 : Buffer 256 records in memory
|
|
|
|
|
CONFIG_USBDEV_TRACE_STRINGS=y : (optional)
|
|
|
|
|
|
|
|
|
|
Application Configuration -> NSH LIbrary:
|
|
|
|
|
CONFIG_NSH_USBDEV_TRACE=n : No builtin tracing from NSH
|
|
|
|
|
CONFIG_NSH_ARCHINIT=y : Automatically start the USB monitor
|
|
|
|
|
|
|
|
|
|
Application Configuration -> System NSH Add-Ons:
|
|
|
|
|
CONFIG_SYSTEM_USBMONITOR=y : Enable the USB monitor daemon
|
|
|
|
|
CONFIG_SYSTEM_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size
|
|
|
|
|
CONFIG_SYSTEM_USBMONITOR_PRIORITY=50 : USB monitor daemon priority
|
|
|
|
|
CONFIG_SYSTEM_USBMONITOR_INTERVAL=1 : Dump trace data every second
|
|
|
|
|
CONFIG_SYSTEM_USBMONITOR_TRACEINIT=y : Enable TRACE output
|
|
|
|
|
CONFIG_SYSTEM_USBMONITOR_TRACECLASS=y
|
|
|
|
|
CONFIG_SYSTEM_USBMONITOR_TRACETRANSFERS=y
|
|
|
|
|
CONFIG_SYSTEM_USBMONITOR_TRACECONTROLLER=y
|
|
|
|
|
CONFIG_SYSTEM_USBMONITOR_TRACEINTERRUPTS=y
|
|
|
|
|
|
|
|
|
|
NOTE: If USB debug output is also enabled, both outputs will appear on the
|
|
|
|
|
serial console. However, the debug output will be asynchronous with the
|
|
|
|
|
trace output and, hence, difficult to interpret.
|
|
|
|
|
|
|
|
|
|
USB High-Speed Host
|
|
|
|
|
===================
|
|
|
|
|
|
|
|
|
|
OHCI Only
|
|
|
|
|
---------
|
|
|
|
|
|
|
|
|
|
Support the USB low/full-speed OHCI host driver can be enabled by changing
|
|
|
|
|
the NuttX configuration file as follows:
|
|
|
|
|
|
|
|
|
|
System Type -> ATSAMA5 Peripheral Support
|
|
|
|
|
CONFIG_SAMA5_UHPHS=y : USB Host High Speed
|
|
|
|
|
|
|
|
|
|
System Type -> USB High Speed Host driver options
|
|
|
|
|
CONFIG_SAMA5_OHCI=y : Low/full-speed OHCI support
|
|
|
|
|
: Defaults for values probably OK
|
|
|
|
|
Device Drivers
|
|
|
|
|
CONFIG_USBHOST=y : Enable USB host support
|
|
|
|
|
|
|
|
|
|
Device Drivers -> USB Host Driver Support
|
|
|
|
|
CONFIG_USBHOST_ISOC_DISABLE=y : Isochronous endpoints not used
|
|
|
|
|
CONFIG_USBHOST_MSC=y : Enable the mass storage class driver
|
|
|
|
|
CONFIG_USBHOST_HIDKBD=y : Enable the HID keyboard class driver
|
|
|
|
|
|
|
|
|
|
Library Routines
|
|
|
|
|
CONFIG_SCHED_WORKQUEUE=y : Worker thread support is required
|
|
|
|
|
|
|
|
|
|
Application Configuration -> NSH Library
|
|
|
|
|
CONFIG_NSH_ARCHINIT=y : NSH board-initialization
|
|
|
|
|
|
|
|
|
|
NOTE: When OHCI is selected, the SAMA5 will operate at 384MHz instead of
|
|
|
|
|
396MHz. This is so that the PLL generates a frequency which is a multiple
|
|
|
|
|
of the 48MHz needed for OHCI. The delay loop calibration values that are
|
|
|
|
|
used will be off slightly because of this.
|
|
|
|
|
|
|
|
|
|
EHCI
|
|
|
|
|
----
|
|
|
|
|
|
|
|
|
|
Support the USB high-speed EHCI host driver can be enabled by changing the
|
|
|
|
|
NuttX configuration file as follows. If EHCI is enabled by itself, then
|
|
|
|
|
only high-speed devices can be supported. If OHCI is also enabled, then
|
|
|
|
|
all low-, full-, and high speed devices will work.
|
|
|
|
|
|
|
|
|
|
System Type -> ATSAMA5 Peripheral Support
|
|
|
|
|
CONFIG_SAMA5_UHPHS=y : USB Host High Speed
|
|
|
|
|
|
|
|
|
|
System Type -> USB High Speed Host driver options
|
|
|
|
|
CONFIG_SAMA5_EHCI=y : High-speed EHCI support
|
|
|
|
|
CONFIG_SAMA5_OHCI=y : Low/full-speed OHCI support
|
|
|
|
|
: Defaults for values probably OK for both
|
|
|
|
|
Device Drivers
|
|
|
|
|
CONFIG_USBHOST=y : Enable USB host support
|
|
|
|
|
CONFIG_USBHOST_INT_DISABLE=y : Interrupt endpoints not needed
|
|
|
|
|
CONFIG_USBHOST_ISOC_DISABLE=y : Isochronous endpoints not needed
|
|
|
|
|
|
|
|
|
|
Device Drivers -> USB Host Driver Support
|
|
|
|
|
CONFIG_USBHOST_ISOC_DISABLE=y : Isochronous endpoints not used
|
|
|
|
|
CONFIG_USBHOST_MSC=y : Enable the mass storage class driver
|
|
|
|
|
CONFIG_USBHOST_HIDKBD=y : Enable the HID keyboard class driver
|
|
|
|
|
|
|
|
|
|
Library Routines
|
|
|
|
|
CONFIG_SCHED_WORKQUEUE=y : Worker thread support is required
|
|
|
|
|
|
|
|
|
|
Application Configuration -> NSH Library
|
|
|
|
|
CONFIG_NSH_ARCHINIT=y : NSH board-initialization
|
|
|
|
|
|
|
|
|
|
Mass Storage Device Usage
|
|
|
|
|
-------------------------
|
|
|
|
|
|
|
|
|
|
Example Usage:
|
|
|
|
|
|
|
|
|
|
NuttShell (NSH) NuttX-6.29
|
|
|
|
|
nsh> ls /dev
|
|
|
|
|
/dev:
|
|
|
|
|
console
|
|
|
|
|
mtdblock0
|
|
|
|
|
null
|
|
|
|
|
ttyS0
|
|
|
|
|
|
|
|
|
|
Here a USB FLASH stick is inserted. Nothing visible happens in the
|
|
|
|
|
shell. But a new device will appear:
|
|
|
|
|
|
|
|
|
|
nsh> ls /dev
|
|
|
|
|
/dev:
|
|
|
|
|
console
|
|
|
|
|
mtdblock0
|
|
|
|
|
null
|
|
|
|
|
sda
|
|
|
|
|
ttyS0
|
|
|
|
|
nsh> mount -t vfat /dev/sda /mnt/sda
|
|
|
|
|
nsh> ls -l /mnt/sda
|
|
|
|
|
/mnt/sda:
|
|
|
|
|
-rw-rw-rw- 8788 viminfo
|
|
|
|
|
drw-rw-rw- 0 .Trash-1000/
|
|
|
|
|
-rw-rw-rw- 3378 zmodem.patch
|
|
|
|
|
-rw-rw-rw- 1503 sz-1.log
|
|
|
|
|
-rw-rw-rw- 613 .bashrc
|
|
|
|
|
|
|
|
|
|
HID Keyboard Usage
|
|
|
|
|
------------------
|
|
|
|
|
|
|
|
|
|
If a (supported) USB keyboard is connected, a /dev/kbda device will appear:
|
|
|
|
|
|
|
|
|
|
nsh> ls /dev
|
|
|
|
|
/dev:
|
|
|
|
|
console
|
|
|
|
|
kbda
|
|
|
|
|
mtdblock0
|
|
|
|
|
null
|
|
|
|
|
ttyS0
|
|
|
|
|
|
|
|
|
|
/dev/kbda is a read-only serial device. Reading from /dev/kbda will get
|
|
|
|
|
keyboard input as ASCII data (other encodings are possible):
|
|
|
|
|
|
|
|
|
|
nsh> cat /dev/kbda
|
|
|
|
|
|
|
|
|
|
Debugging USB Host
|
|
|
|
|
------------------
|
|
|
|
|
|
|
|
|
|
There is normal console debug output available that can be enabled with
|
|
|
|
|
CONFIG_DEBUG + CONFIG_DEBUG_USB. However, USB host operation is very time
|
|
|
|
|
critical and enabling this debug output might interfere with the operation
|
|
|
|
|
of the UDPHS. USB host tracing is a less invasive way to get debug
|
|
|
|
|
information: If tracing is enabled, the USB host will save encoded trace
|
|
|
|
|
output in in-memory buffer; if the USB monitor is also enabled, that trace
|
|
|
|
|
buffer will be periodically emptied and dumped to the system logging device
|
|
|
|
|
(the serial console in this configuration):
|
|
|
|
|
|
|
|
|
|
Device Drivers -> "USB Host Driver Support:
|
|
|
|
|
CONFIG_USBHOST_TRACE=y : Enable USB host trace feature
|
|
|
|
|
CONFIG_USBHOST_TRACE_NRECORDS=256 : Buffer 256 records in memory
|
|
|
|
|
CONFIG_USBHOST_TRACE_VERBOSE=y : Buffer everything
|
|
|
|
|
|
|
|
|
|
Application Configuration -> NSH LIbrary:
|
|
|
|
|
CONFIG_NSH_USBDEV_TRACE=n : No builtin tracing from NSH
|
|
|
|
|
CONFIG_NSH_ARCHINIT=y : Automatically start the USB monitor
|
|
|
|
|
|
|
|
|
|
Application Configuration -> System NSH Add-Ons:
|
|
|
|
|
CONFIG_SYSTEM_USBMONITOR=y : Enable the USB monitor daemon
|
|
|
|
|
CONFIG_SYSTEM_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size
|
|
|
|
|
CONFIG_SYSTEM_USBMONITOR_PRIORITY=50 : USB monitor daemon priority
|
|
|
|
|
CONFIG_SYSTEM_USBMONITOR_INTERVAL=1 : Dump trace data every second
|
|
|
|
|
|
|
|
|
|
NOTE: If USB debug output is also enabled, both outpus will appear on the
|
|
|
|
|
serial console. However, the debug output will be asynchronous with the
|
|
|
|
|
trace output and, hence, difficult to interpret.
|
|
|
|
|
|
|
|
|
|
SDRAM Support
|
|
|
|
|
=============
|
|
|
|
|
|
|
|
|
|
SRAM Heap Configuration
|
|
|
|
|
-----------------------
|
|
|
|
|
|
|
|
|
|
In these configurations, .data and .bss are retained in ISRAM. SDRAM can
|
|
|
|
|
be initialized and included in the heap. Relevant configuration settings:
|
|
|
|
|
|
|
|
|
|
System Type->ATSAMA5 Peripheral Support
|
|
|
|
|
CONFIG_SAMA5_MPDDRC=y : Enable the DDR controller
|
|
|
|
|
|
|
|
|
|
System Type->External Memory Configuration
|
|
|
|
|
CONFIG_SAMA5_DDRCS=y : Tell the system that DRAM is at the DDR CS
|
|
|
|
|
CONFIG_SAMA5_DDRCS_SIZE=268435456 : 2Gb DRAM -> 256MB
|
|
|
|
|
CONFIG_SAMA5_DDRCS_LPDDR2=y : Its DDR2
|
|
|
|
|
CONFIG_SAMA5D4EK_MT47H128M16RT=y : This is the type of DDR2
|
|
|
|
|
|
|
|
|
|
System Type->Heap Configuration
|
|
|
|
|
CONFIG_SAMA5_DDRCS_HEAP=y : Add the SDRAM to the heap
|
|
|
|
|
CONFIG_SAMA5_DDRCS_HEAP_OFFSET=0
|
|
|
|
|
CONFIG_SAMA5_DDRCS_HEAP_SIZE=268435456
|
|
|
|
|
|
|
|
|
|
Memory Management
|
|
|
|
|
CONFIG_MM_REGIONS=2 : Two heap memory regions: ISRAM and SDRAM
|
|
|
|
|
|
|
|
|
|
RAM Test
|
|
|
|
|
--------
|
|
|
|
|
|
|
|
|
|
Another thing you could do is to enable the RAM test built-in application.
|
|
|
|
|
You can enable the NuttX RAM test that may be used to verify the external
|
|
|
|
|
SDRAM. To do this, keep the SDRAM out of the heap so that it can be tested
|
|
|
|
|
without crashing programs using the memory:
|
|
|
|
|
|
|
|
|
|
System Type->Heap Configuration
|
|
|
|
|
CONFIG_SAMA5_DDRCS_HEAP=n : Don't add the SDRAM to the heap
|
|
|
|
|
|
|
|
|
|
Memory Management
|
|
|
|
|
CONFIG_MM_REGIONS=1 : One memory regions: ISRAM
|
|
|
|
|
|
|
|
|
|
Then enable the RAM test built-in application:
|
|
|
|
|
|
|
|
|
|
Application Configuration->System NSH Add-Ons->Ram Test
|
|
|
|
|
CONFIG_SYSTEM_RAMTEST=y
|
|
|
|
|
|
|
|
|
|
In this configuration, the SDRAM is not added to heap and so is not
|
|
|
|
|
accessable to the applications. So the RAM test can be freely executed
|
|
|
|
|
against the SRAM memory beginning at address 0x2000:0000 (DDR CS):
|
|
|
|
|
|
|
|
|
|
nsh> ramtest -h
|
|
|
|
|
Usage: <noname> [-w|h|b] <hex-address> <decimal-size>
|
|
|
|
|
|
|
|
|
|
Where:
|
|
|
|
|
<hex-address> starting address of the test.
|
|
|
|
|
<decimal-size> number of memory locations (in bytes).
|
|
|
|
|
-w Sets the width of a memory location to 32-bits.
|
|
|
|
|
-h Sets the width of a memory location to 16-bits (default).
|
|
|
|
|
-b Sets the width of a memory location to 8-bits.
|
|
|
|
|
|
|
|
|
|
To test the entire external 256MB SRAM:
|
|
|
|
|
|
|
|
|
|
nsh> ramtest -w 20000000 268435456
|
|
|
|
|
RAMTest: Marching ones: 20000000 268435456
|
|
|
|
|
RAMTest: Marching zeroes: 20000000 268435456
|
|
|
|
|
RAMTest: Pattern test: 20000000 268435456 55555555 aaaaaaaa
|
|
|
|
|
RAMTest: Pattern test: 20000000 268435456 66666666 99999999
|
|
|
|
|
RAMTest: Pattern test: 20000000 268435456 33333333 cccccccc
|
|
|
|
|
RAMTest: Address-in-address test: 20000000 268435456
|
|
|
|
|
|
|
|
|
|
SDRAM Data Configuration
|
|
|
|
|
------------------------
|
|
|
|
|
|
|
|
|
|
In these configurations, .data and .bss are retained in ISRAM by default.
|
|
|
|
|
.data and .bss can also be retained in SDRAM using these slightly
|
|
|
|
|
different configuration settings. In this configuration, ISRAM is
|
|
|
|
|
used only for the Cortex-A5 page table for the IDLE thread stack.
|
|
|
|
|
|
|
|
|
|
System Type->ATSAMA5 Peripheral Support
|
|
|
|
|
CONFIG_SAMA5_MPDDRC=y : Enable the DDR controller
|
|
|
|
|
|
|
|
|
|
System Type->External Memory Configuration
|
|
|
|
|
CONFIG_SAMA5_DDRCS=y : Tell the system that DRAM is at the DDR CS
|
|
|
|
|
CONFIG_SAMA5_DDRCS_SIZE=268435456 : 2Gb DRAM -> 256GB
|
|
|
|
|
CONFIG_SAMA5_DDRCS_LPDDR2=y : Its DDR2
|
|
|
|
|
CONFIG_SAMA5D4EK_MT47H128M16RT=y : This is the type of DDR2
|
|
|
|
|
|
|
|
|
|
System Type->Heap Configuration
|
|
|
|
|
CONFIG_SAMA5_ISRAM_HEAP=n : These do not apply in this case
|
|
|
|
|
CONFIG_SAMA5_DCRS_HEAP=n
|
|
|
|
|
|
|
|
|
|
System Type->Boot Memory Configuration
|
|
|
|
|
CONFIG_RAM_START=0x20000000 : Physical address of SDRAM
|
|
|
|
|
CONFIG_RAM_VSTART=0x20000000 : Virtual address of SDRAM
|
|
|
|
|
CONFIG_RAM_SIZE=268435456 : Size of SDRAM
|
|
|
|
|
CONFIG_BOOT_SDRAM_DATA=y : Data is in SDRAM
|
|
|
|
|
|
|
|
|
|
Care must be used applied these RAM locations; graphics
|
|
|
|
|
configurations may use SDRAM in an incompatible way to set aside
|
|
|
|
|
LCD framebuffers.
|
|
|
|
|
|
|
|
|
|
Memory Management
|
|
|
|
|
CONFIG_MM_REGIONS=1 : One heap memory region: ISDRAM
|
|
|
|
|
|
|
|
|
|
NAND Support
|
|
|
|
|
============
|
|
|
|
|
|
|
|
|
|
NAND support is only partial in that there is no file system that works
|
|
|
|
|
with it properly. Lower-level NAND support has been developed and
|
|
|
|
|
verified, but there is no way to use it in the current NuttX architecture
|
|
|
|
|
other than through the raw MTD interface.
|
|
|
|
|
|
|
|
|
|
NAND should still be considered a work in progress. You will not want to
|
|
|
|
|
use NAND unless you are interested in investing a little effort,
|
|
|
|
|
particularly in infrastructure. See the "STATUS SUMMARY" section below.
|
|
|
|
|
|
|
|
|
|
NAND Support
|
|
|
|
|
------------
|
|
|
|
|
|
|
|
|
|
NAND Support can be added to the NSH configuration by modifying the
|
|
|
|
|
NuttX configuration file as follows:
|
|
|
|
|
|
|
|
|
|
Build Setup
|
|
|
|
|
CONFIG_EXPERIMENTAL=y : NXFFS implementation is incomplete and
|
|
|
|
|
: not yet fully functional.
|
|
|
|
|
|
|
|
|
|
System Type -> SAMA5 Peripheral support
|
|
|
|
|
CONFIG_SAMA5_HSMC=y : Make sure that the SMC is enabled
|
|
|
|
|
|
|
|
|
|
Drivers -> Memory Technology Device (MTD) Support
|
|
|
|
|
CONFIG_MTD=y : Enable MTD support
|
|
|
|
|
CONFIG_MTD_NAND=y : Enable NAND support
|
|
|
|
|
CONFIG_MTD_NAND_BLOCKCHECK=n : Interferes with NXFFS bad block checking
|
|
|
|
|
CONFIG_MTD_NAND_SWECC=y : Use S/W ECC calculation
|
|
|
|
|
|
|
|
|
|
Defaults for all other NAND settings should be okay
|
|
|
|
|
|
|
|
|
|
System Type -> External Memory Configuration
|
|
|
|
|
CONFIG_SAMA5_EBICS3=y : Enable External CS3 memory
|
|
|
|
|
CONFIG_SAMA5_EBICS3_NAND=y : Select NAND memory type
|
|
|
|
|
CONFIG_SAMA5_EBICS3_SIZE=8388608 : Use this size
|
|
|
|
|
CONFIG_SAMA5_EBICS3_SWECC=y : Use S/W ECC calculation
|
|
|
|
|
|
|
|
|
|
Defaults for ROM page table addresses should be okay
|
|
|
|
|
|
|
|
|
|
Application Configuration -> NSH Library
|
|
|
|
|
CONFIG_NSH_ARCHINIT=y : Use architecture-specific initialization
|
|
|
|
|
|
|
|
|
|
NOTES:
|
|
|
|
|
|
|
|
|
|
1. WARNING: This will wipe out everything that you may have on the NAND
|
|
|
|
|
FLASH! I have found that using the JTAG with no valid image on NAND
|
|
|
|
|
or Serial FLASH is a problem: In that case, the code always ends up
|
|
|
|
|
in the SAM-BA bootloader.
|
|
|
|
|
|
|
|
|
|
My understanding is that you can enable JTAG in this case by simply
|
|
|
|
|
entering any data on the DBG serial port. I have not tried this.
|
|
|
|
|
Instead, I just changed to boot from Serial Flash:
|
|
|
|
|
|
|
|
|
|
2. Unfortunately, there are no appropriate NAND file system in NuttX as
|
|
|
|
|
of this writing. The following sections discussion issues/problems
|
|
|
|
|
with using NXFFS and FAT.
|
|
|
|
|
|
|
|
|
|
PMECC
|
|
|
|
|
-----
|
|
|
|
|
|
|
|
|
|
Hardware ECC calculation using the SAMA5D4's PMECC can be enable as
|
|
|
|
|
follows:
|
|
|
|
|
|
|
|
|
|
Drivers -> Memory Technology Device (MTD) Support
|
|
|
|
|
CONFIG_MTD_NAND_SWECC=y : Don't use S/W ECC calculation
|
|
|
|
|
CONFIG_MTD_NAND_HWECC=y : Use H/W ECC instead
|
|
|
|
|
|
|
|
|
|
System Type -> External Memory Configuration
|
|
|
|
|
CONFIG_SAMA5_EBICS3_SWECC=n : Don't use S/W ECC calculation
|
|
|
|
|
CONFIG_SAMA5_HAVE_PMECC=n : Use H/W ECC instead
|
|
|
|
|
|
|
|
|
|
Other PMECC-related default settings should be okay.
|
|
|
|
|
|
|
|
|
|
STATUS: As of the writing, NAND transfers using PMECC appear to
|
|
|
|
|
work correctly. However, the PMECC based systems do not work as
|
|
|
|
|
as well with FAT or NXFFS. My belief that that the FAT/NXFFS layers
|
|
|
|
|
are inappropriate for NAND and, as a result, happen not to work with
|
|
|
|
|
the PMECC ECC calculation. See also the "STATUS SUMMARY" section below.
|
|
|
|
|
|
|
|
|
|
DMA Support
|
|
|
|
|
-----------
|
|
|
|
|
|
|
|
|
|
DMA support can be enabled as follows:
|
|
|
|
|
|
|
|
|
|
System Type -> SAMA5 Peripheral support
|
|
|
|
|
CONFIG_SAMA5_DMAC0=y : Use DMAC0 for memory-to-memory DMA
|
|
|
|
|
|
|
|
|
|
System Type -> External Memory Configuration
|
|
|
|
|
CONFIG_SAMA5_NAND_DMA=y : Use DMAC0 for NAND data transfers
|
|
|
|
|
|
|
|
|
|
STATUS: DMA appears to be functional, but probably has not been
|
|
|
|
|
exercised enough to claim that with any certainty. See also the "STATUS
|
|
|
|
|
SUMMARY" section below.
|
|
|
|
|
|
|
|
|
|
NXFFS
|
|
|
|
|
-----
|
|
|
|
|
|
|
|
|
|
The NuttX FLASH File System (NXFFS) works well with NOR-like FLASH
|
|
|
|
|
but does not work well with NAND (See comments below under STATUS)
|
|
|
|
|
|
|
|
|
|
File Systems:
|
|
|
|
|
CONFIG_FS_NXFFS=y : Enable the NXFFS file system
|
|
|
|
|
|
|
|
|
|
Defaults for all other NXFFS settings should be okay.
|
|
|
|
|
|
|
|
|
|
NOTE: NXFFS will require some significant buffering because of
|
|
|
|
|
the large size of the NAND flash blocks. You will also need
|
|
|
|
|
to enable SDRAM as described above.
|
|
|
|
|
|
|
|
|
|
Board Selection
|
|
|
|
|
CONFIG_SAMA5D4EK_NAND_AUTOMOUNT=y : Enable FS support on NAND
|
|
|
|
|
CONFIG_SAMA5D4EK_NAND_NXFFS=y : Use the NXFFS file system
|
|
|
|
|
|
|
|
|
|
Other file systems are not recommended because only NXFFS can handle
|
|
|
|
|
bad blocks and only NXFFS performs wear-levelling.
|
|
|
|
|
|
|
|
|
|
FAT
|
|
|
|
|
---
|
|
|
|
|
|
|
|
|
|
Another option is FAT. FAT, however, is not appropriate for use with
|
|
|
|
|
NAND: FAT will not handle bad blocks, does not perform any wear
|
|
|
|
|
levelling, and may not conform to writing ordering requirements of NAND.
|
|
|
|
|
Also, there appear to be issues with FAT when PMECC is enabled (see
|
|
|
|
|
"STATUS SUMMARY" below).
|
|
|
|
|
|
|
|
|
|
File Systems:
|
|
|
|
|
CONFIG_FS_FAT=y : Enable the FAT FS
|
|
|
|
|
CONFIG_FAT_LCNAMES=y : With lower case name support
|
|
|
|
|
CONFIG_FAT_LFN=y : And (patented) FAT long file name support
|
|
|
|
|
CONFIG_FS_NXFFS=n : Don't need NXFFS
|
|
|
|
|
|
|
|
|
|
Defaults for all other NXFFS settings should be okay.
|
|
|
|
|
|
|
|
|
|
Board Selection
|
|
|
|
|
CONFIG_SAMA5D4EK_NAND_AUTOMOUNT=y : Enable FS support on NAND
|
|
|
|
|
CONFIG_SAMA5D4EK_NAND_FTL=y : Use an flash translation layer
|
|
|
|
|
|
|
|
|
|
NOTE: FTL will require some significant buffering because of
|
|
|
|
|
the large size of the NAND flash blocks. You will also need
|
|
|
|
|
to enable SDRAM as described above.
|
|
|
|
|
|
|
|
|
|
SMART FS
|
|
|
|
|
--------
|
|
|
|
|
|
|
|
|
|
Another option is Smart FS. Smart FS is another small file system
|
|
|
|
|
designed to work with FLASH. Properties: It does support some wear-
|
|
|
|
|
leveling like NXFFS, but like FAT, cannot handle bad blocks and like
|
|
|
|
|
NXFFS, it will try to re-write erased bits.
|
|
|
|
|
|
|
|
|
|
Using NAND with NXFFS
|
|
|
|
|
---------------------
|
|
|
|
|
|
|
|
|
|
With the options CONFIG_SAMA5D4EK_NAND_AUTOMOUNT=y and
|
|
|
|
|
CONFIG_SAMA5D4EK_NAND_NXFFS=y, the NAND FLASH will be mounted in the NSH
|
|
|
|
|
start-up logic before the NSH prompt appears. There is no feedback as
|
|
|
|
|
to whether or not the mount was successful. You can, however, see the
|
|
|
|
|
mounted file systems using the nsh 'mount' command:
|
|
|
|
|
|
|
|
|
|
nsh> mount
|
|
|
|
|
/mnt/nand type nxffs
|
|
|
|
|
|
|
|
|
|
Then NAND can be used like any other file system:
|
|
|
|
|
|
|
|
|
|
nsh> echo "This is a test" >/mnt/nand/atest.txt
|
|
|
|
|
nsh> ls -l /mnt/nand
|
|
|
|
|
/mnt/nand:
|
|
|
|
|
---x--x--x 16 atest.txt
|
|
|
|
|
nsh> cat /mnt/nand/atest.txt
|
|
|
|
|
This is a test
|
|
|
|
|
|
|
|
|
|
The NAND volume can be un-mounted with this comment:
|
|
|
|
|
|
|
|
|
|
nsh> umount /mnt/nand
|
|
|
|
|
nsh> mount
|
|
|
|
|
|
|
|
|
|
And re-mounted with this command:
|
|
|
|
|
|
|
|
|
|
nsh> mount -t nxffs /mnt/mystuff
|
|
|
|
|
nsh> mount
|
|
|
|
|
/mnt/mystuff type nxffs
|
|
|
|
|
|
|
|
|
|
NOTES:
|
|
|
|
|
1. NXFFS can be very slow. The first time that you start the system,
|
|
|
|
|
be prepared for a wait; NXFFS will need to format the NAND volume.
|
|
|
|
|
I have lots of debug on so I don't yet know what the optimized wait
|
|
|
|
|
will be. But with debug ON, software ECC, and no DMA the wait is
|
|
|
|
|
in many tens of minutes (and substantially longer if many debug
|
|
|
|
|
options are enabled.
|
|
|
|
|
|
|
|
|
|
[I don't yet have data for the more optimal cases. It will be
|
|
|
|
|
significantly less, but still not fast.]
|
|
|
|
|
|
|
|
|
|
2. On subsequent boots, after the NXFFS file system has been created
|
|
|
|
|
the delay will be less. When the new file system is empty, it will
|
|
|
|
|
be very fast. But the NAND-related boot time can become substantial
|
|
|
|
|
when there has been a lot of usage of the NAND. This is because
|
|
|
|
|
NXFFS needs to scan the NAND device and build the in-memory dataset
|
|
|
|
|
needed to access NAND and there is more that must be scanned after
|
|
|
|
|
the device has been used. You may want to create a separate thread at
|
|
|
|
|
boot time to bring up NXFFS so that you don't delay the boot-to-prompt
|
|
|
|
|
time excessively in these longer delay cases.
|
|
|
|
|
|
|
|
|
|
3. There is another NXFFS related performance issue: When the FLASH
|
|
|
|
|
is fully used, NXFFS will restructure the entire FLASH, the delay
|
|
|
|
|
to restructure the entire FLASH will probably be even larger. This
|
|
|
|
|
solution in this case is to implement an NXFSS clean-up daemon that
|
|
|
|
|
does the job a little-at-a-time so that there is no massive clean-up
|
|
|
|
|
when the FLASH becomes full.
|
|
|
|
|
|
|
|
|
|
4. Bad NXFFS behavior with NAND: If you restart NuttX, the files that
|
|
|
|
|
you wrote to NAND will be gone. Why? Because the multiple writes
|
|
|
|
|
have corrupted the NAND ECC bits. See STATUS below. NXFFS would
|
|
|
|
|
require a major overhaul to be usable with NAND.
|
|
|
|
|
|
|
|
|
|
Using NAND with FAT
|
|
|
|
|
-------------------
|
|
|
|
|
|
|
|
|
|
If configured for FAT, the system will create block driver at
|
|
|
|
|
/dev/mtdblock0:
|
|
|
|
|
|
|
|
|
|
NuttShell (NSH)
|
|
|
|
|
nsh> ls /dev
|
|
|
|
|
/dev:
|
|
|
|
|
console
|
|
|
|
|
mtdblock0
|
|
|
|
|
null
|
|
|
|
|
ttyS0
|
|
|
|
|
|
|
|
|
|
You will not that the system comes up immediately because there is not
|
|
|
|
|
need to scan the volume in this case..
|
|
|
|
|
|
|
|
|
|
The NSH 'mkfatfs' command can be used to format a FAT file system on
|
|
|
|
|
NAND.
|
|
|
|
|
|
|
|
|
|
nsh> mkfatfs /dev/mtdblock0
|
|
|
|
|
|
|
|
|
|
This step, on the other hand, requires quite a bit of time.
|
|
|
|
|
|
|
|
|
|
And the FAT file system can be mounted like:
|
|
|
|
|
|
|
|
|
|
nsh> mount -t vfat /dev/mtdblock0 /mnt/nand
|
|
|
|
|
nsh> ls /mnt/nand
|
|
|
|
|
/mnt/nand:
|
|
|
|
|
|
|
|
|
|
nsh> echo "This is a test" > /mnt/nand/atest.txt
|
|
|
|
|
|
|
|
|
|
NOTE: This will take a long time because it will require reading,
|
|
|
|
|
modifying, and re-writing the 128KB erase page!
|
|
|
|
|
|
|
|
|
|
nsh> ls -l /mnt/nand
|
|
|
|
|
/mnt/nand:
|
|
|
|
|
-rw-rw-rw- 16 atest.txt
|
|
|
|
|
|
|
|
|
|
nsh> cat /mnt/fat/atest.txt
|
|
|
|
|
This is a test
|
|
|
|
|
|
|
|
|
|
NOTES:
|
|
|
|
|
|
|
|
|
|
1. Unlike NXFFS, FAT can work with NAND (at least with PMECC disabled).
|
|
|
|
|
But there are some significant issues.
|
|
|
|
|
|
|
|
|
|
2. First, each NAND write access will cause a 256KB data transfer: It
|
|
|
|
|
will read the entire 128KB erase block, modify it and write it back
|
|
|
|
|
to memory. There is some caching logic so that this cached erase
|
|
|
|
|
block can be re-used if possible and writes will be deferred as long
|
|
|
|
|
as possible.
|
|
|
|
|
|
|
|
|
|
3. If you hit a bad block, then FAT is finished. There is no mechanism
|
|
|
|
|
in place in FAT not to mark and skip over bad blocks.
|
|
|
|
|
|
|
|
|
|
What is Needed
|
|
|
|
|
--------------
|
|
|
|
|
|
|
|
|
|
What is needed to work with FAT properly would be another MTD layer
|
|
|
|
|
between the FTL layer and the NAND FLASH layer. That layer would
|
|
|
|
|
perform bad block detection and sparing so that FAT works transparently
|
|
|
|
|
on top of the NAND.
|
|
|
|
|
|
|
|
|
|
Another, less general, option would be support bad blocks within FAT.
|
|
|
|
|
|
|
|
|
|
STATUS SUMMARY
|
|
|
|
|
--------------
|
|
|
|
|
|
|
|
|
|
1. PMECC appears to be working in that I can write a NAND block with its
|
|
|
|
|
ECC and read the block back and verify that that is are no bit
|
|
|
|
|
failures. However, when attempting to work with FAT, it does not
|
|
|
|
|
work correctly: The MBR is written and read back correctly, but gets
|
|
|
|
|
corrupted later for unknown reasons.
|
|
|
|
|
|
|
|
|
|
2. DMA works (at least with software ECC), but I have seen occasional
|
|
|
|
|
failures. I recommend enabling DMA with caution.
|
|
|
|
|
|
|
|
|
|
In NuttX, DMA will also cost two context switches (and, hence, four
|
|
|
|
|
register state transfers). With smaller NAND page sizes (say 2KiB and
|
|
|
|
|
below), I would expect little or no performance improvement with DMA
|
|
|
|
|
for this reason.
|
|
|
|
|
|
|
|
|
|
3. NXFFS does not work with NAND. NAND differs from other other FLASH
|
|
|
|
|
types several ways. For one thing, NAND requires error correction
|
|
|
|
|
(ECC) bytes that must be set in order to work around bit failures.
|
|
|
|
|
This affects NXFFS in two ways:
|
|
|
|
|
|
|
|
|
|
a. First, write failures are not fatal. Rather, they should be tried by
|
|
|
|
|
bad blocks and simply ignored. This is because unrecoverable bit
|
|
|
|
|
failures will cause read failures when reading from NAND. Setting
|
|
|
|
|
the CONFIG_EXPERIMENTAL+CONFIG_NXFFS_NANDs option will enable this
|
|
|
|
|
behavior.
|
|
|
|
|
|
|
|
|
|
b. Secondly, NXFFS will write a block many times. It tries to keep
|
|
|
|
|
bits in the erased state and assumes that it can overwrite those bits
|
|
|
|
|
to change them from the erased to the non-erased state. This works
|
|
|
|
|
will with NOR-like FLASH. NAND behaves this way too. But the
|
|
|
|
|
problem with NAND is that the ECC bits cannot be re-written in this
|
|
|
|
|
way. So once a block has been written, it cannot be modified. This
|
|
|
|
|
behavior has NOT been fixed in NXFFS. Currently, NXFFS will attempt
|
|
|
|
|
to re-write the ECC bits causing the ECC to become corrupted because
|
|
|
|
|
the ECC bits cannot be overwritten without erasing the entire block.
|
|
|
|
|
|
|
|
|
|
This may prohibit NXFFS from ever being used with NAND.
|
|
|
|
|
|
|
|
|
|
4. As mentioned above, FAT does work but (1) has some performance issues on
|
|
|
|
|
writes and (2) cannot handle bad blocks.
|
|
|
|
|
|
|
|
|
|
I2C Tool
|
|
|
|
|
========
|
|
|
|
|
|
|
|
|
|
I2C Tool. NuttX supports an I2C tool at apps/system/i2c that can be used
|
|
|
|
|
to peek and poke I2C devices. That tool can be enabled by setting the
|
|
|
|
|
following:
|
|
|
|
|
|
|
|
|
|
System Type -> SAMA5 Peripheral Support
|
|
|
|
|
CONFIG_SAMA5_TWI0=y : Enable TWI0
|
|
|
|
|
CONFIG_SAMA5_TWI1=y : Enable TWI1
|
|
|
|
|
CONFIG_SAMA5_TWI2=y : Enable TWI2
|
|
|
|
|
|
|
|
|
|
System Type -> TWI device driver options
|
|
|
|
|
SAMA5_TWI0_FREQUENCY=100000 : Select a TWI0 frequency
|
|
|
|
|
SAMA5_TWI1_FREQUENCY=100000 : Select a TWI1 frequency
|
|
|
|
|
SAMA5_TWI2_FREQUENCY=100000 : Select a TWI2 frequency
|
|
|
|
|
|
|
|
|
|
Device Drivers -> I2C Driver Support
|
|
|
|
|
CONFIG_I2C=y : Enable I2C support
|
|
|
|
|
CONFIG_I2C_TRANSFER=y : Driver supports the transfer() method
|
|
|
|
|
CONFIG_I2C_WRITEREAD=y : Driver supports the writeread() method
|
|
|
|
|
|
|
|
|
|
Application Configuration -> NSH Library
|
|
|
|
|
CONFIG_SYSTEM_I2CTOOL=y : Enable the I2C tool
|
|
|
|
|
CONFIG_I2CTOOL_MINBUS=0 : TWI0 has the minimum bus number 0
|
|
|
|
|
CONFIG_I2CTOOL_MAXBUS=2 : TWI2 has the maximum bus number 2
|
|
|
|
|
CONFIG_I2CTOOL_DEFFREQ=100000 : Pick a consistent frequency
|
|
|
|
|
|
|
|
|
|
The I2C tool has extensive help that can be accessed as follows:
|
|
|
|
|
|
|
|
|
|
nsh> i2c help
|
|
|
|
|
Usage: i2c <cmd> [arguments]
|
|
|
|
|
Where <cmd> is one of:
|
|
|
|
|
|
|
|
|
|
Show help : ?
|
|
|
|
|
List busses : bus
|
|
|
|
|
List devices : dev [OPTIONS] <first> <last>
|
|
|
|
|
Read register : get [OPTIONS] [<repititions>]
|
|
|
|
|
Show help : help
|
|
|
|
|
Write register: set [OPTIONS] <value> [<repititions>]
|
|
|
|
|
Verify access : verf [OPTIONS] [<value>] [<repititions>]
|
|
|
|
|
|
|
|
|
|
Where common "sticky" OPTIONS include:
|
|
|
|
|
[-a addr] is the I2C device address (hex). Default: 03 Current: 03
|
|
|
|
|
[-b bus] is the I2C bus number (decimal). Default: 0 Current: 0
|
|
|
|
|
[-r regaddr] is the I2C device register address (hex). Default: 00 Current: 00
|
|
|
|
|
[-w width] is the data width (8 or 16 decimal). Default: 8 Current: 8
|
|
|
|
|
[-s|n], send/don't send start between command and data. Default: -n Current: -n
|
|
|
|
|
[-i|j], Auto increment|don't increment regaddr on repititions. Default: NO Current: NO
|
|
|
|
|
[-f freq] I2C frequency. Default: 100000 Current: 100000
|
|
|
|
|
|
|
|
|
|
NOTES:
|
|
|
|
|
o Arguments are "sticky". For example, once the I2C address is
|
|
|
|
|
specified, that address will be re-used until it is changed.
|
|
|
|
|
|
|
|
|
|
WARNING:
|
|
|
|
|
o The I2C dev command may have bad side effects on your I2C devices.
|
|
|
|
|
Use only at your own risk.
|
|
|
|
|
|
|
|
|
|
As an example, the I2C dev comman can be used to list all devices
|
|
|
|
|
responding on TWI0 (the default) like this:
|
|
|
|
|
|
|
|
|
|
nsh> i2c dev 0x03 0x77
|
|
|
|
|
0 1 2 3 4 5 6 7 8 9 a b c d e f
|
|
|
|
|
00: -- -- -- -- -- -- -- -- -- -- -- -- --
|
|
|
|
|
10: -- -- -- -- -- -- -- -- -- -- 1a -- -- -- -- --
|
|
|
|
|
20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
|
|
|
|
|
30: -- -- -- -- -- -- -- -- -- 39 -- -- -- 3d -- --
|
|
|
|
|
40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
|
|
|
|
|
50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
|
|
|
|
|
60: 60 -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
|
|
|
|
|
70: -- -- -- -- -- -- -- --
|
|
|
|
|
nsh>
|
|
|
|
|
|
|
|
|
|
Address 0x1a is the WM8904. Address 0x39 is the SIL9022A. I am not sure
|
|
|
|
|
what is at address 0x3d and 0x60
|
|
|
|
|
|
|
|
|
|
SAMA5 ADC Support
|
|
|
|
|
=================
|
|
|
|
|
|
|
|
|
|
Basic driver configuration
|
|
|
|
|
--------------------------
|
|
|
|
|
ADC support can be added to the NSH configuration. However, there are no
|
|
|
|
|
ADC input pins available to the user for ADC testing (the touchscreen ADC
|
|
|
|
|
inputs are intended for other functionality). Because of this, there is
|
|
|
|
|
not much motivation to enable ADC support on the SAMA4D4-EK. This
|
|
|
|
|
paragraph is included here, however, for people using a custom SAMA5D4x
|
|
|
|
|
board that requires ADC support.
|
|
|
|
|
|
|
|
|
|
System Type -> SAMA5 Peripheral Support
|
|
|
|
|
CONFIG_SAMA5_ADC=y : Enable ADC driver support
|
|
|
|
|
CONFIG_SAMA5_TC0=y : Enable the Timer/counter library need for periodic sampling
|
|
|
|
|
|
|
|
|
|
Drivers
|
|
|
|
|
CONFIG_ANALOG=y : Should be automatically selected
|
|
|
|
|
CONFIG_ADC=y : Should be automatically selected
|
|
|
|
|
|
|
|
|
|
System Type -> ADC Configuration
|
|
|
|
|
CONFIG_SAMA5_ADC_CHAN0=y : These settings enable the sequencer to collect
|
|
|
|
|
CONFIG_SAMA5_ADC_CHAN1=y : Samples from ADC channels 0-3 on each trigger
|
|
|
|
|
CONFIG_SAMA5_ADC_CHAN2=y
|
|
|
|
|
CONFIG_SAMA5_ADC_CHAN3=y
|
|
|
|
|
CONFIG_SAMA5_ADC_SEQUENCER=y
|
|
|
|
|
|
|
|
|
|
CONFIG_SAMA5_ADC_TIOA0TRIG=y : Trigger on the TC0, channel 0 output A
|
|
|
|
|
CONFIG_SAMA5_ADC_TIOAFREQ=2 : At a frequency of 2Hz
|
|
|
|
|
CONFIG_SAMA5_ADC_TIOA_RISING=y : Trigger on the rising edge
|
|
|
|
|
|
|
|
|
|
Default ADC settings (like gain and offset) may also be set if desired.
|
|
|
|
|
|
|
|
|
|
System Type -> Timer/counter Configuration
|
|
|
|
|
CONFIG_SAMA5_TC0_TIOA0=y : Should be automatically selected
|
|
|
|
|
|
|
|
|
|
Work queue supported is also needed:
|
|
|
|
|
|
|
|
|
|
Library routines
|
|
|
|
|
CONFIG_SCHED_WORKQUEUE=y
|
|
|
|
|
|
|
|
|
|
ADC Test Example
|
|
|
|
|
----------------
|
|
|
|
|
For testing purposes, there is an ADC program at apps/examples/adc that
|
|
|
|
|
will collect a specified number of samples. This test program can be
|
|
|
|
|
enabled as follows:
|
|
|
|
|
|
|
|
|
|
Application Configuration -> Examples -> ADC example
|
|
|
|
|
CONFIG_EXAMPLES_ADC=y : Enables the example code
|
|
|
|
|
CONFIG_EXAMPLES_ADC_DEVPATH="/dev/adc0"
|
|
|
|
|
|
|
|
|
|
Other default settings for the ADC example should be okay.
|
|
|
|
|
|
|
|
|
|
ADC DMA Support
|
|
|
|
|
---------------
|
|
|
|
|
At 2Hz, DMA is not necessary nor desire-able. The ADC driver has support
|
|
|
|
|
for DMA transfers of converted data (although that support has not been
|
|
|
|
|
tested as of this writing). DMA support can be added by include the
|
|
|
|
|
following in the configuration.
|
|
|
|
|
|
|
|
|
|
System Type -> SAMA5 Peripheral Support
|
|
|
|
|
CONFIG_SAMA5_DMAC1=y : Enable DMAC1 support
|
|
|
|
|
|
|
|
|
|
System Type -> ADC Configuration
|
|
|
|
|
CONFIG_SAMA5_ADC_DMA=y : Enable ADC DMA transfers
|
|
|
|
|
CONFIG_SAMA5_ADC_DMASAMPLES=2 : Collect two sets of samples per DMA
|
|
|
|
|
|
|
|
|
|
Drivers -> Analog device (ADC/DAC) support
|
|
|
|
|
CONFIG_ADC_FIFOSIZE=16 : Driver may need a large ring buffer
|
|
|
|
|
|
|
|
|
|
Application Configuration -> Examples -> ADC example
|
|
|
|
|
CONFIG_EXAMPLES_ADC_GROUPSIZE=16 : Larger buffers in the test
|
|
|
|
|
|
|
|
|
|
SAMA5 PWM Support
|
|
|
|
|
=================
|
|
|
|
|
|
|
|
|
|
Basic driver configuration
|
|
|
|
|
--------------------------
|
|
|
|
|
PWM support can be added to the NSH configuration. However, there are no
|
|
|
|
|
PWM output pins available to the user for PWM testing. Because of this,
|
|
|
|
|
there is not much motivation to enable PWM support on the SAMA4D4-EK. This
|
|
|
|
|
paragraph is included here, however, for people using a custom SAMA5D4x
|
|
|
|
|
board that requires PWM support.
|
|
|
|
|
|
|
|
|
|
Basic driver configuration:
|
|
|
|
|
|
|
|
|
|
System Type -> SAMA5 Peripheral Support
|
|
|
|
|
CONFIG_SAMA5_PWM=y : Enable PWM driver support
|
|
|
|
|
|
|
|
|
|
Drivers
|
|
|
|
|
CONFIG_PWM=y : Should be automatically selected
|
|
|
|
|
|
|
|
|
|
PWM Channel/Output Selection
|
|
|
|
|
----------------------------
|
|
|
|
|
In order to use the PWM, you must enable one or more PWM Channels:
|
|
|
|
|
|
|
|
|
|
System Type -> PWM Configuration
|
|
|
|
|
CONFIG_SAMA5_PWM_CHAN0=y : Enable one or more of channels 0-3
|
|
|
|
|
CONFIG_SAMA5_PWM_CHAN1=y
|
|
|
|
|
CONFIG_SAMA5_PWM_CHAN2=y
|
|
|
|
|
CONFIG_SAMA5_PWM_CHAN3=y
|
|
|
|
|
|
|
|
|
|
For each channel that is enabled, you must also specify the output pins
|
|
|
|
|
to be enabled and the clocking supplied to the PWM channel.
|
|
|
|
|
|
|
|
|
|
CONFIG_SAMA5_PWM_CHANx_FAULTINPUT=n : (not used currently)
|
|
|
|
|
CONFIG_SAMA5_PWM_CHANx_OUTPUTH=y : Enable One of both of the H and L output pins
|
|
|
|
|
CONFIG_SAMA5_PWM_CHANx_OUTPUTL=y
|
|
|
|
|
|
|
|
|
|
Where x=0..3.
|
|
|
|
|
|
|
|
|
|
Care must be taken because all PWM output pins conflict with some other
|
|
|
|
|
usage of the pin by other devices. Furthermore, many of these pins have
|
|
|
|
|
not been brought out to an external connector:
|
|
|
|
|
|
|
|
|
|
-----+---+---+----+------+----------------
|
|
|
|
|
PWM PIN PER PIO I/O CONFLICTS
|
|
|
|
|
-----+---+---+----+------+----------------
|
|
|
|
|
PWM0 FI B PC28 J2.30 SPI1, ISI
|
|
|
|
|
H B PB0 --- GMAC
|
|
|
|
|
B PA20 J1.14 LCDC, ISI
|
|
|
|
|
L B PB1 --- GMAC
|
|
|
|
|
B PA21 J1.16 LCDC, ISI
|
|
|
|
|
-----+---+---+----+------+----------------
|
|
|
|
|
PWM1 FI B PC31 J2.36 HDMI
|
|
|
|
|
H B PB4 --- GMAC
|
|
|
|
|
B PA22 J1.18 LCDC, ISI
|
|
|
|
|
L B PB5 --- GMAC
|
|
|
|
|
B PE31 J3.20 ISI, HDMI
|
|
|
|
|
B PA23 J1.20 LCDC, ISI
|
|
|
|
|
-----+---+---+----+------+----------------
|
|
|
|
|
PWM2 FI B PC29 J2.29 UART0, ISI, HDMI
|
|
|
|
|
H C PD5 --- HSMCI0
|
|
|
|
|
B PB8 --- GMAC
|
|
|
|
|
L C PD6 --- HSMCI0
|
|
|
|
|
B PB9 --- GMAC
|
|
|
|
|
-----+---+---+----+------+----------------
|
|
|
|
|
PWM3 FI C PD16 --- SPI0, Audio
|
|
|
|
|
H C PD7 --- HSMCI0
|
|
|
|
|
B PB12 J3.7 GMAC
|
|
|
|
|
L C PD8 --- HSMCI0
|
|
|
|
|
B PB13 --- GMAC
|
|
|
|
|
-----+---+---+----+--------------------
|
|
|
|
|
|
|
|
|
|
See configs/sama5d4-ek/include/board.h for all of the default PWM
|
|
|
|
|
pin selections. I used PWM channel 0, pins PA20 and PA21 for testing.
|
|
|
|
|
|
|
|
|
|
Clocking is addressed in the next paragraph.
|
|
|
|
|
|
|
|
|
|
PWM Clock Configuration
|
|
|
|
|
-----------------------
|
|
|
|
|
PWM Channels can be clocked from either a coarsely divided divided down
|
|
|
|
|
MCK or from a custom frequency from PWM CLKA and/or CLKB. If you want
|
|
|
|
|
to use CLKA or CLKB, you must enable and configure them.
|
|
|
|
|
|
|
|
|
|
System Type -> PWM Configuration
|
|
|
|
|
CONFIG_SAMA5_PWM_CLKA=y
|
|
|
|
|
CONFIG_SAMA5_PWM_CLKA_FREQUENCY=3300
|
|
|
|
|
CONFIG_SAMA5_PWM_CLKB=y
|
|
|
|
|
CONFIG_SAMA5_PWM_CLKB_FREQUENCY=3300
|
|
|
|
|
|
|
|
|
|
Then for each of the enabled, channels you must select the input clock
|
|
|
|
|
for that channel:
|
|
|
|
|
|
|
|
|
|
System Type -> PWM Configuration
|
|
|
|
|
CONFIG_SAMA5_PWM_CHANx_CLKA=y : Pick one of MCK, CLKA, or CLKB (only)
|
|
|
|
|
CONFIG_SAMA5_PWM_CHANx_CLKB=y
|
|
|
|
|
CONFIG_SAMA5_PWM_CHANx_MCK=y
|
|
|
|
|
CONFIG_SAMA5_PWM_CHANx_MCKDIV=128 : If MCK is selected, then the MCK divider must
|
|
|
|
|
: also be provided (1,2,4,8,16,32,64,128,256,512, or 1024).
|
|
|
|
|
|
|
|
|
|
PWM Test Example
|
|
|
|
|
----------------
|
|
|
|
|
For testing purposes, there is an PWM program at apps/examples/pwm that
|
|
|
|
|
will collect a specified number of samples. This test program can be
|
|
|
|
|
enabled as follows:
|
|
|
|
|
|
|
|
|
|
Application Configuration -> Examples -> PWM example
|
|
|
|
|
CONFIG_EXAMPLES_PWM=y : Enables the example code
|
|
|
|
|
|
|
|
|
|
Other default settings for the PWM example should be okay.
|
|
|
|
|
|
|
|
|
|
CONFIG_EXAMPLES_PWM_DEVPATH="/dev/pwm0"
|
|
|
|
|
CONFIG_EXAMPLES_PWM_FREQUENCY=100
|
|
|
|
|
|
|
|
|
|
Usage of the example is straightforward:
|
|
|
|
|
|
|
|
|
|
nsh> pwm -h
|
|
|
|
|
Usage: pwm [OPTIONS]
|
|
|
|
|
|
|
|
|
|
Arguments are "sticky". For example, once the PWM frequency is
|
|
|
|
|
specified, that frequency will be re-used until it is changed.
|
|
|
|
|
|
|
|
|
|
"sticky" OPTIONS include:
|
|
|
|
|
[-p devpath] selects the PWM device. Default: /dev/pwm0 Current: /dev/pwm0
|
|
|
|
|
[-f frequency] selects the pulse frequency. Default: 100 Hz Current: 100 Hz
|
|
|
|
|
[-d duty] selects the pulse duty as a percentage. Default: 50 % Current: 50 %
|
|
|
|
|
[-t duration] is the duration of the pulse train in seconds. Default: 5 Current: 5
|
|
|
|
|
[-h] shows this message and exits
|
|
|
|
|
|
|
|
|
|
RTC
|
|
|
|
|
===
|
|
|
|
|
|
|
|
|
|
The Real Time Clock/Calendar RTC) may be enabled with these settings:
|
|
|
|
|
|
|
|
|
|
System Type:
|
|
|
|
|
CONFIG_SAMA5_RTC=y : Enable the RTC driver
|
|
|
|
|
|
|
|
|
|
Drivers (these values will be selected automatically):
|
|
|
|
|
CONFIG_RTC=y : Use the RTC for system time
|
|
|
|
|
CONFIG_RTC_DATETIME=y : RTC supports data/time
|
|
|
|
|
|
2014-06-29 15:40:37 +02:00
|
|
|
NOTE: If you want the RTC to preserve time over power cycles, you will
|
|
|
|
|
need to install a battery in the battery holder (J12) and close the jumper,
|
|
|
|
|
JP13.
|
|
|
|
|
|
|
|
|
|
You can set the RTC using the NSH date command:
|
|
|
|
|
|
|
|
|
|
NuttShell (NSH) NuttX-7.3
|
|
|
|
|
nsh> help date
|
|
|
|
|
date usage: date [-s "MMM DD HH:MM:SS YYYY"]
|
|
|
|
|
nsh> date
|
|
|
|
|
Jan 01 00:34:45 2012
|
|
|
|
|
nsh> date -s "JUN 29 7:30:00 2014"
|
|
|
|
|
nsh> date
|
|
|
|
|
Jun 29 07:30:01 2014
|
|
|
|
|
|
|
|
|
|
After a power cycle and reboot:
|
|
|
|
|
|
|
|
|
|
NuttShell (NSH) NuttX-7.3
|
|
|
|
|
nsh> date
|
|
|
|
|
Jun 29 07:30:55 2014
|
|
|
|
|
nsh>
|
|
|
|
|
|
|
|
|
|
The RTC also supports an alarm that may be enable with the following
|
|
|
|
|
settings. However, there is nothing in the system that currently makes
|
|
|
|
|
use of this alarm.
|
2014-06-06 20:37:36 +02:00
|
|
|
|
|
|
|
|
Drivers:
|
|
|
|
|
CONFIG_RTC_ALARM=y : Enable the RTC alarm
|
|
|
|
|
|
|
|
|
|
Library Routines
|
2014-06-29 15:40:37 +02:00
|
|
|
CONFIG_SCHED_WORKQUEUE=y : Alarm needs work queue support
|
2014-06-06 20:37:36 +02:00
|
|
|
|
|
|
|
|
Watchdog Timer
|
|
|
|
|
==============
|
|
|
|
|
|
|
|
|
|
NSH can be configured to exercise the watchdog timer test
|
|
|
|
|
(apps/examples/watchdog). This can be selected with the following
|
|
|
|
|
settings in the NuttX configuration file:
|
|
|
|
|
|
|
|
|
|
System Type:
|
|
|
|
|
CONFIG_SAMA5_WDT=y : Enable the WDT peripheral
|
2014-06-29 15:40:37 +02:00
|
|
|
: Defaults values for others settings
|
|
|
|
|
should be OK
|
2014-06-06 20:37:36 +02:00
|
|
|
|
|
|
|
|
Drivers (this will automatically be selected):
|
|
|
|
|
CONFIG_WATCHDOG=y : Enables watchdog timer driver support
|
|
|
|
|
|
|
|
|
|
Application Configuration -> Examples
|
|
|
|
|
CONFIG_EXAMPLES_WATCHDOG=y : Enable apps/examples/watchdog
|
|
|
|
|
|
|
|
|
|
The WDT timer is driven off the slow, 32768Hz clock divided by 128. As a
|
|
|
|
|
result, the watchdog a maximum timeout value of 16 seconds. The SAMA5 WDT
|
|
|
|
|
may also only be programmed one time; the processor must be reset before
|
|
|
|
|
the WDT can be reprogrammed.
|
|
|
|
|
|
|
|
|
|
The SAMA5 always boots with the watchdog timer enabled at its maximum
|
|
|
|
|
timeout (16 seconds). In the normal case where no watchdog timer driver
|
|
|
|
|
has been configured, the watchdog timer is disabled as part of the start
|
|
|
|
|
up logic. But, since we are permitted only one opportunity to program
|
|
|
|
|
the WDT, we cannot disable the watchdog time if CONFIG_SAMA5_WDT=y. So,
|
|
|
|
|
be forewarned: You have only 16 seconds to run your watchdog timer test!
|
|
|
|
|
|
2014-06-27 00:42:06 +02:00
|
|
|
NOTE: If you are using the dramboot program to run from DRAM as I did,
|
|
|
|
|
beware that the default version also disables the watchdog. You will
|
|
|
|
|
need a special version of dramboot with CONFIG_SAMA5_WDT=y.
|
|
|
|
|
|
2014-06-06 20:37:36 +02:00
|
|
|
TRNG and /dev/random
|
|
|
|
|
====================
|
|
|
|
|
|
|
|
|
|
NSH can be configured to enable the SAMA5 TRNG peripheral so that it
|
|
|
|
|
provides /dev/random. The following configuration will enable the TRNG,
|
2014-06-29 00:11:41 +02:00
|
|
|
and support for /dev/random:
|
2014-06-06 20:37:36 +02:00
|
|
|
|
|
|
|
|
System Type:
|
|
|
|
|
CONFIG_SAMA5_TRNG=y : Enable the TRNG peripheral
|
|
|
|
|
|
2014-06-29 00:11:41 +02:00
|
|
|
Drivers:
|
2014-06-06 20:37:36 +02:00
|
|
|
CONFIG_DEV_RANDOM=y : Enable /dev/random
|
|
|
|
|
|
2014-06-29 00:11:41 +02:00
|
|
|
A simple test of /dev/random is available at apps/examples/random and
|
|
|
|
|
can be enabled as a NSH application via the following additional
|
|
|
|
|
configuration settings:
|
|
|
|
|
|
2014-06-06 20:37:36 +02:00
|
|
|
Applications -> Examples
|
|
|
|
|
CONFIG_EXAMPLES_RANDOM=y : Enable apps/examples/random
|
|
|
|
|
CONFIG_EXAMPLES_MAXSAMPLES=64 : Default settings are probably OK
|
|
|
|
|
CONFIG_EXAMPLES_NSAMPLES=8
|
|
|
|
|
|
|
|
|
|
I2S Audio Support
|
|
|
|
|
=================
|
|
|
|
|
|
|
|
|
|
The SAMA4D4-EK has two devices on-board that can be used for verification
|
|
|
|
|
of I2S functionality: HDMI and a WM8904 audio CODEC. As of this writing,
|
|
|
|
|
the I2S driver is present, but there are not drivers for either the HDMI
|
|
|
|
|
or the WM8904.
|
|
|
|
|
|
|
|
|
|
WM8904 Audio CODEC Interface
|
|
|
|
|
----------------------------
|
|
|
|
|
|
|
|
|
|
------------- ---------------- -----------------
|
|
|
|
|
WM8904 SAMA5D4 NuttX Pin Name
|
|
|
|
|
------------- ---------------- -----------------
|
|
|
|
|
3 SDA PA30 TWD0 PIO_TWI0_D
|
|
|
|
|
2 SCLK PA31 TWCK0 PIO_TWI0_CK
|
|
|
|
|
28 MCLK PD30 PCK0 PIO_PMC_PCK0
|
|
|
|
|
29 BCLK/GPIO4 PC16 TK PIO_SSC0_TK
|
|
|
|
|
"" " " PC19 RK PIO_SSC0_RK
|
|
|
|
|
30 LRCLK PC17 TF PIO_SSC0_TF
|
|
|
|
|
"" " " PC20 RF PIO_SSC0_RF
|
|
|
|
|
31 ADCDAT PC21 RD PIO_SSC0_RD
|
|
|
|
|
32 DACDAT PC18 TD PIO_SSC0_TD
|
|
|
|
|
1 IRQ/GPIO1 PD16 INT_AUDIO N/A
|
|
|
|
|
------------- ---------------- -----------------
|
|
|
|
|
|
|
|
|
|
I2S Loopback Test
|
|
|
|
|
-----------------
|
|
|
|
|
|
|
|
|
|
The I2S driver was verified using a special I2C character driver (at
|
|
|
|
|
nuttx/drivers/audio/i2schar.c) and a test driver at apps/examples/i2schar.
|
|
|
|
|
The I2S driver was verified in loopback mode with no audio device.
|
|
|
|
|
|
|
|
|
|
[NOTE: The above statement is anticipatory: As of this writing I2S driver
|
|
|
|
|
verification is underway and still not complete].
|
|
|
|
|
|
|
|
|
|
This section describes the modifications to the NSH configuration that were
|
|
|
|
|
used to perform the I2S testing:
|
|
|
|
|
|
|
|
|
|
System Type -> SAMA5 Peripheral Support
|
|
|
|
|
CONFIG_SAMA5_SSCO=y : Enable SSC0 driver support
|
|
|
|
|
CONFIG_SAMA5_DMAC0=y : DMAC0 required by SSC0
|
|
|
|
|
|
|
|
|
|
Alternatively, SSC1 could have be used:
|
|
|
|
|
|
|
|
|
|
System Type -> SAMA5 Peripheral Support
|
|
|
|
|
CONFIG_SAMA5_SSC1=y : Enable SSC0 driver support
|
|
|
|
|
CONFIG_SAMA5_DMAC1=y : DMAC0 required by SSC0
|
|
|
|
|
|
|
|
|
|
System Type -> SSC Configuration
|
|
|
|
|
CONFIG_SAMA5_SSC_MAXINFLIGHT=16 : Up to 16 pending DMA transfers
|
|
|
|
|
CONFIG_SAMA5_SSC0_MASTER=y : Master mode
|
|
|
|
|
CONFIG_SAMA5_SSC0_DATALEN=16 : 16-bit data
|
|
|
|
|
CONFIG_SAMA5_SSC0_RX=y : Support a receiver
|
|
|
|
|
CONFIG_SAMA5_SSC0_RX_RKINPUT=y : Receiver gets clock from RK input
|
|
|
|
|
CONFIG_SAMA5_SSC0_TX=y : Support a transmitter
|
|
|
|
|
CONFIG_SAMA5_SSC0_TX_MCKDIV=y : Transmitter gets clock from MCK/2
|
|
|
|
|
CONFIG_SAMA5_SSC0_MCKDIV_SAMPLERATE=48000 : Sampling at 48K samples/sec
|
|
|
|
|
CONFIG_SAMA5_SSC0_TX_TKOUTPUT_XFR=y : Outputs clock on TK when transferring data
|
|
|
|
|
CONFIG_SAMA5_SSC0_LOOPBACK=y : Loopmode mode connects RD/TD and RK/TK
|
|
|
|
|
|
|
|
|
|
Audio
|
|
|
|
|
CONFIG_AUDIO=y : Audio support needed
|
|
|
|
|
: Defaults should be okay
|
|
|
|
|
|
|
|
|
|
Drivers -> Audio
|
|
|
|
|
CONFIG_I2S=y : General I2S support
|
|
|
|
|
CONFIG_AUDIO_DEVICES=y : Audio device support
|
|
|
|
|
CONFIG_AUDIO_I2SCHAR=y : Build I2S character driver
|
|
|
|
|
|
|
|
|
|
The following describes how I have the test application at
|
|
|
|
|
apps/examples/i2schar configured:
|
|
|
|
|
|
|
|
|
|
CONFIG_EXAMPLES_I2SCHAR=y
|
|
|
|
|
CONFIG_EXAMPLES_I2SCHAR_DEVPATH="/dev/i2schar0"
|
|
|
|
|
CONFIG_EXAMPLES_I2SCHAR_TX=y
|
|
|
|
|
CONFIG_EXAMPLES_I2SCHAR_TXBUFFERS=4
|
|
|
|
|
CONFIG_EXAMPLES_I2SCHAR_TXSTACKSIZE=1536
|
|
|
|
|
CONFIG_EXAMPLES_I2SCHAR_RX=y
|
|
|
|
|
CONFIG_EXAMPLES_I2SCHAR_RXBUFFERS=4
|
|
|
|
|
CONFIG_EXAMPLES_I2SCHAR_RXSTACKSIZE=1536
|
|
|
|
|
CONFIG_EXAMPLES_I2SCHAR_BUFSIZE=256
|
|
|
|
|
CONFIG_EXAMPLES_I2SCHAR_DEVINIT=y
|
|
|
|
|
|
|
|
|
|
Board Selection
|
|
|
|
|
CONFIG_SAMA5D4EK_I2SCHAR_MINOR=0
|
|
|
|
|
CONFIG_SAMA5D4EK_SSC_PORT=0 : 0 or SSC0, 1 for SSC1
|
|
|
|
|
|
|
|
|
|
Library Routines
|
|
|
|
|
CONFIG_SCHED_WORKQUEUE=y : Driver needs work queue support
|
|
|
|
|
|
|
|
|
|
SAMA4D4-EK Configuration Options
|
|
|
|
|
=================================
|
|
|
|
|
|
|
|
|
|
CONFIG_ARCH - Identifies the arch/ subdirectory. This should
|
|
|
|
|
be set to:
|
|
|
|
|
|
|
|
|
|
CONFIG_ARCH="arm"
|
|
|
|
|
|
|
|
|
|
CONFIG_ARCH_family - For use in C code:
|
|
|
|
|
|
|
|
|
|
CONFIG_ARCH_ARM=y
|
|
|
|
|
|
|
|
|
|
CONFIG_ARCH_architecture - For use in C code:
|
|
|
|
|
|
|
|
|
|
CONFIG_ARCH_CORTEXA5=y
|
|
|
|
|
|
|
|
|
|
CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
|
|
|
|
|
|
|
|
|
|
CONFIG_ARCH_CHIP="sama5"
|
|
|
|
|
|
|
|
|
|
CONFIG_ARCH_CHIP_name - For use in C code to identify the exact
|
|
|
|
|
chip:
|
|
|
|
|
|
|
|
|
|
CONFIG_ARCH_CHIP_SAMA5=y
|
|
|
|
|
CONFIG_ARCH_CHIP_ATSAMA5D44=y
|
|
|
|
|
|
|
|
|
|
CONFIG_ARCH_BOARD - Identifies the configs subdirectory and
|
|
|
|
|
hence, the board that supports the particular chip or SoC.
|
|
|
|
|
|
|
|
|
|
CONFIG_ARCH_BOARD="sama5d4-ek" (for the SAMA4D4-EK development board)
|
|
|
|
|
|
|
|
|
|
CONFIG_ARCH_BOARD_name - For use in C code
|
|
|
|
|
|
|
|
|
|
CONFIG_ARCH_BOARD_SAMA5D4_EK=y
|
|
|
|
|
|
|
|
|
|
CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
|
|
|
|
|
of delay loops
|
|
|
|
|
|
|
|
|
|
CONFIG_ENDIAN_BIG - define if big endian (default is little
|
|
|
|
|
endian)
|
|
|
|
|
|
|
|
|
|
CONFIG_RAM_SIZE - Describes the installed DRAM (SRAM in this case):
|
|
|
|
|
|
|
|
|
|
CONFIG_RAM_SIZE=0x0002000 (128Kb)
|
|
|
|
|
|
|
|
|
|
CONFIG_RAM_START - The physical start address of installed DRAM
|
|
|
|
|
|
|
|
|
|
CONFIG_RAM_START=0x20000000
|
|
|
|
|
|
2014-06-27 01:04:53 +02:00
|
|
|
CONFIG_RAM_VSTART - The virtual start address of installed DRAM
|
2014-06-06 20:37:36 +02:00
|
|
|
|
|
|
|
|
CONFIG_RAM_VSTART=0x20000000
|
|
|
|
|
|
|
|
|
|
CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that
|
|
|
|
|
have LEDs
|
|
|
|
|
|
|
|
|
|
CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
|
|
|
|
|
stack. If defined, this symbol is the size of the interrupt
|
|
|
|
|
stack in bytes. If not defined, the user task stacks will be
|
|
|
|
|
used during interrupt handling.
|
|
|
|
|
|
|
|
|
|
CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
|
|
|
|
|
|
|
|
|
|
CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture.
|
|
|
|
|
|
|
|
|
|
CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that
|
|
|
|
|
cause a 100 second delay during boot-up. This 100 second delay
|
|
|
|
|
serves no purpose other than it allows you to calibrate
|
|
|
|
|
CONFIG_ARCH_LOOPSPERMSEC. You simply use a stop watch to measure
|
|
|
|
|
the 100 second delay then adjust CONFIG_ARCH_LOOPSPERMSEC until
|
|
|
|
|
the delay actually is 100 seconds.
|
|
|
|
|
|
|
|
|
|
Individual subsystems can be enabled:
|
|
|
|
|
|
|
|
|
|
CONFIG_SAMA5_DBGU - Debug Unit
|
|
|
|
|
CONFIG_SAMA5_PIT - Periodic Interval Timer
|
|
|
|
|
CONFIG_SAMA5_WDT - Watchdog timer
|
|
|
|
|
CONFIG_SAMA5_HSMC - Multi-bit ECC
|
|
|
|
|
CONFIG_SAMA5_SMD - SMD Soft Modem
|
|
|
|
|
CONFIG_SAMA5_USART0 - USART 0
|
|
|
|
|
CONFIG_SAMA5_USART1 - USART 1
|
|
|
|
|
CONFIG_SAMA5_USART2 - USART 2
|
|
|
|
|
CONFIG_SAMA5_USART3 - USART 3
|
|
|
|
|
CONFIG_SAMA5_UART0 - UART 0
|
|
|
|
|
CONFIG_SAMA5_UART1 - UART 1
|
|
|
|
|
CONFIG_SAMA5_TWI0 - Two-Wire Interface 0
|
|
|
|
|
CONFIG_SAMA5_TWI1 - Two-Wire Interface 1
|
|
|
|
|
CONFIG_SAMA5_TWI2 - Two-Wire Interface 2
|
|
|
|
|
CONFIG_SAMA5_HSMCI0 - High Speed Multimedia Card Interface 0
|
|
|
|
|
CONFIG_SAMA5_HSMCI1 - High Speed Multimedia Card Interface 1
|
|
|
|
|
CONFIG_SAMA5_SPI0 - Serial Peripheral Interface 0
|
|
|
|
|
CONFIG_SAMA5_SPI1 - Serial Peripheral Interface 1
|
|
|
|
|
CONFIG_SAMA5_TC0 - Timer Counter 0 (ch. 0, 1, 2)
|
|
|
|
|
CONFIG_SAMA5_TC1 - Timer Counter 1 (ch. 3, 4, 5)
|
|
|
|
|
CONFIG_SAMA5_PWM - Pulse Width Modulation Controller
|
|
|
|
|
CONFIG_SAMA5_ADC - Touch Screen ADC Controller
|
2014-06-29 19:26:41 +02:00
|
|
|
CONFIG_SAMA5_XDMAC0 - XDMA Controller 0
|
|
|
|
|
CONFIG_SAMA5_XDMAC1 - XDMA Controller 1
|
2014-06-06 20:37:36 +02:00
|
|
|
CONFIG_SAMA5_UHPHS - USB Host High Speed
|
|
|
|
|
CONFIG_SAMA5_UDPHS - USB Device High Speed
|
2014-06-29 19:26:41 +02:00
|
|
|
CONFIG_SAMA5_EMAC0 - Ethernet MAC 0 (GMAC0)
|
|
|
|
|
CONFIG_SAMA5_EMAC1 - Ethernet MAC 1 (GMAC1)
|
2014-06-06 20:37:36 +02:00
|
|
|
CONFIG_SAMA5_LCDC - LCD Controller
|
|
|
|
|
CONFIG_SAMA5_ISI - Image Sensor Interface
|
|
|
|
|
CONFIG_SAMA5_SSC0 - Synchronous Serial Controller 0
|
|
|
|
|
CONFIG_SAMA5_SSC1 - Synchronous Serial Controller 1
|
|
|
|
|
CONFIG_SAMA5_SHA - Secure Hash Algorithm
|
|
|
|
|
CONFIG_SAMA5_AES - Advanced Encryption Standard
|
|
|
|
|
CONFIG_SAMA5_TDES - Triple Data Encryption Standard
|
|
|
|
|
CONFIG_SAMA5_TRNG - True Random Number Generator
|
|
|
|
|
CONFIG_SAMA5_ARM - Performance Monitor Unit
|
|
|
|
|
CONFIG_SAMA5_FUSE - Fuse Controller
|
|
|
|
|
CONFIG_SAMA5_MPDDRC - MPDDR controller
|
|
|
|
|
|
|
|
|
|
Some subsystems can be configured to operate in different ways. The drivers
|
|
|
|
|
need to know how to configure the subsystem.
|
|
|
|
|
|
|
|
|
|
CONFIG_SAMA5_PIOA_IRQ - Support PIOA interrupts
|
|
|
|
|
CONFIG_SAMA5_PIOB_IRQ - Support PIOB interrupts
|
|
|
|
|
CONFIG_SAMA5_PIOC_IRQ - Support PIOD interrupts
|
|
|
|
|
CONFIG_SAMA5_PIOD_IRQ - Support PIOD interrupts
|
|
|
|
|
CONFIG_SAMA5_PIOE_IRQ - Support PIOE interrupts
|
|
|
|
|
|
|
|
|
|
CONFIG_USART0_ISUART - USART0 is configured as a UART
|
|
|
|
|
CONFIG_USART1_ISUART - USART1 is configured as a UART
|
|
|
|
|
CONFIG_USART2_ISUART - USART2 is configured as a UART
|
|
|
|
|
CONFIG_USART3_ISUART - USART3 is configured as a UART
|
|
|
|
|
|
|
|
|
|
AT91SAMA5 specific device driver settings
|
|
|
|
|
|
|
|
|
|
CONFIG_SAMA5_DBGU_SERIAL_CONSOLE - selects the DBGU
|
|
|
|
|
for the console and ttyDBGU
|
|
|
|
|
CONFIG_SAMA5_DBGU_RXBUFSIZE - Characters are buffered as received.
|
|
|
|
|
This specific the size of the receive buffer
|
|
|
|
|
CONFIG_SAMA5_DBGU_TXBUFSIZE - Characters are buffered before
|
|
|
|
|
being sent. This specific the size of the transmit buffer
|
|
|
|
|
CONFIG_SAMA5_DBGU_BAUD - The configure BAUD of the DBGU.
|
|
|
|
|
CONFIG_SAMA5_DBGU_PARITY - 0=no parity, 1=odd parity, 2=even parity
|
|
|
|
|
|
|
|
|
|
CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=0,1,2,3) or UART
|
|
|
|
|
m (m=4,5) for the console and ttys0 (default is the DBGU).
|
|
|
|
|
CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received.
|
|
|
|
|
This specific the size of the receive buffer
|
|
|
|
|
CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before
|
|
|
|
|
being sent. This specific the size of the transmit buffer
|
|
|
|
|
CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be
|
|
|
|
|
CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8.
|
|
|
|
|
CONFIG_U[S]ARTn_PARITY - 0=no parity, 1=odd parity, 2=even parity
|
|
|
|
|
CONFIG_U[S]ARTn_2STOP - Two stop bits
|
|
|
|
|
|
|
|
|
|
AT91SAMA5 USB Host Configuration
|
|
|
|
|
Pre-requisites
|
|
|
|
|
|
|
|
|
|
CONFIG_USBDEV - Enable USB device support
|
|
|
|
|
CONFIG_USBHOST - Enable USB host support
|
|
|
|
|
CONFIG_SAMA5_UHPHS - Needed
|
|
|
|
|
CONFIG_SAMA5_OHCI - Enable the STM32 USB OTG FS block
|
|
|
|
|
CONFIG_SCHED_WORKQUEUE - Worker thread support is required
|
|
|
|
|
|
|
|
|
|
Options:
|
|
|
|
|
|
|
|
|
|
CONFIG_SAMA5_OHCI_NEDS
|
|
|
|
|
Number of endpoint descriptors
|
|
|
|
|
CONFIG_SAMA5_OHCI_NTDS
|
|
|
|
|
Number of transfer descriptors
|
|
|
|
|
CONFIG_SAMA5_OHCI_TDBUFFERS
|
|
|
|
|
Number of transfer descriptor buffers
|
|
|
|
|
CONFIG_SAMA5_OHCI_TDBUFSIZE
|
|
|
|
|
Size of one transfer descriptor buffer
|
|
|
|
|
CONFIG_USBHOST_INT_DISABLE
|
|
|
|
|
Disable interrupt endpoint support
|
|
|
|
|
CONFIG_USBHOST_ISOC_DISABLE
|
|
|
|
|
Disable isochronous endpoint support
|
|
|
|
|
CONFIG_USBHOST_BULK_DISABLE
|
|
|
|
|
Disable bulk endpoint support
|
|
|
|
|
|
|
|
|
|
config SAMA5_OHCI_REGDEBUG
|
|
|
|
|
|
|
|
|
|
Configurations
|
|
|
|
|
==============
|
|
|
|
|
|
|
|
|
|
Information Common to All Configurations
|
|
|
|
|
----------------------------------------
|
|
|
|
|
Each SAMA4D4-EK configuration is maintained in a sub-directory and
|
|
|
|
|
can be selected as follow:
|
|
|
|
|
|
|
|
|
|
cd tools
|
|
|
|
|
./configure.sh sama5d4-ek/<subdir>
|
|
|
|
|
cd -
|
|
|
|
|
. ./setenv.sh
|
|
|
|
|
|
|
|
|
|
Before sourcing the setenv.sh file above, you should examine it and perform
|
|
|
|
|
edits as necessary so that TOOLCHAIN_BIN is the correct path to the directory
|
|
|
|
|
than holds your toolchain binaries.
|
|
|
|
|
|
|
|
|
|
And then build NuttX by simply typing the following. At the conclusion of
|
|
|
|
|
the make, the nuttx binary will reside in an ELF file called, simply, nuttx.
|
|
|
|
|
|
|
|
|
|
make
|
|
|
|
|
|
|
|
|
|
The <subdir> that is provided above as an argument to the tools/configure.sh
|
|
|
|
|
must be is one of the following.
|
|
|
|
|
|
|
|
|
|
NOTES:
|
|
|
|
|
|
|
|
|
|
1. These configurations use the mconf-based configuration tool. To
|
|
|
|
|
change any of these configurations using that tool, you should:
|
|
|
|
|
|
|
|
|
|
a. Build and install the kconfig-mconf tool. See nuttx/README.txt
|
|
|
|
|
and misc/tools/
|
|
|
|
|
|
|
|
|
|
b. Execute 'make menuconfig' in nuttx/ in order to start the
|
|
|
|
|
reconfiguration process.
|
|
|
|
|
|
|
|
|
|
2. Unless stated otherwise, all configurations generate console
|
|
|
|
|
output on the DBGU (J23).
|
|
|
|
|
|
|
|
|
|
3. All of these configurations use the Code Sourcery for Windows toolchain
|
|
|
|
|
(unless stated otherwise in the description of the configuration). That
|
|
|
|
|
toolchain selection can easily be reconfigured using 'make menuconfig'.
|
|
|
|
|
Here are the relevant current settings:
|
|
|
|
|
|
|
|
|
|
Build Setup:
|
|
|
|
|
CONFIG_HOST_WINDOWS=y : Microsoft Windows
|
|
|
|
|
CONFIG_WINDOWS_CYGWIN=y : Using Cygwin or other POSIX environment
|
|
|
|
|
|
|
|
|
|
System Type -> Toolchain:
|
|
|
|
|
CONFIG_ARMV7A_TOOLCHAIN_GNU_EABIW=y : GNU EABI toolchain for windows
|
|
|
|
|
|
|
|
|
|
That same configuration will work with Atmel GCC toolchain. The only
|
|
|
|
|
change required to use the Atmel GCC toolchain is to change the PATH
|
|
|
|
|
variable so that those tools are selected instead of the CodeSourcery
|
|
|
|
|
tools. Try 'which arm-none-eabi-gcc' to make sure that you are
|
|
|
|
|
selecting the right tool.
|
|
|
|
|
|
|
|
|
|
The setenv.sh file is available for you to use to set the PATH
|
|
|
|
|
variable. The path in the that file may not, however, be correct
|
|
|
|
|
for your installation.
|
|
|
|
|
|
|
|
|
|
See also the "NOTE about Windows native toolchains" in the section call
|
|
|
|
|
"GNU Toolchain Options" above.
|
|
|
|
|
|
|
|
|
|
!!!WARNING!!! The first time that you type 'make', the system will
|
|
|
|
|
configure itself based on the settings in the .config file. One of
|
|
|
|
|
these settings can cause a lot of confusion if you configure the build
|
|
|
|
|
in the wrong state: If you are running on Linux, make *certain* that
|
|
|
|
|
you have CONFIG_HOST_LINUX=y *before* the first make or you will
|
|
|
|
|
create a very corrupt configuration that may not be easy to recover
|
|
|
|
|
from.
|
|
|
|
|
|
|
|
|
|
4. The SAMA5Dx is running at 396MHz by default in these configurations.
|
|
|
|
|
This is because the original timing for the PLLs, NOR FLASH, and SDRAM
|
|
|
|
|
came from the Atmel NoOS sample code which runs at that rate.
|
|
|
|
|
|
|
|
|
|
The SAMA5Dx is capable of running at 528MHz, however, and is easily
|
|
|
|
|
re-configured:
|
|
|
|
|
|
|
|
|
|
Board Selection -> CPU Frequency
|
|
|
|
|
CONFIG_SAMA5D4EK_396MHZ=n # Disable 396MHz operation
|
|
|
|
|
CONFIG_SAMA5D4EK_528MHZ=y # Enable 528MHz operation
|
|
|
|
|
|
|
|
|
|
If you switch to 528MHz, you should also check the loop calibration
|
|
|
|
|
value in your .config file. Of course, it would be best to re-calibrate
|
|
|
|
|
the timing loop, but these values should get you in the ballpark:
|
|
|
|
|
|
|
|
|
|
CONFIG_BOARD_LOOPSPERMSEC=49341 # Calibrated on SAMA5D3-EK at 396MHz
|
|
|
|
|
# running from ISRAM
|
|
|
|
|
CONFIG_BOARD_LOOPSPERMSEC=65775 # Calibrated on SAMA5D3-Xplained at
|
|
|
|
|
# 528MHz running from SDRAM
|
|
|
|
|
|
|
|
|
|
Operation at 528MHz has been verified but is not the default in these
|
|
|
|
|
configurations because most testing was done at 396MHz. NAND has not
|
|
|
|
|
been verified at these rates.
|
|
|
|
|
|
|
|
|
|
Configuration Sub-directories
|
|
|
|
|
-----------------------------
|
|
|
|
|
Summary: Some of the descriptions below are long and wordy. Here is the
|
|
|
|
|
concise summary of the available SAMA4D4-EK configurations:
|
|
|
|
|
|
2014-06-28 17:57:00 +02:00
|
|
|
at25boot: This is a little program to write a boot loader into the
|
|
|
|
|
AT25 serial FLASH (in particular, dramboot). See the description
|
|
|
|
|
below and the section above entitled "Creating and Using AT25BOOT"
|
|
|
|
|
for more information
|
2014-06-27 00:42:06 +02:00
|
|
|
dramboot: This is a little program to help debug of code in DRAM. See
|
|
|
|
|
the description below and the section above entitled "Creating and
|
|
|
|
|
Using DRAMBOOT" for more information
|
2014-06-06 20:37:36 +02:00
|
|
|
nsh: This is another NSH configuration, not too different from the
|
|
|
|
|
demo configuration. The nsh configuration is, however, bare bones.
|
|
|
|
|
It is the simplest possible NSH configuration and is useful as a
|
|
|
|
|
platform for debugging and integrating new features in isolation.
|
2014-06-14 21:11:42 +02:00
|
|
|
ramtest: This is a stripped down version of NSH that runs out of
|
|
|
|
|
internal SRAM. It configures SDRAM and supports only the RAM test
|
|
|
|
|
at apps/examples/ramtest. This configuration is useful for
|
|
|
|
|
bringing up SDRAM.
|
2014-06-06 20:37:36 +02:00
|
|
|
|
|
|
|
|
There may be issues with some of these configurations. See the details
|
|
|
|
|
before of the status of individual configurations.
|
|
|
|
|
|
|
|
|
|
Now for the gory details:
|
|
|
|
|
|
2014-06-28 17:57:00 +02:00
|
|
|
at25boot:
|
|
|
|
|
|
|
|
|
|
To work around some SAM-BA availability issues that I had at one time,
|
|
|
|
|
I created the at25boot program. at25boot is a tiny program that runs in
|
|
|
|
|
ISRAM. at25boot will enable SDRAM and configure the AT25 Serial FLASH.
|
|
|
|
|
It will prompt and then load an Intel HEX program into SDRAM over the
|
|
|
|
|
serial console. If the program is successfully loaded in SDRAM, at25boot
|
|
|
|
|
will copy the program at the beginning of the AT26 Serial FLASH.
|
|
|
|
|
If the jumpering is set correctly, the SAMA5D4 RomBOOT loader will
|
|
|
|
|
then boot the program from the serial FLASH the next time that it
|
|
|
|
|
reset.
|
|
|
|
|
|
|
|
|
|
The usage is different, otherwise I believe the notes for the dramboot
|
|
|
|
|
configuration should all apply.
|
|
|
|
|
|
2014-06-28 20:38:41 +02:00
|
|
|
STATUS: While this program works great and appears to correctly write
|
|
|
|
|
the binary image onto the AT25 Serial FLASH, the RomBOOT loader will
|
|
|
|
|
not boot it! I believe that is because the secure boot loader has some
|
|
|
|
|
undocumented requirements that I am unaware of. (2014-6-28)
|
|
|
|
|
|
2014-06-27 00:42:06 +02:00
|
|
|
dramboot:
|
2014-06-27 01:04:53 +02:00
|
|
|
|
2014-06-27 00:42:06 +02:00
|
|
|
This is a little program to help debug of code in DRAM. It does the
|
|
|
|
|
following:
|
|
|
|
|
|
2014-06-29 17:52:07 +02:00
|
|
|
- Sets the clocking so that the SAMA5 is running at 528MHz.
|
|
|
|
|
- Configures DRAM,
|
|
|
|
|
- Loads and Intel HEX file into DRAM over the terminal port,
|
|
|
|
|
- Waits for you to break in with GDB (or optionally starts the
|
|
|
|
|
newly loaded program).
|
2014-06-27 00:42:06 +02:00
|
|
|
|
|
|
|
|
At that point, you can set the PC and begin executing from SDRAM under
|
|
|
|
|
debug control. See the section entitled "Creating and Using
|
|
|
|
|
DRAMBOOT" above.
|
|
|
|
|
|
|
|
|
|
NOTES:
|
|
|
|
|
|
|
|
|
|
1. This configuration uses the the USART3 for the serial console
|
|
|
|
|
which is available at the "DBGU" RS-232 connector (J24). That
|
|
|
|
|
is easily changed by reconfiguring to (1) enable a different
|
|
|
|
|
serial peripheral, and (2) selecting that serial peripheral as
|
|
|
|
|
the console device.
|
|
|
|
|
|
|
|
|
|
2. By default, this configuration is set up to build on Windows
|
|
|
|
|
under either a Cygwin or MSYS environment using a recent, Windows-
|
|
|
|
|
native, generic ARM EABI GCC toolchain (such as the CodeSourcery
|
|
|
|
|
toolchain). Both the build environment and the toolchain
|
|
|
|
|
selection can easily be changed by reconfiguring:
|
|
|
|
|
|
|
|
|
|
CONFIG_HOST_WINDOWS=y : Windows operating system
|
|
|
|
|
CONFIG_WINDOWS_CYGWIN=y : POSIX environment under windows
|
|
|
|
|
CONFIG_ARMV7A_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery for Windows
|
|
|
|
|
|
|
|
|
|
If you are running on Linux, make *certain* that you have
|
|
|
|
|
CONFIG_HOST_LINUX=y *before* the first make or you will create a
|
|
|
|
|
corrupt configuration that may not be easy to recover from. See
|
|
|
|
|
the warning in the section "Information Common to All Configurations"
|
|
|
|
|
for further information.
|
|
|
|
|
|
|
|
|
|
3. This configuration executes out of internal SRAM flash and is
|
|
|
|
|
loaded into SRAM by the boot RomBoot from NAND, Serial
|
|
|
|
|
DataFlash, SD card or from a TFTPC sever via the Boot ROM.
|
|
|
|
|
Data also is positioned in SRAM.
|
|
|
|
|
|
|
|
|
|
2. The default dramboot program initializes the DRAM memory,
|
|
|
|
|
displays a message, loads an Intel HEX program into DRAM over the
|
|
|
|
|
serial console and halts. The dramboot program can also be
|
|
|
|
|
configured to jump directly into DRAM without requiring the
|
|
|
|
|
final halt and go by setting CONFIG_SAMA5D4EK_DRAM_START=y in the
|
|
|
|
|
NuttX configuration.
|
|
|
|
|
|
|
|
|
|
3. Be aware that the default dramboot also disables the watchdog.
|
|
|
|
|
Since you will not be able to re-enable the watchdog later, you may
|
|
|
|
|
need to set CONFIG_SAMA5_WDT=y in the NuttX configuration file.
|
|
|
|
|
|
|
|
|
|
4. If you put dramboot on the Serial FLASH, you can automatically
|
|
|
|
|
boot to SDRAM on reset. See the section "Creating and Using DRAMBOOT"
|
|
|
|
|
above.
|
|
|
|
|
|
|
|
|
|
5. Here are the steps that I use to execute this program in SRAM
|
|
|
|
|
using only the ROM Bootloader:
|
|
|
|
|
|
|
|
|
|
a) Hold the DIS_BOOT button and
|
|
|
|
|
|
|
|
|
|
b) With the DIS_BOOT button pressed, power cycle the board. A
|
|
|
|
|
reset does not seem to be sufficient.
|
|
|
|
|
|
|
|
|
|
c) The serial should show RomBOOT in a terminal window (at 115200
|
|
|
|
|
8N1) and nothing more.
|
|
|
|
|
|
|
|
|
|
d) Press ENTER in the terminal window a few times to enable JTAG.
|
|
|
|
|
|
|
|
|
|
e) Start the Segger GDB server. It should successfully connect to
|
|
|
|
|
the board via JTAG (if JTAG was correctly enabled in step d)).
|
|
|
|
|
|
|
|
|
|
f) Start GDB, connect, to the GDB server, load NuttX, and debug.
|
|
|
|
|
|
|
|
|
|
gdb> target remote localhost:2331
|
|
|
|
|
gdb> mon halt (don't do mon reset)
|
|
|
|
|
gdb> load nuttx
|
|
|
|
|
gdb> mon reg pc (make sure that the PC is 0x200040
|
|
|
|
|
gdb> ... and debug ...
|
|
|
|
|
|
2014-06-28 20:38:41 +02:00
|
|
|
STATUS: I don't have a working SAM-BA at the moment and there are issues
|
|
|
|
|
with my AT25BOOT (see above). I currently work around these issues by
|
|
|
|
|
putting DRAMBOOT on a microSD card (as boot.bin). The RomBOOT loader does
|
|
|
|
|
boot that image without issue.
|
|
|
|
|
|
2014-06-06 20:37:36 +02:00
|
|
|
nsh:
|
|
|
|
|
|
2014-06-14 21:11:42 +02:00
|
|
|
This configuration directory provide the NuttShell (NSH). This is a
|
|
|
|
|
very simple NSH configuration upon which you can build further
|
|
|
|
|
functionality.
|
2014-06-06 20:37:36 +02:00
|
|
|
|
|
|
|
|
NOTES:
|
2014-06-27 00:42:06 +02:00
|
|
|
|
2014-06-14 21:11:42 +02:00
|
|
|
1. This configuration uses the the USART3 for the serial console
|
|
|
|
|
which is available at the "DBGU" RS-232 connector (J24). That
|
2014-06-06 20:37:36 +02:00
|
|
|
is easily changed by reconfiguring to (1) enable a different
|
|
|
|
|
serial peripheral, and (2) selecting that serial peripheral as
|
|
|
|
|
the console device.
|
|
|
|
|
|
|
|
|
|
2. By default, this configuration is set up to build on Windows
|
|
|
|
|
under either a Cygwin or MSYS environment using a recent, Windows-
|
|
|
|
|
native, generic ARM EABI GCC toolchain (such as the CodeSourcery
|
|
|
|
|
toolchain). Both the build environment and the toolchain
|
|
|
|
|
selection can easily be changed by reconfiguring:
|
|
|
|
|
|
|
|
|
|
CONFIG_HOST_WINDOWS=y : Windows operating system
|
|
|
|
|
CONFIG_WINDOWS_CYGWIN=y : POSIX environment under windows
|
|
|
|
|
CONFIG_ARMV7A_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery for Windows
|
|
|
|
|
|
|
|
|
|
If you are running on Linux, make *certain* that you have
|
|
|
|
|
CONFIG_HOST_LINUX=y *before* the first make or you will create a
|
|
|
|
|
corrupt configuration that may not be easy to recover from. See
|
|
|
|
|
the warning in the section "Information Common to All Configurations"
|
|
|
|
|
for further information.
|
|
|
|
|
|
|
|
|
|
3. This configuration executes out of SDRAM flash and is loaded into
|
|
|
|
|
SDRAM from NAND, Serial DataFlash, SD card or from a TFTPC sever via
|
2014-06-27 01:04:53 +02:00
|
|
|
U-Boot, BareBox, or the DRAMBOOT configuration described above. Data
|
|
|
|
|
also is positioned in SDRAM.
|
|
|
|
|
|
|
|
|
|
The load address is different for the DRAMBOOT program and the Linux
|
|
|
|
|
bootloaders. This can easily be reconfigured, however:
|
|
|
|
|
|
|
|
|
|
CONFIG_SAMA5D4EK_DRAM_BOOT=y
|
2014-06-06 20:37:36 +02:00
|
|
|
|
2014-06-27 01:04:53 +02:00
|
|
|
See the section above entitled "Creating and Using DRAMBOOT" above
|
2014-06-28 21:27:19 +02:00
|
|
|
for more information. Here is a summary of the steps that I used
|
|
|
|
|
to boot the NSH configuration:
|
2014-06-27 01:04:53 +02:00
|
|
|
|
2014-06-28 21:27:19 +02:00
|
|
|
a. Create the DRAMBOOT program as described above. It should be
|
|
|
|
|
configured with CONFIG_SAMA5D4EK_DRAM_START=y so that DRAMBOOT
|
|
|
|
|
will immediately start the program. You may not want to do
|
|
|
|
|
this is your prefer to break in with GDB.
|
|
|
|
|
|
|
|
|
|
b. Write the DRAMBOOT program binary (nuttx.bin) to a microSD
|
|
|
|
|
card as "boot.bin". Insert the microSD card into the boar;
|
|
|
|
|
The ROM Booloader should now boot DRAMBOOT on reset and you
|
|
|
|
|
should see this message:
|
|
|
|
|
|
|
|
|
|
Send Intel HEX file now
|
|
|
|
|
|
|
|
|
|
c. Build the NSH version of NuttX. Send the Intel HEX of NSH
|
|
|
|
|
at the prompt. After the file is received, NSH should start
|
|
|
|
|
automatically.
|
|
|
|
|
|
|
|
|
|
At times the past, have have tested with nuttx.bin on an SD card and
|
|
|
|
|
booting with U-Boot. These are the commands that I used to boot NuttX
|
|
|
|
|
from the SD card:
|
2014-06-06 20:37:36 +02:00
|
|
|
|
|
|
|
|
U-Boot> fatload mmc 0 0x20008000 nuttx.bin
|
|
|
|
|
U-Boot> go 0x20008040
|
|
|
|
|
|
2014-06-29 00:11:41 +02:00
|
|
|
4. This configuration supports /dev/null, /dev/zero, and /dev/random.
|
|
|
|
|
|
|
|
|
|
CONFIG_DEV_NULL=y : Enables /dev/null
|
|
|
|
|
CONFIG_DEV_ZERO=y : Enabled /dev/zero
|
|
|
|
|
|
|
|
|
|
Support for /dev/random is implemented using the SAMA5D4's True
|
|
|
|
|
Random Number Generator (TRNG). See the section above entitled
|
|
|
|
|
"TRNG and /dev/random" for information about configuring /dev/random.
|
|
|
|
|
|
|
|
|
|
CONFIG_SAMA5_TRNG=y : Enables the TRNG peripheral
|
|
|
|
|
CONFIG_DEV_RANDOM=y : Enables /dev/random
|
|
|
|
|
|
|
|
|
|
5. This configuration has support for NSH built-in applications enabled.
|
|
|
|
|
|
|
|
|
|
6. This configuration has support for the FAT and ROMFS file systems
|
|
|
|
|
built in.
|
|
|
|
|
|
|
|
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|
The FAT file system includes long file name support. Please be aware
|
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|
|
that Microsoft claims patents against the long file name support (see
|
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|
|
|
more discussion in the top-level COPYING file).
|
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|
|
CONFIG_FS_FAT=y : Enables the FAT file system
|
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|
|
CONFIG_FAT_LCNAMES=y : Enable lower case 8.3 file names
|
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|
CONFIG_FAT_LFN=y : Enables long file name support
|
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|
CONFIG_FAT_MAXFNAME=32 : Arbitrarily limits the size of a path
|
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|
|
segment name to 32 bytes
|
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|
The ROMFS file system is enabled simply with:
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|
CONFIG_FS_ROMFS=y : Enable ROMFS file system
|
2014-06-06 20:37:36 +02:00
|
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|
2014-06-29 00:11:41 +02:00
|
|
|
6. An NSH star-up script is provided by the ROMFS file system. The ROMFS
|
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|
|
file system is mounted at /etc and provides:
|
2014-06-06 20:37:36 +02:00
|
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|
2014-06-29 00:11:41 +02:00
|
|
|
|- dev/
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|
| `- ram0
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|
`- etc/
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|
`- init.d/
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|
`- rcS
|
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(There will, of course, be other devices uner /dev include /dev/console,
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|
/dev/null, /dev/zero, /dev/random, etc.).
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|
Relevant configuration options include:
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|
CONFIG_NSH_ROMFSETC=y : Enable mounting at of startup file system
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|
CONFIG_NSH_ROMFSMOUNTPT="/etc" : Mount at /etc
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|
|
CONFIG_NSH_ROMFSDEVNO=0 : Device is /dev/ram0
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|
CONFIG_NSH_ARCHROMFS=y : ROMFS image is at
|
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|
|
configs/sama5d4-ek/include/nsh_romfsimg.h
|
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|
|
The content of /etc/init.d/rcS can be see in the file rcS.template that
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|
|
can be found at: configs/sama5d4-ek/include/rcS.template:
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|
|
mkrd -m 2 -s 512 1024
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|
mkfatfs /dev/ram1
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|
|
mount -t vfat /dev/ram1 /tmp
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|
|
The above commands will create a RAM disk block device at /dev/ram1.
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|
|
The RAM disk will take 0.4MiB of memory (512 x 1024). Then it will
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|
|
create a FAT file system on the ram disk and mount it at /tmp. So
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|
|
after NSH starts and runs the rcS script, we will have:
|
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|
|
|- dev/
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|
|
| |- ram0
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|
| `- ram2
|
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|
|
|- etc/
|
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|
|
| `- init.d/
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|
|
| `- rcS
|
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|
|
`- tmp/
|
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|
|
The /tmp directory can them be used for and scratch purpose.
|
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|
|
|
2014-06-29 15:40:37 +02:00
|
|
|
7. The Real Time Clock/Calendar (RTC) is enabled in this configuration.
|
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|
|
See the section entitled "RTC" above for detailed configuration
|
|
|
|
|
settings.
|
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|
|
The RTC alarm is not enabled by default since there is nothing in
|
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|
|
this configuration that uses it. The alarm can easily be enabled,
|
|
|
|
|
however, as described in the "RTC" section.
|
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|
|
|
|
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|
|
The time value from the RTC will be used as the NuttX system time
|
|
|
|
|
in all timestamp operations. You may use the NSH 'date' command
|
|
|
|
|
to set or view the RTC as described above in the "RTC" section.
|
|
|
|
|
|
|
|
|
|
NOTE: If you want the RTC to preserve time over power cycles, you
|
|
|
|
|
will need to install a battery in the battery holder (J12) and close
|
|
|
|
|
the jumper, JP13.
|
|
|
|
|
|
2014-06-29 19:26:41 +02:00
|
|
|
8. Support for HSMCI0 and HSMCI1 is built-in by default. The SAMA4D4-EK
|
|
|
|
|
provides a two SD memory card slots: (1) a full size SD card slot
|
|
|
|
|
(J10), and (2) a microSD memory card slot (J11). The full size SD
|
|
|
|
|
card slot connects via HSMCI0; the microSD connects vi HSMCI1.
|
|
|
|
|
Support for both SD slots can be enabled with the settings provided
|
|
|
|
|
in the paragraph entitled "HSMCI Card Slots" above.
|
|
|
|
|
|
|
|
|
|
NOTE: For now I am boot off the microSD slot so, unless are booting
|
|
|
|
|
in a different manner, this HSMCI1 slot may not be useful to you.
|
2014-06-06 20:37:36 +02:00
|
|
|
|
2014-06-29 17:36:15 +02:00
|
|
|
9. The SAMA5D4-EK includes for an AT25 serial DataFlash. That support is
|
|
|
|
|
NOT enabled in this configuration. Support for that serial FLASH can
|
|
|
|
|
be enabled by modifying the NuttX configuration as described above in
|
|
|
|
|
the paragraph entitled "AT25 Serial FLASH".
|
|
|
|
|
|
2014-06-29 15:40:37 +02:00
|
|
|
10. Support the USB low-, high- and full-speed OHCI host driver can be enabled
|
2014-06-06 20:37:36 +02:00
|
|
|
by changing the NuttX configuration file as described in the section
|
|
|
|
|
entitled "USB High-Speed Host" above.
|
|
|
|
|
|
2014-06-29 15:40:37 +02:00
|
|
|
11. Support the USB high-speed USB device driver (UDPHS) can be enabled
|
2014-06-06 20:37:36 +02:00
|
|
|
by changing the NuttX configuration file as described above in the
|
|
|
|
|
section entitled "USB High-Speed Device."
|
|
|
|
|
|
2014-06-29 15:40:37 +02:00
|
|
|
12. I2C Tool. NuttX supports an I2C tool at apps/system/i2c that can be
|
2014-06-29 00:11:41 +02:00
|
|
|
used to peek and poke I2C devices. See the discussion above under
|
|
|
|
|
"I2C Tool" for detailed configuration settings.
|
2014-06-06 20:37:36 +02:00
|
|
|
|
2014-06-29 15:40:37 +02:00
|
|
|
13. Networking support via the can be added to NSH by modifying the
|
2014-06-29 00:11:41 +02:00
|
|
|
configuration. See the "Networking" section above for detailed
|
|
|
|
|
configuration settings.
|
2014-06-06 20:37:36 +02:00
|
|
|
|
2014-06-29 00:11:41 +02:00
|
|
|
14. This example can be configured to exercise the watchdog timer test
|
|
|
|
|
(apps/examples/watchdog). See the detailed configuration settings in
|
|
|
|
|
the section entitled "Watchdog Timer" above.
|
2014-06-06 20:37:36 +02:00
|
|
|
|
2014-06-29 00:11:41 +02:00
|
|
|
STATUS:
|
2014-06-06 20:37:36 +02:00
|
|
|
See the To-Do list below
|
|
|
|
|
|
2014-06-27 01:04:53 +02:00
|
|
|
ramtest:
|
|
|
|
|
|
2014-06-14 21:11:42 +02:00
|
|
|
This is a stripped down version of NSH that runs out of
|
|
|
|
|
internal SRAM. It configures SDRAM and supports only the RAM test
|
|
|
|
|
at apps/examples/ramtest. This configuration is useful for
|
|
|
|
|
bringing up SDRAM.
|
|
|
|
|
|
|
|
|
|
NOTES:
|
2014-06-27 00:42:06 +02:00
|
|
|
|
2014-06-14 21:11:42 +02:00
|
|
|
1. This configuration uses the the USART3 for the serial console
|
|
|
|
|
which is available at the "DBGU" RS-232 connector (J24). That
|
|
|
|
|
is easily changed by reconfiguring to (1) enable a different
|
|
|
|
|
serial peripheral, and (2) selecting that serial peripheral as
|
|
|
|
|
the console device.
|
|
|
|
|
|
|
|
|
|
2. By default, this configuration is set up to build on Windows
|
|
|
|
|
under either a Cygwin or MSYS environment using a recent, Windows-
|
|
|
|
|
native, generic ARM EABI GCC toolchain (such as the CodeSourcery
|
|
|
|
|
toolchain). Both the build environment and the toolchain
|
|
|
|
|
selection can easily be changed by reconfiguring:
|
|
|
|
|
|
|
|
|
|
CONFIG_HOST_WINDOWS=y : Windows operating system
|
|
|
|
|
CONFIG_WINDOWS_CYGWIN=y : POSIX environment under windows
|
|
|
|
|
CONFIG_ARMV7A_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery for Windows
|
|
|
|
|
|
|
|
|
|
If you are running on Linux, make *certain* that you have
|
|
|
|
|
CONFIG_HOST_LINUX=y *before* the first make or you will create a
|
|
|
|
|
corrupt configuration that may not be easy to recover from. See
|
|
|
|
|
the warning in the section "Information Common to All Configurations"
|
|
|
|
|
for further information.
|
|
|
|
|
|
|
|
|
|
3. This configuration executes out of internal SRAM flash and is
|
|
|
|
|
loaded into SRAM by the boot ROM SDRAM from NAND, Serial
|
|
|
|
|
DataFlash, SD card or from a TFTPC sever via the Boot ROM.
|
2014-06-27 00:42:06 +02:00
|
|
|
Data also is positioned in SRAM.
|
2014-06-06 20:37:36 +02:00
|
|
|
|
2014-06-18 21:03:10 +02:00
|
|
|
Here are the steps that I use to execute this program in SRAM
|
|
|
|
|
using only the ROM Bootloader:
|
|
|
|
|
|
|
|
|
|
a) Hold the DIS_BOOT button and
|
|
|
|
|
|
2014-06-19 01:40:06 +02:00
|
|
|
b) With the DIS_BOOT button pressed, power cycle the board. A
|
|
|
|
|
reset does not seem to be sufficient.
|
2014-06-18 21:03:10 +02:00
|
|
|
|
|
|
|
|
c) The serial should show RomBOOT in a terminal window (at 115200
|
|
|
|
|
8N1) and nothing more.
|
|
|
|
|
|
|
|
|
|
d) Press ENTER in the terminal window a few times to enable JTAG.
|
|
|
|
|
|
|
|
|
|
e) Start the Segger GDB server. It should successfully connect to
|
2014-06-19 01:40:06 +02:00
|
|
|
the board via JTAG (if JTAG was correctly enabled in step d)).
|
|
|
|
|
|
|
|
|
|
f) Start GDB, connect, to the GDB server, load NuttX, and debug.
|
2014-06-18 21:03:10 +02:00
|
|
|
|
|
|
|
|
gdb> target remote localhost:2331
|
|
|
|
|
gdb> mon halt (don't do mon reset)
|
|
|
|
|
gdb> load nuttx
|
|
|
|
|
gdb> mon reg pc (make sure that the PC is 0x200040
|
|
|
|
|
gdb> ... and debug ...
|
|
|
|
|
|
2014-06-06 20:37:36 +02:00
|
|
|
To-Do List
|
|
|
|
|
==========
|
|
|
|
|
|
|
|
|
|
1) Neither USB OHCI nor EHCI support Isochronous endpoints. Interrupt
|
|
|
|
|
endpoint support in the EHCI driver is untested (but works in similar
|
|
|
|
|
EHCI drivers).
|
|
|
|
|
|
|
|
|
|
2) HSCMI TX DMA support is currently commented out.
|
|
|
|
|
|
2014-06-14 21:11:42 +02:00
|
|
|
3) Some drivers may require some adjustments if you intend to run from SDRAM.
|
2014-06-06 20:37:36 +02:00
|
|
|
That is because in this case macros like BOARD_MCK_FREQUENCY are not constants
|
|
|
|
|
but are instead function calls: The MCK clock frequency is not known in
|
|
|
|
|
advance but instead has to be calculated from the bootloader PLL configuration.
|
|
|
|
|
|
|
|
|
|
As of this writing, all drivers have been converted to run from SDRAM except
|
|
|
|
|
for the PWM and the Timer/Counter drivers. These drivers use the
|
|
|
|
|
BOARD_MCK_FREQUENCY definition in more complex ways and will require some
|
|
|
|
|
minor redesign and re-testing before they can be available.
|
