2016-03-25 21:21:24 +01:00
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/************************************************************************************
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* configs/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h
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*
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2016-03-25 22:01:16 +01:00
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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2016-03-25 21:21:24 +01:00
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* Author: dev@ziggurat29.com
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __CONFIGS_STM32L476VG_DISCO_INCLUDE_STM32L476VG_DISCO_CLOCKING_H
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#define __CONFIGS_STM32L476VG_DISCO_INCLUDE_STM32L476VG_DISCO_CLOCKING_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Clocking *************************************************************************/
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2016-04-30 05:13:32 +02:00
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/* The stm32l476vg-disco supports both HSE and LSE crystals. As shipped, the HSE
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2016-04-30 17:04:38 +02:00
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* crystal is not populated. Therefore the stm32l476vg-disco will need to run off the
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* 16MHz HSI clock, or the 32khz-synced MSI, unless you install the HSE xtal.
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2016-03-25 21:21:24 +01:00
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*/
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/* HSI - 16 MHz RC factory-trimmed
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* LSI - 32 KHz RC
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* MSI - variable up to 48 MHz, synchronized to LSE
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* HSE - not installed
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* LSE - 32.768 kHz installed
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*/
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#define STM32L4_HSI_FREQUENCY 16000000ul
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#define STM32L4_LSI_FREQUENCY 32000
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#define STM32L4_LSE_FREQUENCY 32768
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2016-04-18 04:08:25 +02:00
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#define BOARD_AHB_FREQUENCY 80000000ul
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2016-04-30 05:13:32 +02:00
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/* XXX there needs to be independent selections for the System Clock Mux and
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2016-04-30 17:04:38 +02:00
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* the PLL Source Mux; currently System Clock Mux always is PLL, and PLL
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* Source Mux is chosen by the following define. This is probably OK in many
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* cases, but should be separated to support other power configurations.
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2016-03-25 21:21:24 +01:00
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*/
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2016-04-30 05:13:32 +02:00
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#if 0
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2017-07-25 00:46:30 +02:00
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# define HSI_CLOCK_CONFIG 1 /* HSI-16 clock configuration */
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2016-04-30 05:13:32 +02:00
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#elif 0
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2016-04-30 17:04:38 +02:00
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/* Make sure you actually installed one! */
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2017-07-25 00:46:30 +02:00
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# define HSE_CLOCK_CONFIG 1 /* HSE with 8 MHz xtal */
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2016-04-30 05:13:32 +02:00
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#else
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2017-07-25 00:46:30 +02:00
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# define MSI_CLOCK_CONFIG 1 /* MSI @ 4 MHz autotrimmed via LSE */
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2016-04-30 05:13:32 +02:00
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#endif
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#if defined(HSI_CLOCK_CONFIG)
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2016-04-30 17:04:38 +02:00
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#define STM32L4_BOARD_USEHSI 1
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2016-03-25 21:21:24 +01:00
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2016-04-30 17:04:38 +02:00
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/* Prescaler common to all PLL inputs; will be 1 (XXX source is implicitly
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2016-03-25 21:21:24 +01:00
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as per comment above HSI) */
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#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1)
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/* 'main' PLL config; we use this to generate our system clock via the R
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2016-03-25 22:01:16 +01:00
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* output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz
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*
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* XXX NOTE: currently the main PLL is implicitly turned on and is implicitly
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* the system clock; this should be configurable since not all applications may
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* want things done this way.
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2016-03-25 21:21:24 +01:00
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*/
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#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10)
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#define STM32L4_PLLCFG_PLLP 0
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#undef STM32L4_PLLCFG_PLLP_ENABLED
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#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2
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#define STM32L4_PLLCFG_PLLQ_ENABLED
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#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2
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#define STM32L4_PLLCFG_PLLR_ENABLED
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/* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't
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2016-03-25 22:01:16 +01:00
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* do that with the main PLL's N value. We set N = 13, and enable
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* the Q output (ultimately for CLK48) with /4. So,
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* 16 MHz / 1 * 12 / 4 = 48 MHz
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*
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* XXX NOTE: currently the SAIPLL /must/ be explicitly selected in the
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* menuconfig, or else all this is a moot point, and the various 48 MHz
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* peripherals will not work (RNG at present). I would suggest removing
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* that option from Kconfig altogether, and simply making it an option
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* that is selected via a #define here, like all these other params.
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2016-03-25 21:21:24 +01:00
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*/
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#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12)
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#define STM32L4_PLLSAI1CFG_PLLP 0
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#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED
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#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4
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#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
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#define STM32L4_PLLSAI1CFG_PLLR 0
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#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED
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/* 'SAIPLL2' is not used in this application */
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#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8)
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#define STM32L4_PLLSAI2CFG_PLLP 0
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#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED
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#define STM32L4_PLLSAI2CFG_PLLR 0
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#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED
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#define STM32L4_SYSCLK_FREQUENCY 80000000ul
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/* CLK48 will come from PLLSAI1 (implicitly Q) */
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2016-03-27 21:16:15 +02:00
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#define STM32L4_USE_CLK48 1
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2016-03-25 21:21:24 +01:00
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#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
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2016-04-30 17:04:38 +02:00
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/* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */
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2016-03-27 19:13:19 +02:00
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2016-03-27 21:16:15 +02:00
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#define STM32L4_USE_LSE 1
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2016-03-27 19:13:19 +02:00
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2016-03-25 21:21:24 +01:00
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/* AHB clock (HCLK) is SYSCLK (80MHz) */
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#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY
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#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
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/* APB1 clock (PCLK1) is HCLK/1 (80MHz) */
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#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
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#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
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/* Timers driven from APB1 will be twice PCLK1 */
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/* REVISIT : this can be configured */
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#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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/* APB2 clock (PCLK2) is HCLK (80MHz) */
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#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
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#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
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/* Timers driven from APB2 will be twice PCLK2 */
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/* REVISIT : this can be configured */
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#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
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* otherwise frequency is 2xAPBx.
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* Note: TIM1,8 are on APB2, others on APB1
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*/
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/* REVISIT : this can be configured */
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2016-04-30 05:13:32 +02:00
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#elif defined(HSE_CLOCK_CONFIG)
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2016-04-30 17:04:38 +02:00
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/* Use the HSE */
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2016-04-30 05:13:32 +02:00
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#define STM32L4_BOARD_USEHSE 1
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/* XXX sysclk mux = pllclk */
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/* XXX pll source mux = hse */
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2016-04-30 17:04:38 +02:00
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/* Prescaler common to all PLL inputs */
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2016-04-30 05:13:32 +02:00
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#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1)
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/* 'main' PLL config; we use this to generate our system clock */
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#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20)
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#define STM32L4_PLLCFG_PLLP 0
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#undef STM32L4_PLLCFG_PLLP_ENABLED
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#define STM32L4_PLLCFG_PLLQ 0
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#undef STM32L4_PLLCFG_PLLQ_ENABLED
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#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2
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#define STM32L4_PLLCFG_PLLR_ENABLED
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/* 'SAIPLL1' is used to generate the 48 MHz clock */
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#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12)
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#define STM32L4_PLLSAI1CFG_PLLP 0
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#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED
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#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2
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#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
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#define STM32L4_PLLSAI1CFG_PLLR 0
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#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED
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/* 'SAIPLL2' is not used in this application */
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#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8)
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#define STM32L4_PLLSAI2CFG_PLLP 0
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#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED
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#define STM32L4_PLLSAI2CFG_PLLR 0
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#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED
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#define STM32L4_SYSCLK_FREQUENCY 80000000ul
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2016-04-30 17:04:38 +02:00
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/* Enable CLK48; get it from PLLSAI1 */
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2016-04-30 05:13:32 +02:00
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#define STM32L4_USE_CLK48
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#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
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2016-04-30 17:04:38 +02:00
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/* Enable LSE (for the RTC) */
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2016-04-30 05:13:32 +02:00
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#define STM32L4_USE_LSE 1
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2016-04-30 17:04:38 +02:00
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/* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
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2016-04-30 05:13:32 +02:00
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#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY
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#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
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2016-04-30 17:04:38 +02:00
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/* Configure the APB1 prescaler */
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2016-04-30 05:13:32 +02:00
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#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
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#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
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#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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2016-04-30 17:04:38 +02:00
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/* Configure the APB2 prescaler */
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2016-04-30 05:13:32 +02:00
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#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
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#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
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#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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#elif defined(MSI_CLOCK_CONFIG)
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2016-04-30 17:04:38 +02:00
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/* Use the MSI; frequ = 4 MHz; autotrim from LSE */
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2016-04-30 05:13:32 +02:00
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#define STM32L4_BOARD_USEMSI 1
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#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M
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/* XXX sysclk mux = pllclk */
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/* XXX pll source mux = msi */
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2016-04-30 17:04:38 +02:00
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/* Prescaler common to all PLL inputs */
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2016-04-30 05:13:32 +02:00
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#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1)
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/* 'main' PLL config; we use this to generate our system clock */
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#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40)
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#define STM32L4_PLLCFG_PLLP 0
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#undef STM32L4_PLLCFG_PLLP_ENABLED
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#define STM32L4_PLLCFG_PLLQ 0
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2017-07-25 00:46:30 +02:00
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#undef STM32L4_PLLCFG_PLLQ_ENABLED
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2016-04-30 05:13:32 +02:00
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#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2
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#define STM32L4_PLLCFG_PLLR_ENABLED
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/* 'SAIPLL1' is used to generate the 48 MHz clock */
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#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24)
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#define STM32L4_PLLSAI1CFG_PLLP 0
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#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED
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#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2
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#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
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#define STM32L4_PLLSAI1CFG_PLLR 0
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#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED
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/* 'SAIPLL2' is not used in this application */
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#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8)
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#define STM32L4_PLLSAI2CFG_PLLP 0
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#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED
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#define STM32L4_PLLSAI2CFG_PLLR 0
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#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED
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#define STM32L4_SYSCLK_FREQUENCY 80000000ul
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2016-04-30 17:04:38 +02:00
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/* Enable CLK48; get it from PLLSAI1 */
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2016-04-30 05:13:32 +02:00
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#define STM32L4_USE_CLK48
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#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
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2016-04-30 17:04:38 +02:00
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/* Enable LSE (for the RTC) */
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2016-04-30 05:13:32 +02:00
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#define STM32L4_USE_LSE 1
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2016-04-30 17:04:38 +02:00
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/* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
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2016-04-30 05:13:32 +02:00
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#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY
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2017-07-25 00:46:30 +02:00
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#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
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2016-04-30 05:13:32 +02:00
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2016-04-30 17:04:38 +02:00
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/* Configure the APB1 prescaler */
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2016-04-30 05:13:32 +02:00
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#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
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#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
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#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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|
2016-04-30 17:04:38 +02:00
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/* Configure the APB2 prescaler */
|
2016-04-30 05:13:32 +02:00
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#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
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#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
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#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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#endif
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|
2016-07-08 23:39:55 +02:00
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
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* otherwise frequency is 2xAPBx.
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* Note: TIM1,8,15,16,17 are on APB2, others on APB1
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*/
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#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY
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#define BOARD_TIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
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#define BOARD_TIM3_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
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#define BOARD_TIM4_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
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#define BOARD_TIM5_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
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#define BOARD_TIM6_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
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#define BOARD_TIM7_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
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#define BOARD_TIM8_FREQUENCY STM32L4_HCLK_FREQUENCY
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#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY
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#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY
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#define BOARD_TIM17_FREQUENCY STM32L4_HCLK_FREQUENCY
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#define BOARD_LPTIM1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
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#define BOARD_LPTIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
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2016-03-25 21:21:24 +01:00
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/************************************************************************************
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* Public Data
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************************************************************************************/
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/************************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __CONFIGS_STM32L476VG_DISCO_INCLUDE_STM32L476VG_DISCO_CLOCKING_H */
|
