265 lines
14 KiB
C
265 lines
14 KiB
C
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/************************************************************************************
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* arch/arm/include/stm32f0l0/chip.h
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*
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* Copyright (C) 2017 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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* Alan Carvalho de Assis <acassis@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_STM32F0L0_CHIP_H
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#define __ARCH_ARM_INCLUDE_STM32F0L0_CHIP_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Get customizations for each supported chip */
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#if defined(CONFIG_ARCH_CHIP_STM32F051R8)
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# define STM32F051x 1 /* STM32F051x family */
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# undef STM32F072x /* Not STM32F072x family */
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# undef STM32F091x /* Not STM32F091x family */
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# define STM32_FLASH_SIZE (64*1024) /* 64Kb */
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# define STM32_SRAM_SIZE (8*1024) /* 8Kb */
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# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
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# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */
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# define STM32_NI2C 2 /* Two I2C modules */
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# define STM32_NUSART 2 /* Two USARTs modules */
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# define STM32_NCAN 0 /* No CAN controllers */
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# define STM32_NUSBDEV 1 /* One USB device controller */
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# define STM32_NDAC 1 /* One DAC module */
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# define STM32_NDACCHAN 1 /* One DAC channels */
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# define STM32_NCOMP 2 /* Two Analog Comparators */
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# define STM32_NCAP 13 /* Capacitive sensing channels (14 on UFQFPN32)) */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
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#elif defined(CONFIG_ARCH_CHIP_STM32F072C8) || defined(CONFIG_ARCH_CHIP_STM32F072CB)
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# undef STM32F051x /* Not STM32F051x family */
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# define STM32F072x 1 /* STM32F072x family */
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# undef STM32F091x /* Not STM32F091x family */
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# ifdef CONFIG_ARCH_CHIP_STM32F072C8
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# define STM32_FLASH_SIZE (64*1024) /* 64Kb */
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# else
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# define STM32_FLASH_SIZE (128*1024) /* 128Kb */
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# endif
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# define STM32_SRAM_SIZE (16*1024) /* 16Kb */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
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# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */
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# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
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# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
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# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */
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# define STM32_NI2C 2 /* Two I2C modules */
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# define STM32_NUSART 4 /* Four USARTs module */
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# define STM32_NCAN 1 /* One CAN controller */
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# define STM32_NUSBDEV 1 /* One USB device controller */
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# define STM32_NCEC 1 /* One HDMI-CEC controller */
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# define STM32_NADC12 1 /* One 12-bit module */
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# define STM32_NADCCHAN 10 /* Ten external channels */
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# define STM32_NADCINT 3 /* Three internal channels */
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# define STM32_NDAC 1 /* One DAC module */
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# define STM32_NDACCHAN 2 /* Two DAC channels */
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# define STM32_NCOMP 2 /* Two Analog Comparators */
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# define STM32_NCAP 17 /* Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
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#elif defined(CONFIG_ARCH_CHIP_STM32F072R8) || defined(CONFIG_ARCH_CHIP_STM32F072RB)
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# undef STM32F051x /* Not STM32F051x family */
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# define STM32F072x 1 /* STM32F072x family */
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# undef STM32F091x /* Not STM32F091x family */
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# ifdef CONFIG_ARCH_CHIP_STM32F072R8
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# define STM32_FLASH_SIZE (64*1024) /* 64Kb */
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# else
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# define STM32_FLASH_SIZE (128*1024) /* 128Kb */
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# endif
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# define STM32_SRAM_SIZE (16*1024) /* 16Kb */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
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# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */
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# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
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# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
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# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */
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# define STM32_NI2C 2 /* Two I2C modules */
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# define STM32_NUSART 4 /* Four USARTs module */
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# define STM32_NCAN 1 /* One CAN controller */
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# define STM32_NUSBDEV 1 /* One USB device controller */
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# define STM32_NCEC 1 /* One HDMI-CEC controller */
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# define STM32_NADC12 1 /* One 12-bit module */
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# define STM32_NADCCHAN 16 /* 16 external channels */
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# define STM32_NADCINT 3 /* Three internal channels */
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# define STM32_NDAC 1 /* One DAC module */
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# define STM32_NDACCHAN 2 /* Two DAC channels */
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# define STM32_NCOMP 2 /* Two Analog Comparators */
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# define STM32_NCAP 18 /* Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
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#elif defined(CONFIG_ARCH_CHIP_STM32F072V8) || defined(CONFIG_ARCH_CHIP_STM32F072VB)
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# undef STM32F051x /* Not STM32F051x family */
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# define STM32F072x 1 /* STM32F072x family */
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# undef STM32F091x /* Not STM32F091x family */
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# ifdef CONFIG_ARCH_CHIP_STM32F072V8
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# define STM32_FLASH_SIZE (64*1024) /* 64Kb */
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# else
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# define STM32_FLASH_SIZE (128*1024) /* 128Kb */
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# endif
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# define STM32_SRAM_SIZE (16*1024) /* 16Kb */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
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# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */
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# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
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# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
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# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */
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# define STM32_NI2C 2 /* Two I2C modules */
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# define STM32_NUSART 4 /* Four USARTs module */
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# define STM32_NCAN 1 /* One CAN controller */
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# define STM32_NUSBDEV 1 /* One USB device controller */
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# define STM32_NCEC 1 /* One HDMI-CEC controller */
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# define STM32_NADC12 1 /* One 12-bit module */
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# define STM32_NADCCHAN 16 /* 16 external channels */
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# define STM32_NADCINT 3 /* Three internal channels */
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# define STM32_NDAC 1 /* One DAC module */
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# define STM32_NDACCHAN 2 /* Two DAC channels */
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# define STM32_NCOMP 2 /* Two Analog Comparators */
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# define STM32_NCAP 24 /* Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
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#elif defined(CONFIG_ARCH_CHIP_STM32F091CB) || defined(CONFIG_ARCH_CHIP_STM32F091CC)
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# undef STM32F051x /* Not STM32F051x family */
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# undef STM32F072x /* Not STM32F072x family */
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# define STM32F091x 1 /* STM32F091x family */
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# ifdef CONFIG_ARCH_CHIP_STM32F091CB
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# define STM32_FLASH_SIZE (128*1024) /* 128Kb */
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# else
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# define STM32_FLASH_SIZE (256*1024) /* 256Kb */
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# endif
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# define STM32_SRAM_SIZE (32*1024) /* 32Kb */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
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# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */
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# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
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# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
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# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */
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# define STM32_NI2C 2 /* Two I2C modules */
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# define STM32_NUSART 6 /* Six USARTs modules */
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# define STM32_NCAN 1 /* One CAN controller */
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# define STM32_NUSBDEV 0 /* No USB device controller */
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# define STM32_NCEC 1 /* One HDMI-CEC controller */
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# define STM32_NADC12 1 /* One 12-bit module */
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# define STM32_NADCCHAN 10 /* 10 external channels */
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# define STM32_NADCINT 3 /* Three internal channels */
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# define STM32_NDAC 1 /* One DAC module */
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# define STM32_NDACCHAN 2 /* Two DAC channels */
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# define STM32_NCOMP 2 /* Two Analog Comparators */
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# define STM32_NCAP 17 /* Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
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#elif defined(CONFIG_ARCH_CHIP_STM32F091RB) || defined(CONFIG_ARCH_CHIP_STM32F091RC) \
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|| defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC)
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# undef STM32F051x /* Not STM32F051x family */
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# undef STM32F072x /* Not STM32F072x family */
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# define STM32F091x 1 /* STM32F091x family */
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# if defined(CONFIG_ARCH_CHIP_STM32F091RB) || defined(CONFIG_ARCH_CHIP_STM32F091VB)
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# define STM32_FLASH_SIZE (128*1024) /* 128Kb */
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# else
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# define STM32_FLASH_SIZE (256*1024) /* 256Kb */
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# endif
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# define STM32_SRAM_SIZE (32*1024) /* 32Kb */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
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# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */
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# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
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# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
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# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */
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# define STM32_NI2C 2 /* Two I2C modules */
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# define STM32_NUSART 8 /* Eight USARTs modules */
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# define STM32_NCAN 1 /* One CAN controller */
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# define STM32_NUSBDEV 0 /* No USB device controller */
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# define STM32_NCEC 1 /* One HDMI-CEC controller */
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# define STM32_NADC12 1 /* One 12-bit module */
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# define STM32_NADCCHAN 16 /* 16 external channels */
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# define STM32_NADCINT 3 /* Three internal channels */
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# define STM32_NDAC 1 /* One DAC module */
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# define STM32_NDACCHAN 2 /* Two DAC channels */
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# define STM32_NCOMP 2 /* Two Analog Comparators */
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# if defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC)
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# define STM32_NCAP 24 /* Capacitive sensing channels */
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# else
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# define STM32_NCAP 18 /* Capacitive sensing channels */
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# endif
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
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#else
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# error "Unsupported STM32F0xx chip"
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#endif
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/* NVIC priority levels *************************************************************/
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/* Each priority field holds a priority value, 0-31. The lower the value, the greater
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* the priority of the corresponding interrupt. The processor implements only
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* bits[7:6] of each field, bits[5:0] read as zero and ignore writes.
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*/
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#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_INCLUDE_STM32F0L0_CHIP_H */
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