2020-12-03 13:10:10 +01:00
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############################################################################
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2021-04-04 21:51:24 +02:00
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# libs/libc/machine/risc-v/common/arch_setjmp.S
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2020-12-03 13:10:10 +01:00
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#
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# Licensed to the Apache Software Foundation (ASF) under one or more
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# contributor license agreements. See the NOTICE file distributed with
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# this work for additional information regarding copyright ownership. The
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# ASF licenses this file to you under the Apache License, Version 2.0 (the
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# "License"); you may not use this file except in compliance with the
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# License. You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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# License for the specific language governing permissions and limitations
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# under the License.
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#
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############################################################################
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2022-03-08 14:17:58 +01:00
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#include <nuttx/config.h>
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#ifdef CONFIG_ARCH_RV64
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# define SZREG 8
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2020-12-03 13:10:10 +01:00
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# define REG_S sd
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# define REG_L ld
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2022-03-08 14:17:58 +01:00
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#elif defined(CONFIG_ARCH_RV32)
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# define SZREG 4
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2020-12-03 13:10:10 +01:00
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# define REG_S sw
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# define REG_L lw
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2022-03-08 14:17:58 +01:00
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#endif
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#ifdef CONFIG_ARCH_QPFPU
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# define SZFREG 16
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# define FREG_S fsq
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# define FREG_L flq
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#elif defined(CONFIG_ARCH_DPFPU)
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# define SZFREG 8
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# define FREG_S fsd
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# define FREG_L fld
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#elif defined(CONFIG_ARCH_FPU)
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# define SZFREG 4
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# define FREG_S fsw
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# define FREG_L flw
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2020-12-03 13:10:10 +01:00
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#endif
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.section .text
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.globl setjmp
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.type setjmp, @function
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setjmp:
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2022-03-08 14:17:58 +01:00
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REG_S ra, 0*SZREG(a0)
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REG_S s0, 1*SZREG(a0)
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REG_S s1, 2*SZREG(a0)
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REG_S s2, 3*SZREG(a0)
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REG_S s3, 4*SZREG(a0)
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REG_S s4, 5*SZREG(a0)
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REG_S s5, 6*SZREG(a0)
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REG_S s6, 7*SZREG(a0)
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REG_S s7, 8*SZREG(a0)
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REG_S s8, 9*SZREG(a0)
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REG_S s9, 10*SZREG(a0)
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REG_S s10, 11*SZREG(a0)
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REG_S s11, 12*SZREG(a0)
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REG_S sp, 13*SZREG(a0)
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2020-12-03 13:10:10 +01:00
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2022-03-08 14:17:58 +01:00
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addi a0, a0, 14 * SZREG
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#ifdef CONFIG_ARCH_FPU
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FREG_S fs0, 0*SZFREG(a0)
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FREG_S fs1, 1*SZFREG(a0)
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FREG_S fs2, 2*SZFREG(a0)
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FREG_S fs3, 3*SZFREG(a0)
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FREG_S fs4, 4*SZFREG(a0)
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FREG_S fs5, 5*SZFREG(a0)
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FREG_S fs6, 6*SZFREG(a0)
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FREG_S fs7, 7*SZFREG(a0)
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FREG_S fs8, 8*SZFREG(a0)
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FREG_S fs9, 9*SZFREG(a0)
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FREG_S fs10, 10*SZFREG(a0)
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FREG_S fs11, 11*SZFREG(a0)
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#endif
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2020-12-03 13:10:10 +01:00
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li a0, 0
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ret
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.size setjmp, .-setjmp
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/* volatile void longjmp (jmp_buf, int); */
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.section .text
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.globl longjmp
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.type longjmp, @function
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longjmp:
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2022-03-08 14:17:58 +01:00
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REG_L ra, 0*SZREG(a0)
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REG_L s0, 1*SZREG(a0)
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REG_L s1, 2*SZREG(a0)
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REG_L s2, 3*SZREG(a0)
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REG_L s3, 4*SZREG(a0)
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REG_L s4, 5*SZREG(a0)
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REG_L s5, 6*SZREG(a0)
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REG_L s6, 7*SZREG(a0)
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REG_L s7, 8*SZREG(a0)
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REG_L s8, 9*SZREG(a0)
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REG_L s9, 10*SZREG(a0)
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REG_L s10, 11*SZREG(a0)
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REG_L s11, 12*SZREG(a0)
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REG_L sp, 13*SZREG(a0)
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addi a0, a0, 14 * SZREG
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2020-12-03 13:10:10 +01:00
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2022-03-08 14:17:58 +01:00
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#ifdef CONFIG_ARCH_FPU
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FREG_L fs0, 0*SZFREG(a0)
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FREG_L fs1, 1*SZFREG(a0)
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FREG_L fs2, 2*SZFREG(a0)
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FREG_L fs3, 3*SZFREG(a0)
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FREG_L fs4, 4*SZFREG(a0)
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FREG_L fs5, 5*SZFREG(a0)
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FREG_L fs6, 6*SZFREG(a0)
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FREG_L fs7, 7*SZFREG(a0)
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FREG_L fs8, 8*SZFREG(a0)
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FREG_L fs9, 9*SZFREG(a0)
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FREG_L fs10, 10*SZFREG(a0)
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FREG_L fs11, 11*SZFREG(a0)
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#endif
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2020-12-03 13:10:10 +01:00
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seqz a0, a1
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add a0, a0, a1 # a0 = (a1 == 0) ? 1 : a1
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ret
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.size longjmp, .-longjmp
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