2017-02-19 21:20:56 +01:00
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/****************************************************************************
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2019-08-12 18:06:40 +02:00
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* boards/arm/kinetis/twr-k64f120m/scripts/ld.script
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2017-02-19 21:20:56 +01:00
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*
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2021-03-17 18:14:12 +01:00
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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2017-02-19 21:20:56 +01:00
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*
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2021-03-17 18:14:12 +01:00
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* http://www.apache.org/licenses/LICENSE-2.0
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2017-02-19 21:20:56 +01:00
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*
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2021-03-17 18:14:12 +01:00
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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2017-02-19 21:20:56 +01:00
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*
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****************************************************************************/
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/* The MK64FN1M0VMD12 has 1MB of FLASH beginning at address 0x0000:0000 and
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* 256KB of SRAM beginning at address 0x1fff:0000 (SRAM_L 64KB) and 0x2000:0000
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* (SRAM_U 192KB).
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*
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* NOTE: that the first part of the K64 FLASH region is reserved for
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* interrupt vectflash and, following that, is a region from 0x0000:0400
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* to 0x0000:040f that is reserved for the FLASH control fields (FCF).
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*
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* NOTE: The on-chip RAM is split evenly among SRAM_L and SRAM_U. The RAM is
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* also implemented such that the SRAM_L and SRAM_U ranges form a
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* contiguous block in the memory map.
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*/
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MEMORY
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{
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2019-09-16 01:22:16 +02:00
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vectflash (rx) : ORIGIN = 0x00000000, LENGTH = 1K
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cfmprotect (rx) : ORIGIN = 0x00000400, LENGTH = 16
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progflash (rx) : ORIGIN = 0x00000800, LENGTH = 1M - 2K
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datasram (rwx) : ORIGIN = 0x1fff0000, LENGTH = 256K
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2017-02-19 21:20:56 +01:00
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}
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OUTPUT_ARCH(arm)
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2018-06-20 16:18:32 +02:00
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EXTERN(_vectors)
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2017-02-19 21:20:56 +01:00
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ENTRY(_stext)
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EXTERN(__flashconfigbytes)
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SECTIONS
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{
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2019-09-16 01:22:16 +02:00
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.vectors : {
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_svectors = ABSOLUTE(.);
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*(.vectors)
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_evectors = ABSOLUTE(.);
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} > vectflash
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2017-02-19 21:20:56 +01:00
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2019-09-16 01:22:16 +02:00
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.cfmprotect : {
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KEEP(*(.cfmconfig))
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} > cfmprotect
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2017-02-19 21:20:56 +01:00
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2019-09-16 01:22:16 +02:00
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.text : {
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_stext = ABSOLUTE(.);
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*(.text .text.*)
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*(.fixup)
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*(.gnu.warning)
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*(.rodata .rodata.*)
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*(.gnu.linkonce.t.*)
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*(.glue_7)
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*(.glue_7t)
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*(.got)
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*(.gcc_except_table)
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*(.gnu.linkonce.r.*)
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_etext = ABSOLUTE(.);
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} > progflash
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2017-02-19 21:20:56 +01:00
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2019-09-16 01:22:16 +02:00
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.init_section : ALIGN(4) {
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_sinit = ABSOLUTE(.);
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2023-08-25 09:02:40 +02:00
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KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
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2023-12-22 04:45:30 +01:00
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KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors))
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2019-09-16 01:22:16 +02:00
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_einit = ABSOLUTE(.);
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} > progflash
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2017-02-19 21:20:56 +01:00
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2019-09-16 01:22:16 +02:00
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.ARM.extab : ALIGN(4) {
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*(.ARM.extab*)
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} > progflash
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2017-02-19 21:20:56 +01:00
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2019-09-16 01:22:16 +02:00
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.ARM.exidx : ALIGN(4) {
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__exidx_start = ABSOLUTE(.);
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*(.ARM.exidx*)
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__exidx_end = ABSOLUTE(.);
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} > progflash
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2017-02-19 21:20:56 +01:00
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2019-09-16 01:22:16 +02:00
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.data : ALIGN(4) {
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_sdata = ABSOLUTE(.);
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*(.data .data.*)
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*(.gnu.linkonce.d.*)
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CONSTRUCTORS
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. = ALIGN(4);
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_edata = ABSOLUTE(.);
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} > datasram AT > progflash
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2017-02-19 21:20:56 +01:00
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2019-09-16 01:22:16 +02:00
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_eronly = LOADADDR(.data);
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2017-02-19 21:20:56 +01:00
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2019-09-16 01:22:16 +02:00
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.ramfunc ALIGN(4): {
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_sramfuncs = ABSOLUTE(.);
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*(.ramfunc .ramfunc.*)
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_eramfuncs = ABSOLUTE(.);
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} > datasram AT > progflash
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2017-02-19 21:20:56 +01:00
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2019-09-16 01:22:16 +02:00
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_framfuncs = LOADADDR(.ramfunc);
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2017-02-19 21:20:56 +01:00
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2019-09-16 01:22:16 +02:00
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.bss : ALIGN(4) {
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_sbss = ABSOLUTE(.);
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*(.bss .bss.*)
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*(.gnu.linkonce.b.*)
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*(COMMON)
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. = ALIGN(4);
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_ebss = ABSOLUTE(.);
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} > datasram
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2017-02-19 21:20:56 +01:00
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2019-09-16 01:22:16 +02:00
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/* Stabs debugging sections. */
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.stab 0 : { *(.stab) }
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.stabstr 0 : { *(.stabstr) }
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.stab.excl 0 : { *(.stab.excl) }
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.stab.exclstr 0 : { *(.stab.exclstr) }
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.stab.index 0 : { *(.stab.index) }
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.stab.indexstr 0 : { *(.stab.indexstr) }
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.comment 0 : { *(.comment) }
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.debug_abbrev 0 : { *(.debug_abbrev) }
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.debug_info 0 : { *(.debug_info) }
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.debug_line 0 : { *(.debug_line) }
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.debug_pubnames 0 : { *(.debug_pubnames) }
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.debug_aranges 0 : { *(.debug_aranges) }
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2017-02-19 21:20:56 +01:00
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}
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