221 lines
11 KiB
C
221 lines
11 KiB
C
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/****************************************************************************
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* arch/arm/include/stm32wb/stm32wb_irq.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* This file should never be included directly but, rather, only indirectly
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* through arch/irq.h
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*/
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#ifndef __ARCH_ARM_INCLUDE_STM32WB_STM32WB_IRQ_H
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#define __ARCH_ARM_INCLUDE_STM32WB_STM32WB_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* IRQ numbers. The IRQ number corresponds vector number and hence map
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* directly to bits in the NVIC. This does, however, waste several words of
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* memory in the IRQ to handle mapping tables.
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*
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* Processor Exceptions (vectors 0-15). These common definitions can be
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* found in the file nuttx/arch/arm/include/stm32wb/irq.h which includes
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* this file
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*
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* External interrupts (vectors >= 16)
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*
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* These interrupts vectors was implemented based on RM0434 Table 61.
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*
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*/
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#define STM32WB_IRQ_WWDG (STM32WB_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
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#define STM32WB_IRQ_PVD (STM32WB_IRQ_FIRST + 1) /* 1: PVD through EXTI[16] Line detection interrupt */
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#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55)
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# define STM32WB_IRQ_PVM1 (STM32WB_IRQ_FIRST + 1) /* 1: PVM1 through EXTI[31] Line detection interrupt */
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#endif
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#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) \
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|| defined(CONFIG_STM32WB_STM32WB15)
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# define STM32WB_IRQ_PVM3 (STM32WB_IRQ_FIRST + 1) /* 1: PVM3 through EXTI[33] Line detection interrupt */
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#endif
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#define STM32WB_IRQ_TAMPER (STM32WB_IRQ_FIRST + 2) /* 2: Tamper through EXTI[18] interrupts */
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#define STM32WB_IRQ_TIMESTAMP (STM32WB_IRQ_FIRST + 2) /* 2: Time stamp through EXTI[18] interrupts */
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#define STM32WB_IRQ_LSECSS (STM32WB_IRQ_FIRST + 2) /* 2: LSECSS through EXTI[18] interrupts */
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#define STM32WB_IRQ_RTC_WKUP (STM32WB_IRQ_FIRST + 3) /* 3: RTC global interrupt */
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#define STM32WB_IRQ_FLASH (STM32WB_IRQ_FIRST + 4) /* 4: Flash global interrupt */
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#define STM32WB_IRQ_RCC (STM32WB_IRQ_FIRST + 5) /* 5: RCC global interrupt */
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#define STM32WB_IRQ_EXTI0 (STM32WB_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */
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#define STM32WB_IRQ_EXTI1 (STM32WB_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */
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#define STM32WB_IRQ_EXTI2 (STM32WB_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */
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#define STM32WB_IRQ_EXTI3 (STM32WB_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */
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#define STM32WB_IRQ_EXTI4 (STM32WB_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */
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#define STM32WB_IRQ_DMA1CH1 (STM32WB_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */
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#define STM32WB_IRQ_DMA1CH2 (STM32WB_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */
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#define STM32WB_IRQ_DMA1CH3 (STM32WB_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */
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#define STM32WB_IRQ_DMA1CH4 (STM32WB_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */
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#define STM32WB_IRQ_DMA1CH5 (STM32WB_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */
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#define STM32WB_IRQ_DMA1CH6 (STM32WB_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */
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#define STM32WB_IRQ_DMA1CH7 (STM32WB_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */
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#define STM32WB_IRQ_ADC1 (STM32WB_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */
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#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55)
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#define STM32WB_IRQ_USB_HP (STM32WB_IRQ_FIRST + 19) /* 19: USB High Priority Interrupt */
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#define STM32WB_IRQ_USB_LP (STM32WB_IRQ_FIRST + 20) /* 20: USB Low Priority Interrupt */
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#endif
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#define STM32WB_IRQ_C2SEV (STM32WB_IRQ_FIRST + 21) /* 21: CPU2 SEV Interrupt */
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#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) \
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|| defined(CONFIG_STM32WB_STM32WB15)
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# define STM32WB_IRQ_COMP (STM32WB_IRQ_FIRST + 22) /* 22: COMP1/COMP2 Interrupts */
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#endif
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#define STM32WB_IRQ_EXTI95 (STM32WB_IRQ_FIRST + 23) /* 23: EXTI Lines [9:5] Interrupt */
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#define STM32WB_IRQ_TIM1BRK (STM32WB_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */
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#define STM32WB_IRQ_TIM1UP (STM32WB_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */
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#define STM32WB_IRQ_TIM1TRGCOM (STM32WB_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Communication Interrupts */
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#if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \
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|| defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55)
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# define STM32WB_IRQ_TIM16 (STM32WB_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */
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# define STM32WB_IRQ_TIM17 (STM32WB_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */
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#endif
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#define STM32WB_IRQ_TIM1CC (STM32WB_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */
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#define STM32WB_IRQ_TIM2 (STM32WB_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */
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#define STM32WB_IRQ_PKA (STM32WB_IRQ_FIRST + 29) /* 29: PKA Interrupt */
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#define STM32WB_IRQ_I2C1EV (STM32WB_IRQ_FIRST + 30) /* 30: I2C1 event interrupt */
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#define STM32WB_IRQ_I2C1ER (STM32WB_IRQ_FIRST + 31) /* 31: I2C1 error interrupt */
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#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55)
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# define STM32WB_IRQ_I2C3EV (STM32WB_IRQ_FIRST + 32) /* 32: I2C3 event interrupt */
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# define STM32WB_IRQ_I2C3ER (STM32WB_IRQ_FIRST + 33) /* 33: I2C3 error interrupt */
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#endif
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#define STM32WB_IRQ_SPI1 (STM32WB_IRQ_FIRST + 34) /* 34: SPI1 global interrupt */
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#if defined(CONFIG_STM32WB_STM32WB55)
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# define STM32WB_IRQ_SPI2 (STM32WB_IRQ_FIRST + 35) /* 35: SPI2 global interrupt */
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#endif
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#define STM32WB_IRQ_USART1 (STM32WB_IRQ_FIRST + 36) /* 36: USART1 global interrupt */
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#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) \
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|| defined(CONFIG_STM32WB_STM32WB15)
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# define STM32WB_IRQ_LPUART1 (STM32WB_IRQ_FIRST + 37) /* 37: LPUART1 global interrupt */
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#endif
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#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55)
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# define STM32WB_IRQ_SAI1 (STM32WB_IRQ_FIRST + 38) /* 38: SAI1 A/B global interrupt */
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#endif
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#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) \
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|| defined(CONFIG_STM32WB_STM32WB55)
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# define STM32WB_IRQ_TSC (STM32WB_IRQ_FIRST + 39) /* 39: TSC global interrupt */
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#endif
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#define STM32WB_IRQ_EXTI1510 (STM32WB_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */
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#define STM32WB_IRQ_RTCALRM (STM32WB_IRQ_FIRST + 41) /* 41: RTC alarm A/B interrupt */
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#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55)
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# define STM32WB_IRQ_CRS (STM32WB_IRQ_FIRST + 42) /* 42: CRS interrupt */
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#endif
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#define STM32WB_IRQ_PWRSOTF (STM32WB_IRQ_FIRST + 43) /* 43: PWR switching on the fly interrupt */
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#define STM32WB_IRQ_PWRBLEACT (STM32WB_IRQ_FIRST + 43) /* 43: PWR end of BLE activity interrupt */
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#define STM32WB_IRQ_PWRRFPHASE (STM32WB_IRQ_FIRST + 43) /* 43: PWR end of critical radio phase interrupt */
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#if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \
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|| defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55)
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# define STM32WB_IRQ_PWR802ACT (STM32WB_IRQ_FIRST + 43) /* 43: PWR end of 802.15.4 activity interrupt */
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#endif
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#define STM32WB_IRQ_IPCCRX (STM32WB_IRQ_FIRST + 44) /* 44: IPCC RX occupied interrupt */
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#define STM32WB_IRQ_IPCCTX (STM32WB_IRQ_FIRST + 45) /* 45: IPCC TX free interrupt */
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#define STM32WB_IRQ_HSEM (STM32WB_IRQ_FIRST + 46) /* 46: Semaphore interrupt 0 to CPU1 */
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#define STM32WB_IRQ_LPTIM1 (STM32WB_IRQ_FIRST + 47) /* 47: LPTIM1 global interrupt */
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#define STM32WB_IRQ_LPTIM2 (STM32WB_IRQ_FIRST + 48) /* 48: LPTIM2 global interrupt */
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#if defined(CONFIG_STM32WB_STM32WB55)
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# define STM32WB_IRQ_LCD (STM32WB_IRQ_FIRST + 49) /* 49: LCD global interrupt */
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#endif
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#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55)
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# define STM32WB_IRQ_QUADSPI (STM32WB_IRQ_FIRST + 50) /* 50: QUADSPI global interrupt */
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# define STM32WB_IRQ_AES1 (STM32WB_IRQ_FIRST + 51) /* 51: AES1 crypto global interrupt */
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#endif
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#define STM32WB_IRQ_AES2 (STM32WB_IRQ_FIRST + 52) /* 52: AES2 crypto global interrupt */
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#define STM32WB_IRQ_RNG (STM32WB_IRQ_FIRST + 53) /* 53: RNG global interrupt */
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#define STM32WB_IRQ_FPU (STM32WB_IRQ_FIRST + 54) /* 54: FPU global interrupt */
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#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55)
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# define STM32WB_IRQ_DMA2CH1 (STM32WB_IRQ_FIRST + 55) /* 55: DMA2 Channel 1 global interrupt */
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# define STM32WB_IRQ_DMA2CH2 (STM32WB_IRQ_FIRST + 56) /* 56: DMA2 Channel 2 global interrupt */
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# define STM32WB_IRQ_DMA2CH3 (STM32WB_IRQ_FIRST + 57) /* 57: DMA2 Channel 3 global interrupt */
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# define STM32WB_IRQ_DMA2CH4 (STM32WB_IRQ_FIRST + 58) /* 58: DMA2 Channel 4 global interrupt */
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# define STM32WB_IRQ_DMA2CH5 (STM32WB_IRQ_FIRST + 59) /* 59: DMA2 Channel 5 global interrupt */
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# define STM32WB_IRQ_DMA2CH6 (STM32WB_IRQ_FIRST + 60) /* 60: DMA2 Channel 6 global interrupt */
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# define STM32WB_IRQ_DMA2CH7 (STM32WB_IRQ_FIRST + 61) /* 61: DMA2 Channel 7 global interrupt */
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#endif
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#define STM32WB_IRQ_DMAMUX1 (STM32WB_IRQ_FIRST + 62) /* 62: DMAMUX1 overrun interrupt */
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#define STM32WB_IRQ_NEXTINTS 63
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/* (EXTI interrupts do not use IRQ numbers) */
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#define NR_IRQS (STM32WB_IRQ_FIRST + STM32WB_IRQ_NEXTINTS)
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif /* __ARCH_ARM_INCLUDE_STM32WB_STM32WB_IRQ_H */
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