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nuttx/Documentation/platforms/risc-v/k230/index.rst

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risc-v: Initial support for CanMV-k230 board and K230 chip The code is mainly derived from the NuttX qemu-rv/rv-virt codebase. Major changes: - boards/Kconfig: add new BOARD_K230_CANMV - arch/risc-v/Kconfig: add new CHIP_K230 chip and ARCH_RV_MMIO_BITS - arch/risc-v/src/common/riscv_mtimer.c: use ARCH_RV_MMIO_BITS to select MMIO access width New additions: - arch/risc-v/include/k230/: k230 SoC definitions - arch/risc-v/src/k230/: k230 SoC sources - boards/risc-v/k230/canmv230/: CanMV-K230 board sources and configs - Documentation/platforms/risc-v/k230/: simple doc Note that only FLAT build works for canmv230 now. This PR has changes in RiscV common layer thus may affect other RiscV ports It changes the mtime/mtimecmp access control from using config ARCH_RV64 to newly intorduced config ARCH_RV_MMIO_BITS. Original design uses ARCH_RV64 to select 64bit MMIO in riscv_mtimer.c, this can't cope with the situation with K230 --- it has ARCH_RV64 but only can do 32bit MMIO. So a new ARCH_RV_MMIO_BITS config has been introduced. Its value depicts the MMIO width in bits. The MMIO_BITS defaults to 32/64 for RV32/ RV64 respectively. This allows the macro to replace current use of ARCH_RV64 in riscv_mtimer.c. The new MMIO_BITS config is a derived one, and for RiscV chips with equal CPU and MMIO widths there is no need to explicitly set it as the default rule will do that. Only chips with different CPU and MMIO widths need set it in Kconfig. So by design this change should be safe but RiscV ports should be checked. "ostest" verification has been done for: - canmv230/nsh - rv-vivt/nsh - rv-virt/nsh64 configuration generation and manual check of derived RV_MMIO_BITS has been done for: - star64/nsh - arty_a7/nsh - bl602evb/nsh Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2023-12-13 03:59:21 +01:00
=============
Kendryte K230
=============
risc-v/k230: update documents added brief features list for K230 chip updated CanMV230 board docs for NUTTSBI config usage Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-01-20 03:51:53 +01:00
The `Kendryte K230 <https://www.canaan.io/product/k230>`_ SoC contains two 64 bit RV64GC CPUs based on T-Head C908 IP core for embedded IoT applications.
- **CPU1:** RISC-V Core, 1.6GHz, 32KB I-cache, 32KB D-cache, 256KB L2 Cache, 128bit RVV 1.0 support
- **CPU0:** RISC-V Core, 0.8GHz, 32KB I-cache, 32KB D-cache, 256KB L2 Cache
- **KPU:** INT8 and INT16 Inference performance: Restnet-50>85fps@INT8, Mobilenet_v2 >670fps@INT8, YoloV5S>38fps@INT8
- **DPU:** for 3D structured light, resolution is up to 1920*1080
- **RAM:** 32-bit LPDDR4 / DDR4 / LPDDR3 / DDR3
- **Video Codec:** H.264, H.265 and JPEG support;
- **Video Input:** 3 x MIPI-CSI
- **Video Output:** 1 x MIPI DSI
- **USB:** USB-OTG 2.0 x 2
- **Security:** TRNG, OTP
- **Peripherals:** 5xUART, 5xI2C, 6xPWM, 64xGPIO+8xPMU, 2xSDxC:SD3.0, 3xSPI, WDT/RTC/Timer
See more details from above vendor's website.
risc-v: Initial support for CanMV-k230 board and K230 chip The code is mainly derived from the NuttX qemu-rv/rv-virt codebase. Major changes: - boards/Kconfig: add new BOARD_K230_CANMV - arch/risc-v/Kconfig: add new CHIP_K230 chip and ARCH_RV_MMIO_BITS - arch/risc-v/src/common/riscv_mtimer.c: use ARCH_RV_MMIO_BITS to select MMIO access width New additions: - arch/risc-v/include/k230/: k230 SoC definitions - arch/risc-v/src/k230/: k230 SoC sources - boards/risc-v/k230/canmv230/: CanMV-K230 board sources and configs - Documentation/platforms/risc-v/k230/: simple doc Note that only FLAT build works for canmv230 now. This PR has changes in RiscV common layer thus may affect other RiscV ports It changes the mtime/mtimecmp access control from using config ARCH_RV64 to newly intorduced config ARCH_RV_MMIO_BITS. Original design uses ARCH_RV64 to select 64bit MMIO in riscv_mtimer.c, this can't cope with the situation with K230 --- it has ARCH_RV64 but only can do 32bit MMIO. So a new ARCH_RV_MMIO_BITS config has been introduced. Its value depicts the MMIO width in bits. The MMIO_BITS defaults to 32/64 for RV32/ RV64 respectively. This allows the macro to replace current use of ARCH_RV64 in riscv_mtimer.c. The new MMIO_BITS config is a derived one, and for RiscV chips with equal CPU and MMIO widths there is no need to explicitly set it as the default rule will do that. Only chips with different CPU and MMIO widths need set it in Kconfig. So by design this change should be safe but RiscV ports should be checked. "ostest" verification has been done for: - canmv230/nsh - rv-vivt/nsh - rv-virt/nsh64 configuration generation and manual check of derived RV_MMIO_BITS has been done for: - star64/nsh - arty_a7/nsh - bl602evb/nsh Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2023-12-13 03:59:21 +01:00
Supported Boards
================
.. toctree::
:glob:
:maxdepth: 1
boards/*/*
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