409 lines
12 KiB
C
409 lines
12 KiB
C
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/****************************************************************************
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* drivers/video/isx019_reg.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __DRIVERS_VIDEO_ISX019_REG_H
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#define __DRIVERS_VIDEO_ISX019_REG_H
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* FPGA I2C setting */
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#define FPGA_I2C_SLVADDR (0x1b)
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#define FPGA_I2C_SLVADDR_LEN (7)
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#define FPGA_I2C_REGSIZE_MAX (1)
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#define FPGA_I2C_REGADDR_LEN (1)
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#define FPGA_I2C_FREQUENCY (100000) /* Standard mode : 100kHz */
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/* FPGA I2C offset */
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#define FPGA_I2C_OFFSET_ADDR (0)
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#define FPGA_I2C_OFFSET_WRITEDATA (1)
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#define FPGA_I2C_OFFSET_READDATA (0)
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/* FPGA register address */
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#define FPGA_RESET (0x00)
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#define FPGA_DATA_OUTPUT (0x01)
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#define FPGA_FORMAT_AND_SCALE (0x02)
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#define FPGA_FPS_AND_THUMBNAIL (0x03)
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#define FPGA_CLIP_SIZE (0x04)
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#define FPGA_CLIP_TOP (0x05)
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#define FPGA_CLIP_LEFT (0x06)
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#define FPGA_DQT_ADDRESS (0x07)
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#define FPGA_DQT_SELECT (0x08)
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#define FPGA_DQT_DATA (0x09)
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#define FPGA_DQT_CALC_ADDRESS (0x0A)
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#define FPGA_DQT_CALC_SELECT (0x0B)
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#define FPGA_DQT_CALC_DATA (0x0C)
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#define FPGA_ACTIVATE (0x0D)
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#define FPGA_PIN_OUTPUT_SELECT (0x20)
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#define FPGA_PIN_STATUS (0x21)
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#define FPGA_VERSION (0x30)
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/* value for setting to FPGA register */
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#define FPGA_RESET_ENABLE (0x00)
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#define FPGA_RESET_RELEASE (0x01)
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#define FPGA_DATA_OUTPUT_START (0x01)
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#define FPGA_DATA_OUTPUT_STOP (0x00)
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#define FPGA_FORMAT_RGB (0x00)
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#define FPGA_FORMAT_YUV (0x01)
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#define FPGA_FORMAT_JPEG (0x02)
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#define FPGA_FORMAT_THUMBNAIL (0x03)
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#define FPGA_SCALE_1280_960 (0<<4)
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#define FPGA_SCALE_640_480 (1<<4)
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#define FPGA_SCALE_320_240 (2<<4)
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#define FPGA_SCALE_160_120 (3<<4)
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#define FPGA_FPS_BITS (0x03)
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#define FPGA_FPS_1_1 (0x00)
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#define FPGA_FPS_1_2 (0x01)
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#define FPGA_FPS_1_3 (0x02)
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#define FPGA_FPS_1_4 (0x03)
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#define FPGA_THUMBNAIL_SCALE_1_1 (0<<4)
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#define FPGA_THUMBNAIL_SCALE_1_2 (1<<4)
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#define FPGA_THUMBNAIL_SCALE_1_4 (2<<4)
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#define FPGA_THUMBNAIL_SCALE_1_8 (3<<4)
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#define FPGA_CLIP_NON (0x00)
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#define FPGA_CLIP_1280_720 (0x01)
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#define FPGA_CLIP_640_360 (0x02)
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#define FPGA_CLIP_UNIT (8)
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#define FPGA_DQT_READ (0<<6)
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#define FPGA_DQT_WRITE (1<<6)
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#define FPGA_DQT_CURRENT (0<<7)
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#define FPGA_DQT_BUFFER (1<<7)
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#define FPGA_DQT_LUMA (0x00)
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#define FPGA_DQT_CHROMA (0x01)
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#define FPGA_ACTIVATE_REQUEST (0x01)
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#define FPGA_PIN_OUTPUT_EXBUSY (0x00)
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#define FPGA_PIN_OUTPUT_ERROR (0x01)
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#define FPGA_PIN_STATUS_EXBUSY (1<<0)
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#define FPGA_PIN_STATUS_ERROR (1<<4)
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/* ISX019 I2C setting */
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#define ISX019_I2C_SLVADDR (0x1a)
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#define ISX019_I2C_SLVADDR_LEN (7)
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#define ISX019_I2C_REGSIZE_MAX (4)
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#define ISX019_I2C_REGADDR_LEN (4)
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#define ISX019_I2C_FREQUENCY (100000) /* Standard mode : 100kHz */
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/* Offset of ISX019 I2C command format */
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#define ISX019_I2C_OFFSET_TOTALLEN (0)
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#define ISX019_I2C_OFFSET_CMDNUM (1)
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#define ISX019_I2C_OFFSET_CMDLEN (2)
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#define ISX019_I2C_OFFSET_CMD (3)
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#define ISX019_I2C_OFFSET_CATEGORY (4)
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#define ISX019_I2C_OFFSET_ADDRESS_H (5)
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#define ISX019_I2C_OFFSET_ADDRESS_L (6)
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#define ISX019_I2C_OFFSET_WRITEDATA (7)
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#define ISX019_I2C_OFFSET_READSIZE (7)
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#define ISX019_I2C_OFFSET_FLASHCODE1 (4)
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#define ISX019_I2C_OFFSET_FLASHCODE2 (5)
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#define ISX019_I2C_OFFSET_FLASHCODE3 (6)
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#define ISX019_I2C_OFFSET_FLASHCODE4 (7)
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#define ISX019_I2C_OFFSET_STS (3)
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#define ISX019_I2C_OFFSET_READDATA (4)
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/* Command code of ISX019 I2C command format */
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#define ISX019_I2C_CMD_FLASHLOCK (0x00)
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#define ISX019_I2C_CMD_READ (0x01)
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#define ISX019_I2C_CMD_WRITE (0x02)
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#define ISX019_I2C_CMD_FLASHWRITE (0x05)
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/* Command length of ISX019 I2C command format */
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#define ISX019_I2C_TOTALLEN(s) (3 + (s))
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#define ISX019_I2C_WRREQ_LEN(s) (5 + (s))
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#define ISX019_I2C_WRRES_LEN (2)
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#define ISX019_I2C_WRREQ_TOTALLEN(s) ISX019_I2C_TOTALLEN(ISX019_I2C_WRREQ_LEN(s))
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#define ISX019_I2C_WRRES_TOTALLEN ISX019_I2C_TOTALLEN(ISX019_I2C_WRRES_LEN)
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#define ISX019_I2C_RDREQ_LEN (6)
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#define ISX019_I2C_RDRES_LEN(s) (2 + (s))
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#define ISX019_I2C_RDREQ_TOTALLEN ISX019_I2C_TOTALLEN(ISX019_I2C_RDREQ_LEN)
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#define ISX019_I2C_RDRES_TOTALLEN(s) ISX019_I2C_TOTALLEN(ISX019_I2C_RDRES_LEN(s))
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#define ISX019_I2C_FLOCKREQ_LEN (6)
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#define ISX019_I2C_FLOCKRES_LEN (2)
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#define ISX019_I2C_FLOCKREQ_TOTALLEN ISX019_I2C_TOTALLEN(ISX019_I2C_FLOCKREQ_LEN)
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#define ISX019_I2C_FLOCKRES_TOTALLEN ISX019_I2C_TOTALLEN(ISX019_I2C_FLOCKRES_LEN)
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#define ISX019_I2C_FWRREQ_LEN (2)
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#define ISX019_I2C_FWRRES_LEN (2)
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#define ISX019_I2C_FWRREQ_TOTALLEN ISX019_I2C_TOTALLEN(ISX019_I2C_FWRREQ_LEN)
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#define ISX019_I2C_FWRRES_TOTALLEN ISX019_I2C_TOTALLEN(ISX019_I2C_FWRRES_LEN)
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/* Constant value of codes for flash lock */
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#define ISX019_I2C_FLASHCODE1 (0x57)
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#define ISX019_I2C_FLASHCODE2 (0x52)
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#define ISX019_I2C_FLASHLOCK1 (0x44)
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#define ISX019_I2C_FLASHLOCK2 (0x53)
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#define ISX019_I2C_FLASHUNLOCK1 (0x45)
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#define ISX019_I2C_FLASHUNLOCK2 (0x4e)
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/* Status code of I2C command format */
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#define ISX019_I2C_STS_OK (0x01)
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#define ISX019_I2C_STS_ERR_CMD (0xf1)
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#define ISX019_I2C_STS_ERR_CAT (0xf2)
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#define ISX019_I2C_STS_ERR_ADDR (0xf3)
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#define ISX019_I2C_STS_ERR_ACCESS (0xf4)
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#define ISX019_I2C_STS_ERR_BYTE (0xf7)
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#define ISX019_I2C_STS_ERR_FLASH (0xfa)
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/* Category of ISX019 register */
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#define CAT_VERSION (0x00)
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#define CAT_CONFIG (0x01)
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#define CAT_SYSCOM (0x06)
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#define CAT_OTP (0x08)
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#define CAT_AUTOCTRL (0x0c)
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#define CAT_SMCFG (0x0f)
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#define CAT_CATAE (0x13)
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#define CAT_AEDGRM (0x14)
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#define CAT_AEWD (0x15)
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#define CAT_AECOM (0x18)
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#define CAT_AESOUT (0x19)
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#define CAT_CATAWB (0x21)
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#define CAT_AWB_USERTYPE (0x26)
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#define CAT_AUTOCOM (0x2c)
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#define CAT_AWBSOUT (0x31)
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#define CAT_PICTTUNE (0x34)
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#define CAT_PICTGAMMA (0x41)
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/* Offset of ISX019 register */
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/* For CAT_VERSION */
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#define ROM_VERSION (0x0000)
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/* For CAT_CONFIG */
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#define MODE_SENSSEL (0x0000)
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#define MODE_POSTSEL (0x0001)
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#define MODE_SENSPOST_SEL (0x0002)
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#define MODE_IOSEL (0x0003)
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#define REVERSE (0x0008)
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/* For CAT_SYSCOM */
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#define DEVSTS (0x0001)
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/* For CAT_OTP */
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#define CHIP_ID (0x0000)
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#define CHIP_ID_LEN (11)
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/* For CAT_AUTOCTRL */
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#define AEWEIGHTMODE (0x0000)
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/* For CAT_CATAE */
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#define AEMODE (0x0000)
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#define SHT_PRIMODE (0x0008)
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#define GAIN_PRIMODE (0x000c)
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/* For CAT_AEDGRM */
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#define SHTCTRLVAL1 (0x0008)
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#define SHTCTRLVAL2 (0x0010)
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#define SHTCTRLVAL3 (0x0018)
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#define SHTCTRLVAL4 (0x0020)
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#define SHTCTRLVAL5 (0x0028)
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#define MAXFRMEXP (0x007b)
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#define EVSEL (0x009c)
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/* For CAT_AEWD */
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#define AEWDMODE (0x0000)
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#define AEWEIGHTMODE_WD (0x0001)
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/* For CAT_AECOM */
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#define GAIN_LEVEL (0x0036)
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/* For CAT_AESOUT */
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#define SHT_TIME (0x01cc)
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#define V_TIME (0x01d0)
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/* For CAT_CATAWB */
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#define AWBMODE (0x0000)
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#define AWBUSER_NO (0x000a)
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/* For CAT_AWB_USERTYPE */
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#define USER0_R (0x0000)
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#define USER0_B (0x0002)
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#define USER1_R (0x000c)
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#define USER1_B (0x000e)
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#define USER2_R (0x0018)
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#define USER2_B (0x001a)
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#define USER3_R (0x0024)
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#define USER3_B (0x0026)
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#define USER4_R (0x0030)
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#define USER4_B (0x0032)
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/* For CAT_AUTOCOM */
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#define CONT_R (0x0006)
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#define CONT_B (0x0008)
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/* For CAT_AWBSOUT */
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#define AWBSTS (0x0000)
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/* For CAT_PICTTUNE */
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#define UISHARPNESS (0x0000)
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#define UICONTRAST (0x0001)
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#define UIBRIGHTNESS (0x0002)
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#define UIHUE (0x0004)
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#define UISATURATION (0x0005)
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/* For CAT_PICTGAMMA */
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#define GAM_KNOT_C0 (0x0000)
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#define GAM_KNOT_C8 (0x0010)
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#define GAM_KNOT_C9 (0x0012)
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#define GAM_KNOT_C10 (0x0014)
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#define GAM_KNOT_C11 (0x0016)
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#define NR_GAM_KNOT_LOWINPUT (9)
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#define NR_GAM_KNOT_HIGHINPUT (16)
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#define GAM_LOWINPUT_INTERVAL (double)(32.0 / 4096.0)
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#define GAM_HIGHINPUT_INTERVAL (double)(256.0 / 4096.0)
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#define GAM_OUTPUT_SCALE (255)
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/* Definition for ISX019 register setting value */
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/* For drive mode */
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#define NOT_STREAM_SENS (0)
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#define NOT_STREAM_POST (0)
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#define NOT_STREAM_SENSPOST (0)
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#define NOT_STREAM_IO (0)
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#define NORM_30FPS_SENS (2)
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#define NORM_30FPS_POST (2)
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#define NORM_30FPS_SENSPOST (2)
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#define NORM_30FPS_IO (2)
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#define DOL2_30FPS_SENS (6)
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#define DOL2_30FPS_POST (2)
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#define DOL2_30FPS_SENSPOST (24)
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#define DOL2_30FPS_IO (2)
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#define DOL3_30FPS_SENS (44)
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#define DOL3_30FPS_POST (125)
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#define DOL3_30FPS_SENSPOST (160)
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#define DOL3_30FPS_IO (2)
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#define NORM_25FPS_SENS (3)
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#define NORM_25FPS_POST (8)
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#define NORM_25FPS_SENSPOST (8)
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#define NORM_25FPS_IO (2)
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#define DOL2_25FPS_SENS (7)
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#define DOL2_25FPS_POST (8)
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#define DOL2_25FPS_SENSPOST (30)
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#define DOL2_25FPS_IO (2)
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||
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||
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#define DOL3_25FPS_SENS (45)
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||
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#define DOL3_25FPS_POST (131)
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||
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#define DOL3_25FPS_SENSPOST (166)
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#define DOL3_25FPS_IO (2)
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||
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||
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/* For REVERSE register(H_REVERSE and V_REVERSE) */
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||
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#define H_REVERSE (0x01)
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#define V_REVERSE (0x02)
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||
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||
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/* For AEWEIGHTMODE */
|
||
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||
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#define AEWEIGHT_AVERAGE (0x00)
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||
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#define AEWEIGHT_CENTER (0x01)
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||
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#define AEWEIGHT_SPOT (0x02)
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||
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|
#define AEWEIGHT_MATRIX (0x03)
|
||
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|
||
|
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/* For AEWEIGHTMODE(HDR) */
|
||
|
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|
||
|
|
#define AEWEIGHTHDR_AVERAGE (0x00)
|
||
|
|
#define AEWEIGHTHDR_CENTER (0x05)
|
||
|
|
#define AEWEIGHTHDR_SPOT (0x0a)
|
||
|
|
#define AEWEIGHTHDR_MATRIX (0x0f)
|
||
|
|
|
||
|
|
/* For AWBMODE */
|
||
|
|
|
||
|
|
#define AWBMODE_AUTO (0x00)
|
||
|
|
#define AWBMODE_HOLD (0x02)
|
||
|
|
#define AWBMODE_MANUAL (0x04)
|
||
|
|
|
||
|
|
/* For AEMODE */
|
||
|
|
|
||
|
|
#define AEMODE_AUTO (0x00)
|
||
|
|
#define AEMODE_HOLD (0x01)
|
||
|
|
|
||
|
|
/* For AEWDMODE */
|
||
|
|
|
||
|
|
#define AEWDMODE_AUTO (0x00)
|
||
|
|
#define AEWDMODE_HDR (0x01)
|
||
|
|
#define AEWDMODE_NORMAL (0x02)
|
||
|
|
|
||
|
|
/* For AWBSTS */
|
||
|
|
|
||
|
|
#define AWBSTS_STABLE (0x02)
|
||
|
|
#define AWBSTS_AEWAIT (0x06)
|
||
|
|
|
||
|
|
/* For USERX_R, USERX_B */
|
||
|
|
|
||
|
|
#define RED_INCANDESCENT (0x115f)
|
||
|
|
#define BLUE_INCANDESCENT (0x0e40)
|
||
|
|
#define RED_FLUORESCENT (0x0daf)
|
||
|
|
#define BLUE_FLUORESCENT (0x1250)
|
||
|
|
#define RED_DAYLIGHT (0x0b81)
|
||
|
|
#define BLUE_DAYLIGHT (0x1832)
|
||
|
|
#define RED_CLOUDY (0x0a4f)
|
||
|
|
#define BLUE_CLOUDY (0x1bc5)
|
||
|
|
#define RED_SHADE (0x0a4f)
|
||
|
|
#define BLUE_SHADE (0x1bc5)
|
||
|
|
|
||
|
|
#endif /* __DRIVERS_VIDEO_ISX019_REG_H */
|