193 lines
10 KiB
C
193 lines
10 KiB
C
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/************************************************************************************
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* arch/arm/src/stm32/stm32_i2c.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32_STM32_I2C_H
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#define __ARCH_ARM_SRC_STM32_STM32_I2C_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include "chip.h"
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */
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#define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */
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#define STM32_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */
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#define STM32_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */
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#define STM32_I2C_DR_OFFSET 0x0010 /* Data register (16-bit) */
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#define STM32_I2C_SR1_OFFSET 0x0014 /* Status register 1 (16-bit) */
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#define STM32_I2C_SR2_OFFSET 0x0018 /* Status register 2 (16-bit) */
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#define STM32_I2C_CCR_OFFSET 0x001c /* Clock control register (16-bit) */
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#define STM32_I2C_TRISE_OFFSET 0x0020 /* TRISE Register (16-bit) */
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/* Register Addresses ***************************************************************/
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#if STM32_NI2C > 0
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# define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET)
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# define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET)
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# define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET)
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# define STM32_I2C1_OAR2 (STM32_I2C1_BASE+STM32_I2C_OAR2_OFFSET)
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# define STM32_I2C1_DR (STM32_I2C1_BASE+STM32_I2C_DR_OFFSET)
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# define STM32_I2C1_SR1 (STM32_I2C1_BASE+STM32_I2C_SR1_OFFSET)
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# define STM32_I2C1_SR2 (STM32_I2C1_BASE+STM32_I2C_SR2_OFFSET)
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# define STM32_I2C1_CCR (STM32_I2C1_BASE+STM32_I2C_CCR_OFFSET)
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# define STM32_I2C1_TRISE (STM32_I2C1_BASE+STM32_I2C_TRISE_OFFSET)
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#endif
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#if STM32_NI2C > 1
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# define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET)
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# define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET)
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# define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET)
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# define STM32_I2C2_OAR2 (STM32_I2C2_BASE+STM32_I2C_OAR2_OFFSET)
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# define STM32_I2C2_DR (STM32_I2C2_BASE+STM32_I2C_DR_OFFSET)
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# define STM32_I2C2_SR1 (STM32_I2C2_BASE+STM32_I2C_SR1_OFFSET)
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# define STM32_I2C2_SR2 (STM32_I2C2_BASE+STM32_I2C_SR2_OFFSET)
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# define STM32_I2C2_CCR (STM32_I2C2_BASE+STM32_I2C_CCR_OFFSET)
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# define STM32_I2C2_TRISE (STM32_I2C2_BASE+STM32_I2C_TRISE_OFFSET)
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#endif
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/* Register Bitfield Definitions ****************************************************/
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/* Control register 1 */
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#define I2C_CR1_PE (1 << 0) /* Bit 0: Peripheral Enable*/
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#define I2C_CR1_SMBUS (1 << 1) /* Bit 1: SMBus Mode */
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#define I2C_CR1_SMBTYPE (1 << 3) /* Bit 3: SMBus Type */
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#define I2C_CR1_ENARP (1 << 4) /* Bit 4: ARP Enable */
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#define I2C_CR1_ENPEC (1 << 5) /* Bit 5: PEC Enable */
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#define I2C_CR1_ENGC (1 << 6) /* Bit 6: General Call Enable */
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#define I2C_CR1_NOSTRETCH (1 << 7) /* Bit 7: Clock Stretching Disable (Slave mode) */
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#define I2C_CR1_START (1 << 8) /* Bit 8: Start Generation */
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#define I2C_CR1_STOP (1 << 9) /* Bit 9: Stop Generation */
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#define I2C_CR1_ACK (1 << 10) /* Bit 10: Acknowledge Enable */
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#define I2C_CR1_POS (1 << 11) /* Bit 11: Acknowledge/PEC Position (for data reception) */
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#define I2C_CR1_PEC (1 << 12) /* Bit 12: Packet Error Checking */
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#define I2C_CR1_ALERT (1 << 13) /* Bit 13: SMBus Alert */
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#define I2C_CR1_SWRST (1 << 15) /* Bit 15: Software Reset */
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/* Control register 2 */
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#define I2C_CR2_FREQ_SHIFT (0) /* Bits 5-0: Peripheral Clock Frequency */
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#define I2C_CR2_FREQ_MASK (0x3f << I2C_CR2_FREQ_SHIFT)
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#define I2C_CR2_ITERREN (1 << 8) /* Bit 8: Error Interrupt Enable */
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#define I2C_CR2_ITEVTEN (1 << 9) /* Bit 9: Event Interrupt Enable */
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#define I2C_CR2_ITBUFEN (1 << 10 /* Bit 10: Buffer Interrupt Enable */
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#define I2C_CR2_DMAEN (1 << 11) /* Bit 11: DMA Requests Enable */
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#define I2C_CR2_LAST (1 << 12) /* Bit 12: DMA Last Transfer */
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/* Own address register 1 */
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#define I2C_OAR1_ADD0 (1 << 0) /* Bit 0: Interface Address */
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#define I2C_OAR1_ADD8_SHIFT (1) /* Bits 7-1: Interface Address */
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#define I2C_OAR1_ADD8_MASK (0x007f << I2C_OAR1_ADD8_SHIFT)
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#define I2C_OAR1_ADD10_SHIFT (1) /* Bits 9-1: Interface Address (10-bit addressing mode)*/
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#define I2C_OAR1_ADD10_MASK (0x01ff << I2C_OAR1_ADD10_SHIFT)
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#define I2C_OAR1_ONE (1 << 14) /* Bit 14: Must be configured and kept at 1 */
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#define I2C_OAR1_ADDMODE (1 << 15) /* Bit 15: Addressing Mode (Slave mode) */
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/* Own address register 2 */
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#define I2C_OAR2_ENDUAL (1 << 0) /* Bit 0: Dual addressing mode enable */
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#define I2C_OAR2_ADD2_SHIFT (1) /* Bits 7-1: Interface address */
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#define I2C_OAR2_ADD2_MASK (0x7f << I2C_OAR2_ADD2_SHIFT)
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/* Data register */
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#define I2C_DR_SHIFT (0) /* Bits 7-0: 8-bit Data Register */
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#define I2C_DR_MASK (0x00ff << I2C_DR_SHIFT)
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/* Status register 1 */
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#define I2C_SR1_SB (1 << 0) /* Bit 0: Start Bit (Master mode) */
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#define I2C_SR1_ADDR (1 << 1) /* Bit 1: Address sent (master mode)/matched (slave mode) */
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#define I2C_SR1_BTF (1 << 2) /* Bit 2: Byte Transfer Finished */
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#define I2C_SR1_ADD10 (1 << 3) /* Bit 3: 10-bit header sent (Master mode) */
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#define I2C_SR1_STOPF (1 << 4) /* Bit 4: Stop detection (Slave mode) */
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#define I2C_SR1_RXNE (1 << 6) /* Bit 6: Data Register not Empty (receivers) */
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#define I2C_SR1_TXE (1 << 7) /* Bit 7: Data Register Empty (transmitters) */
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#define I2C_SR1_BERR (1 << 8) /* Bit 8: Bus Error */
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#define I2C_SR1_ARLO (1 << 9) /* Bit 9: Arbitration Lost (master mode) */
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#define I2C_SR1_AF (1 << 10) /* Bit 10: Acknowledge Failure */
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#define I2C_SR1_OVR (1 << 11) /* Bit 11: Overrun/Underrun */
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#define I2C_SR1_PECERR (1 << 12) /* Bit 12: PEC Error in reception */
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#define I2C_SR1_TIMEOUT (1 << 14) /* Bit 14: Timeout or Tlow Error */
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#define I2C_SR1_SMBALERT (1 << 15) /* Bit 15: SMBus Alert */
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/* Status register 2 */
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#define I2C_SR2_MSL (1 << 0) /* Bit 0: Master/Slave */
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#define I2C_SR2_BUSY (1 << 1) /* Bit 1: Bus Busy */
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#define I2C_SR2_TRA (1 << 2) /* Bit 2: Transmitter/Receiver */
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#define I2C_SR2_GENCALL (1 << 4) /* Bit 4: General Call Address (Slave mode) */
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#define I2C_SR2_SMBDEFAULT (1 << 5) /* Bit 5: SMBus Device Default Address (Slave mode) */
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#define I2C_SR2_SMBHOST (1 << 6) /* Bit 6: SMBus Host Header (Slave mode) */
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#define I2C_SR2_DUALF (1 << 7) /* Bit 7: Dual Flag (Slave mode) */
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#define I2C_SR2_PEC_SHIFT (1) /* Bits 15-8: Packet Error Checking Register */
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#define I2C_SR2_PEC_MASK (0xff << I2C_SR2_PEC_SHIFT)
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/* Clock control register */
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#define I2C_CCR_CCR_SHIFT (0) /* Bits 11-0: Clock Control Register in Fast/Standard mode (Master mode) */
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#define I2C_CCR_CCR_MASK (0x0fff << I2C_CCR_CCR_SHIFT)
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#define I2C_CCR_DUTY (1 << 14) /* Bit 14: Fast Mode Duty Cycle */
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#define I2C_CCR_FS (1 << 15) /* Bit 15: I2C Master Mode Selection */
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/* TRISE Register */
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#define I2C_TRISE_SHIFT (0) /* Bits 5-0: Maximum Rise Time in Fast/Standard mode (Master mode) */
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#define I2C_TRISE_MASK (0x3f << I2C_TRISE_SHIFT)
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_STM32_STM32_I2C_H */
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