117 lines
5.8 KiB
C
117 lines
5.8 KiB
C
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/************************************************************************************
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* arch/arm/src/stm32/stm32_rtc.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32_STM32_RTC_H
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#define __ARCH_ARM_SRC_STM32_STM32_RTC_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include "chip.h"
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define STM32_RTC_CRH_OFFSET 0x0000 /* RTC control register High (16-bit) */
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#define STM32_RTC_CRL_OFFSET 0x0004 /* RTC control register low (16-bit) */
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#define STM32_RTC_PRLH_OFFSET 0x0008 /* RTC prescaler load register high (16-bit) */
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#define STM32_RTC_PRLL_OFFSET 0x000c /* RTC prescaler load register low (16-bit) */
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#define STM32_RTC_DIVH_OFFSET 0x0010 /* RTC prescaler divider register high (16-bit) */
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#define STM32_RTC_DIVL_OFFSET 0x0014 /* RTC prescaler divider register low (16-bit) */
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#define STM32_RTC_CNTH_OFFSET 0x0018 /* RTC counter register high (16-bit) */
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#define STM32_RTC_CNTL_OFFSET 0x001c /* RTC counter register low (16-bit) */
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#define STM32_RTC_ALRH_OFFSET 0x0020 /* RTC alarm register high (16-bit) */
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#define STM32_RTC_ALRL_OFFSET 0x0024 /* RTC alarm register low (16-bit) */
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/* Register Addresses ***************************************************************/
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#define STM32_RTC_CRH (STM32_RTC_BASE+STM32_RTC_CRH_OFFSET)
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#define STM32_RTC_CRL (STM32_RTC_BASE+STM32_RTC_CRL_OFFSET)
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#define STM32_RTC_PRLH (STM32_RTC_BASE+STM32_RTC_PRLH_OFFSET)
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#define STM32_RTC_PRLL (STM32_RTC_BASE+STM32_RTC_PRLL_OFFSET)
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#define STM32_RTC_DIVH (STM32_RTC_BASE+STM32_RTC_DIVH_OFFSET)
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#define STM32_RTC_DIVL (STM32_RTC_BASE+STM32_RTC_DIVL_OFFSET)
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#define STM32_RTC_CNTH (STM32_RTC_BASE+STM32_RTC_CNTH_OFFSET)
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#define STM32_RTC_CNTL (STM32_RTC_BASE+STM32_RTC_CNTL_OFFSET)
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#define STM32_RTC_ALRH (STM32_RTC_BASE+STM32_RTC_ALRH_OFFSET)
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#define STM32_RTC_ALRL (STM32_RTC_BASE+STM32_RTC_ALRL_OFFSET)
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/* Register Bitfield Definitions ****************************************************/
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/* RTC control register High (16-bit) */
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#define RTC_CRH_SECIE (1 << 0) /* Bit 0 : Second Interrupt Enable*/
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#define RTC_CRH_ALRIE (1 << 1) /* Bit 1: Alarm Interrupt Enable*/
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#define RTC_CRH_OWIE (1 << 2) /* Bit 2: OverfloW Interrupt Enable*/
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/* RTC control register low (16-bit) */
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#define RTC_CRL_SECF (1 << 0) /* Bit 0: Second Flag*/
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#define RTC_CRL_ALRF (1 << 1) /* Bit 1: Alarm Flag*/
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#define RTC_CRL_OWF (1 << 2) /* Bit 2: Overflow Flag*/
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#define RTC_CRL_RSF (1 << 3) /* Bit 3: Registers Synchronized Flag*/
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#define RTC_CRL_CNF (1 << 4) /* Bit 4: Configuration Flag*/
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#define RTC_CRL_RTOFF (1 << 5) /* Bit 5: RTC operation OFF*/
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/* RTC prescaler load register high (16-bit) */
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#define RTC_PRLH_PRL_SHIFT (0) /* Bits 3-0: RTC Prescaler Reload Value High */
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#define RTC_PRLH_PRL_MASK (0x0f << RTC_PRLH_PRL_SHIFT)
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/* RTC prescaler divider register high (16-bit) */
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#define RTC_DIVH_RTC_DIV_SHIFT (0) /* Bits 3-0: RTC Clock Divider High */
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#define RTC_DIVH_RTC_DIV_MASK (0x0f << RTC_DIVH_RTC_DIV_SHIFT)
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_STM32_STM32_RTC_H */
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