2017-12-24 17:55:46 +01:00
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/****************************************************************************
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* arch/arm/src/lpc54xx/lpc54_dma.c
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*
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* Copyright (C) 2017 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <errno.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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#include "up_internal.h"
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#include "up_arch.h"
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2017-12-24 21:28:39 +01:00
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#include "chip/lpc54_inputmux.h"
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2017-12-24 17:55:46 +01:00
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#include "chip/lpc54_dma.h"
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#include "lpc54_enableclk.h"
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#include "lpc54_reset.h"
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#include "lpc54_dma.h"
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#ifdef CONFIG_LPC54_DMA
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/* This structure represents the state of one DMA channel */
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struct lpc54_dmach_s
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{
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bool inuse; /* True: The channel is in use */
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dma_callback_t callback; /* DMA completion callback function */
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void *arg; /* Argument to pass to the callback function */
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};
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/* This structure represents the state of the LPC54 DMA block */
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struct lpc54_dma_s
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{
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sem_t exclsem; /* For exclusive access to the DMA channel list */
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/* This is the state of each DMA channel */
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struct lpc54_dmach_s dmach[LPC54_DMA_NCHANNELS];
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};
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* The state of the LPC54 DMA block */
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static struct lpc54_dma_s g_dma;
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2017-12-24 21:28:39 +01:00
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/* The SRAMBASE register must be configured with an address (preferably in
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* on-chip SRAM) where DMA descriptors will be stored. Each DMA channel has
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* an entry for the channel descriptor in the SRAM table.
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2017-12-24 17:55:46 +01:00
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*/
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2017-12-24 21:28:39 +01:00
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static struct lpc54_dmachan_desc_s g_dma_desc[LPC54_DMA_NCHANNELS];
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2017-12-24 17:55:46 +01:00
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: lpc54_dma_dispatch
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*
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* Description:
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* Dispatch a DMA interrupt.
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static void lpc54_dma_dispatch(int ch, int result)
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{
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struct lpc54_dmach_s *dmach;
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/* Yes.. Is this channel assigned? Is there a callback function? */
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dmach = &g_dma.dmach[ch];
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if (dmach->inuse && dmach->callback != NULL)
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{
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/* Perform the callback */
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2017-12-24 21:28:39 +01:00
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dmach->callback(ch, dmach->arg, result);
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2017-12-24 17:55:46 +01:00
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}
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/* Disable this channel, mask any further interrupts for this channel, and
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* clear any pending interrupts.
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*/
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2017-12-24 21:28:39 +01:00
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lpc54_dmastop(ch);
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2017-12-24 17:55:46 +01:00
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}
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/****************************************************************************
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* Name: lpc54_dma_interrupt
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*
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* Description:
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* The common DMA interrupt handler.
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static int lpc54_dma_interrupt(int irq, FAR void *context, FAR void *arg)
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{
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uint32_t pending;
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uint32_t bitmask;
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int ch;
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/* Check for pending DMA channel error interrupts */
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pending = getreg32(LPC54_DMA_ERRINT0);
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putreg32(pending, LPC54_DMA_ERRINT0);
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for (ch = 0; pending != 0 && ch < LPC54_DMA_NCHANNELS; ch++)
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{
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/* Check if there is a pending error on this channel */
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bitmask = DMA_CHANNEL((uint32_t)ch);
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if ((pending & bitmask) != 0)
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{
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/* Dispatch the DMA channel error event */
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lpc54_dma_dispatch(ch, -EIO);
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pending &= ~bitmask;
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}
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}
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/* Check for pending DMA interrupt A events */
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pending = getreg32(LPC54_DMA_INTA0);
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putreg32(pending, LPC54_DMA_INTA0);
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for (ch = 0; pending != 0 && ch < LPC54_DMA_NCHANNELS; ch++)
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{
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/* Check if there is a pending interrupt A on this channel */
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bitmask = DMA_CHANNEL((uint32_t)ch);
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if ((pending & bitmask) != 0)
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{
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/* Dispatch DMA channel interrupt A event */
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lpc54_dma_dispatch(ch, OK);
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pending &= ~bitmask;
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}
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}
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#if 0 /* interrupt B is not used */
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/* Check for pending DMA interrupt B events */
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pending = getreg32(LPC54_DMA_INTB0);
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putreg32(pending, LPC54_DMA_INTB0);
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for (ch = 0; pending != 0 && ch < LPC54_DMA_NCHANNELS; ch++)
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{
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/* Check if there is a pending interrupt A on this channel */
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bitmask = DMA_CHANNEL((uint32_t)ch);
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if ((pending & bitmask) != 0)
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{
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/* Dispatch DMA channel interrupt B event */
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lpc54_dma_dispatch(ch, OK);
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pending &= ~bitmask;
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}
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}
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#endif
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return OK;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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2018-11-20 15:08:28 +01:00
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* Name: up_dma_initialize
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2017-12-24 17:55:46 +01:00
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*
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* Description:
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2017-12-25 17:45:47 +01:00
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* Initialize the DMA subsystem. Called from up_initialize() early in the
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* boot-up sequence. Prototyped in up_internal.h.
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2017-12-24 17:55:46 +01:00
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*
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* Returned Value:
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2017-12-25 17:45:47 +01:00
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* None
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2017-12-24 17:55:46 +01:00
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*
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****************************************************************************/
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2018-11-20 15:08:28 +01:00
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void weak_function up_dma_initialize(void)
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2017-12-24 17:55:46 +01:00
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{
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int ret;
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/* Enable clocking to the DMA block */
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lpc54_dma_enableclk();
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/* Reset the DMA peripheral */
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lpc54_reset_dma();
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/* Disable and clear all DMA interrupts */
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putreg32(DMA_ALL_CHANNELS, LPC54_DMA_INTENCLR0);
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putreg32(DMA_ALL_CHANNELS, LPC54_DMA_ERRINT0);
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putreg32(DMA_ALL_CHANNELS, LPC54_DMA_INTA0);
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putreg32(DMA_ALL_CHANNELS, LPC54_DMA_INTB0);
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/* Initialize the DMA state structure */
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nxsem_init(&g_dma.exclsem, 0, 1);
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2017-12-24 21:28:39 +01:00
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/* Set the SRAMBASE to the beginning a array of DMA descriptors, one for
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* each DMA channel.
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*/
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putreg32((uint32_t)g_dma_desc, LPC54_DMA_SRAMBASE);
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2017-12-24 17:55:46 +01:00
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/* Attach and enable the DMA interrupt handler */
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ret = irq_attach(LPC54_IRQ_DMA, lpc54_dma_interrupt, NULL);
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if (ret == OK)
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{
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up_enable_irq(LPC54_IRQ_DMA);
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}
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/* Enable the DMA controller */
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putreg32(DMA_CTRL_ENABLE, LPC54_DMA_CTRL);
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}
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/****************************************************************************
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2017-12-24 21:28:39 +01:00
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* Name: lpc54_dma_setup
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2017-12-24 17:55:46 +01:00
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*
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* Description:
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2017-12-24 21:28:39 +01:00
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* Configure DMA for one transfer.
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2017-12-24 17:55:46 +01:00
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*
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2017-12-24 21:28:39 +01:00
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* Input Parameters:
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* ch - DMA channel number
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* cfg - The content of the DMA channel configuration register. See
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* peripheral channel definitions in chip/lpc54_dma.h. The
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* caller must provide all fields: PERIPHREQEN, TRIGPOL,
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* TRIGTYPE, TRIGBURST, BURSTPOWER, SRCBURSTWRAP, DSTBURSTWRAP,
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* and CHPRIORITY.
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* xfrcfg - The content of the DMA channel configuration register. See
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* peripheral channel definitions in chip/lpc54_dma.h. The
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* caller must provide all fields: WIDTH, SRCINC, and DSTINC.\
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* All of fields are managed by the DMA driver
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* trigsrc - See input mux DMA trigger ITRIG_INMUX_* definitions in
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* chip/lpc54_inputmux.h.
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* srcaddr - Source address of the DMA transfer
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* dstaddr - Destination address of the DMA transfer
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* nbytes - Number of bytes to transfer
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2017-12-24 17:55:46 +01:00
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*
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****************************************************************************/
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2017-12-24 21:28:39 +01:00
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int lpc54_dma_setup(int ch, uint32_t cfg, uint32_t xfrcfg, uint8_t trigsrc,
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uintptr_t srcaddr, uintptr_t dstaddr, size_t nbytes)
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2017-12-24 17:55:46 +01:00
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{
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2017-12-24 21:28:39 +01:00
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struct lpc54_dmach_s *dmach;
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uintptr_t base;
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uintptr_t regaddr;
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uint32_t nxfrs;
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uint32_t width;
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uint32_t incr;
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2017-12-24 17:55:46 +01:00
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int ret;
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2017-12-24 21:28:39 +01:00
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DEBUGASSERT((unsigned)ch < LPC54_DMA_NCHANNELS && nbytes < 4096);
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dmach = &g_dma.dmach[ch];
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/* Get exclusive access to the DMA data structures and interface */
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2017-12-24 17:55:46 +01:00
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2017-12-24 21:28:39 +01:00
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ret = nxsem_wait(&g_dma.exclsem);
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if (ret < 0)
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2017-12-24 17:55:46 +01:00
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{
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2017-12-24 21:28:39 +01:00
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return ret;
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2017-12-24 17:55:46 +01:00
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}
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2017-12-24 21:28:39 +01:00
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/* Make sure that the DMA channel is not in use */
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2017-12-24 17:55:46 +01:00
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2017-12-24 21:28:39 +01:00
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DEBUGASSERT(!dmach->inuse);
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if (dmach->inuse)
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2017-12-24 17:55:46 +01:00
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{
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2017-12-24 21:28:39 +01:00
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ret = -EBUSY;
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goto errout_with_exclsem;
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2017-12-24 17:55:46 +01:00
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}
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2017-12-24 21:28:39 +01:00
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dmach->inuse = true;
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2017-12-24 17:55:46 +01:00
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2017-12-24 21:28:39 +01:00
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/* Make sure that the trigger is not active */
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2017-12-24 17:55:46 +01:00
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2017-12-24 21:28:39 +01:00
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base = LPC54_DMA_CHAN_BASE(ch);
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putreg32(0, base + LPC54_DMA_CFG_OFFSET);
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2017-12-24 17:55:46 +01:00
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2017-12-24 21:28:39 +01:00
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/* Number of transfers */
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2017-12-24 17:55:46 +01:00
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2017-12-24 21:28:39 +01:00
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switch (xfrcfg & DMA_XFERCFG_WIDTH_MASK)
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{
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default:
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case DMA_XFERCFG_WIDTH_8BIT:
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width = 1;
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nxfrs = nbytes;
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break;
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2017-12-24 17:55:46 +01:00
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2017-12-24 21:28:39 +01:00
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case DMA_XFERCFG_WIDTH_16BIT:
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width = 2;
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nxfrs = ((nbytes + 1) >> 1);
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break;
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2017-12-24 17:55:46 +01:00
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2017-12-24 21:28:39 +01:00
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case DMA_XFERCFG_WIDTH_32BIT:
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width = 4;
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nxfrs = ((nbytes + 3) >> 2);
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break;
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}
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2017-12-24 17:55:46 +01:00
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2017-12-24 21:28:39 +01:00
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|
|
/* Check if the number of transfers can be performed */
|
2017-12-24 17:55:46 +01:00
|
|
|
|
2017-12-24 21:28:39 +01:00
|
|
|
if (nxfrs > LPC54_DMA_MAXXFRS)
|
|
|
|
{
|
|
|
|
return -E2BIG;
|
|
|
|
}
|
2017-12-24 17:55:46 +01:00
|
|
|
|
2017-12-24 21:28:39 +01:00
|
|
|
/* Set up the channel DMA descriptor */
|
2017-12-24 17:55:46 +01:00
|
|
|
|
2017-12-24 21:28:39 +01:00
|
|
|
g_dma_desc[ch].reserved = 0;
|
2017-12-24 17:55:46 +01:00
|
|
|
|
2017-12-24 21:28:39 +01:00
|
|
|
switch (cfg & DMA_XFERCFG_SRCINC_MASK)
|
|
|
|
{
|
|
|
|
default:
|
|
|
|
case DMA_XFERCFG_SRCINC_NONE:
|
|
|
|
incr = 0;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DMA_XFERCFG_SRCINC_1X:
|
|
|
|
incr = width;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DMA_XFERCFG_SRCINC_2X:
|
|
|
|
incr = width << 1;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DMA_XFERCFG_SRCINC_4X:
|
|
|
|
incr = width << 2;
|
|
|
|
incr = 0;
|
|
|
|
break;
|
|
|
|
}
|
2017-12-24 17:55:46 +01:00
|
|
|
|
2017-12-24 21:28:39 +01:00
|
|
|
g_dma_desc[ch].srcend = (uint32_t)srcaddr + nxfrs * incr;
|
2017-12-24 17:55:46 +01:00
|
|
|
|
2017-12-24 21:28:39 +01:00
|
|
|
switch (cfg & DMA_XFERCFG_DSTINC_MASK)
|
|
|
|
{
|
|
|
|
default:
|
|
|
|
case DMA_XFERCFG_DSTINC_NONE:
|
|
|
|
incr = 0;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DMA_XFERCFG_DSTINC_1X:
|
|
|
|
incr = width;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DMA_XFERCFG_DSTINC_2X:
|
|
|
|
incr = width << 1;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DMA_XFERCFG_DSTINC_4X:
|
|
|
|
incr = width << 2;
|
|
|
|
incr = 0;
|
|
|
|
break;
|
|
|
|
}
|
2017-12-24 17:55:46 +01:00
|
|
|
|
2017-12-24 21:28:39 +01:00
|
|
|
g_dma_desc[ch].dstend = (uint32_t)dstaddr + nxfrs * incr;
|
|
|
|
g_dma_desc[ch].link = 0;
|
2017-12-24 17:55:46 +01:00
|
|
|
|
2017-12-24 21:28:39 +01:00
|
|
|
/* Set the trigger source */
|
|
|
|
|
|
|
|
regaddr = LPC54_MUX_DMA_ITRIG_INMUX(ch);
|
|
|
|
putreg32(MUX_DMA_ITRIG_INMUX(trigsrc), regaddr);
|
|
|
|
|
|
|
|
/* Set the channel configuration register.
|
|
|
|
*
|
|
|
|
* PERIPHREQEN - Provided by caller
|
|
|
|
* TRIGPOL - Provided by caller
|
|
|
|
* TRIGTYPE - Provided by caller
|
|
|
|
* TRIGBURST - Provided by caller
|
|
|
|
* BURSTPOWER - Provided by caller
|
|
|
|
* SRCBURSTWRAP - Provided by caller
|
|
|
|
* DSTBURSTWRAP - Provided by caller
|
|
|
|
* CHPRIORITY - Provided by caller
|
|
|
|
*/
|
|
|
|
|
|
|
|
putreg32(cfg, base + LPC54_DMA_CFG_OFFSET);
|
|
|
|
|
|
|
|
/* Set the channel transfer configuration register
|
|
|
|
*
|
|
|
|
* CFGVALID - Current channel descriptor is valid.
|
|
|
|
* RELOAD - No reload
|
|
|
|
* SWTRIG - No software trigger
|
|
|
|
* CLRTRIG - Trigger cleared when descriptor is exhausted
|
|
|
|
* SETINTA - Use interrupt A
|
|
|
|
* SETINTB - Don't use interrupt B
|
|
|
|
* WIDTH - Provided by caller
|
|
|
|
* SRCINC - Provided by caller
|
|
|
|
* DSTINC - Provided by caller
|
|
|
|
* XFERCOUNT - Derived from with and nbytes
|
|
|
|
*/
|
|
|
|
|
|
|
|
xfrcfg &= ~(DMA_XFERCFG_RELOAD | DMA_XFERCFG_SWTRIG | DMA_XFERCFG_SETINTB |
|
|
|
|
DMA_XFERCFG_XFERCOUNT_MASK);
|
|
|
|
xfrcfg |= (DMA_XFERCFG_CFGVALID | DMA_XFERCFG_CLRTRIG | DMA_XFERCFG_SETINTA);
|
|
|
|
xfrcfg |= DMA_XFERCFG_XFERCOUNT(nxfrs);
|
|
|
|
putreg32(xfrcfg, base + LPC54_DMA_XFERCFG_OFFSET);
|
|
|
|
ret = OK;
|
|
|
|
|
|
|
|
errout_with_exclsem:
|
|
|
|
nxsem_post(&g_dma.exclsem);
|
|
|
|
return ret;
|
2017-12-24 17:55:46 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: lpc54_dmastart
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Start the DMA transfer
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2017-12-24 21:28:39 +01:00
|
|
|
int lpc54_dmastart(int ch, dma_callback_t callback, void *arg)
|
2017-12-24 17:55:46 +01:00
|
|
|
{
|
2017-12-24 21:28:39 +01:00
|
|
|
struct lpc54_dmach_s *dmach;
|
|
|
|
uintptr_t regaddr;
|
2017-12-24 17:55:46 +01:00
|
|
|
uint32_t bitmask;
|
|
|
|
|
2017-12-24 21:28:39 +01:00
|
|
|
DEBUGASSERT((unsigned)ch < LPC54_DMA_NCHANNELS);
|
|
|
|
dmach = &g_dma.dmach[ch];
|
|
|
|
DEBUGASSERT(dmach->inuse && callback != NULL);
|
2017-12-24 17:55:46 +01:00
|
|
|
|
|
|
|
/* Save the callback information */
|
|
|
|
|
|
|
|
dmach->callback = callback;
|
|
|
|
dmach->arg = arg;
|
|
|
|
|
|
|
|
/* Clear any pending DMA interrupts */
|
|
|
|
|
2017-12-24 21:28:39 +01:00
|
|
|
bitmask = DMA_CHANNEL(ch);
|
2017-12-24 17:55:46 +01:00
|
|
|
putreg32(bitmask, LPC54_DMA_ERRINT0);
|
|
|
|
putreg32(bitmask, LPC54_DMA_INTA0);
|
|
|
|
putreg32(bitmask, LPC54_DMA_INTB0);
|
|
|
|
|
2017-12-24 21:28:39 +01:00
|
|
|
/* Enable the channel and enable interrupt A and error interrupts. */
|
|
|
|
|
|
|
|
putreg32(bitmask, LPC54_DMA_ENABLESET0); /* Enable the channel */
|
|
|
|
putreg32(bitmask, LPC54_DMA_INTENSET0); /* Enable channel interrupts */
|
2017-12-24 17:55:46 +01:00
|
|
|
|
2017-12-24 21:28:39 +01:00
|
|
|
/* Enable the trigger for this channel */
|
2017-12-24 17:55:46 +01:00
|
|
|
|
2017-12-24 21:28:39 +01:00
|
|
|
regaddr = LPC54_DMA_CTLSTAT(ch);
|
|
|
|
modifyreg32(regaddr, 0, DMA_CTLSTAT_TRIG);
|
2017-12-24 17:55:46 +01:00
|
|
|
return OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: lpc54_dmastop
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Cancel the DMA. After lpc54_dmastop() is called, the DMA channel is
|
|
|
|
* reset and lpc54_dmasetup() must be called before lpc54_dmastart() can be
|
|
|
|
* called again
|
|
|
|
*
|
|
|
|
* This function will be called either by the user directly, by the user
|
|
|
|
* indirectly via lpc54_dmafree(), or from lpc54_dma_interrupt when the
|
|
|
|
* transfer completes.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2017-12-24 21:28:39 +01:00
|
|
|
void lpc54_dmastop(int ch)
|
2017-12-24 17:55:46 +01:00
|
|
|
{
|
2017-12-24 21:28:39 +01:00
|
|
|
struct lpc54_dmach_s *dmach;
|
2017-12-24 17:55:46 +01:00
|
|
|
uint32_t bitmask;
|
|
|
|
|
2017-12-24 21:28:39 +01:00
|
|
|
DEBUGASSERT((unsigned)ch < LPC54_DMA_NCHANNELS);
|
|
|
|
dmach = &g_dma.dmach[ch];
|
|
|
|
DEBUGASSERT(dmach->inuse);
|
2017-12-24 17:55:46 +01:00
|
|
|
|
|
|
|
/* Disable this channel and mask any further interrupts from the channel.
|
|
|
|
* this channel.
|
|
|
|
*/
|
2017-12-24 21:28:39 +01:00
|
|
|
|
|
|
|
bitmask = DMA_CHANNEL(ch);
|
|
|
|
putreg32(bitmask, LPC54_DMA_INTENCLR0); /* Disable channel interrupts */
|
|
|
|
putreg32(bitmask, LPC54_DMA_ENABLECLR0); /* Disable the channel */
|
2017-12-24 17:55:46 +01:00
|
|
|
|
|
|
|
/* Clear any pending interrupts for this channel */
|
|
|
|
|
|
|
|
putreg32(bitmask, LPC54_DMA_ERRINT0);
|
|
|
|
putreg32(bitmask, LPC54_DMA_INTA0);
|
|
|
|
putreg32(bitmask, LPC54_DMA_INTB0);
|
|
|
|
|
2017-12-24 21:28:39 +01:00
|
|
|
/* This channel is no longer in use */
|
2017-12-24 17:55:46 +01:00
|
|
|
|
2017-12-24 21:28:39 +01:00
|
|
|
g_dma.dmach[ch].inuse = false;
|
2017-12-24 17:55:46 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: lpc54_dmasample
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Sample DMA register contents
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
#ifdef CONFIG_DEBUG_DMA
|
2017-12-24 21:28:39 +01:00
|
|
|
void lpc54_dmasample(int ch, struct lpc54_dmaregs_s *regs)
|
2017-12-24 17:55:46 +01:00
|
|
|
{
|
|
|
|
uintptr_t base;
|
|
|
|
|
2017-12-24 21:28:39 +01:00
|
|
|
DEBUGASSERT((unsigned)ch < LPC54_DMA_NCHANNELS);
|
2017-12-24 17:55:46 +01:00
|
|
|
|
|
|
|
/* Sample the global DMA registers */
|
|
|
|
|
|
|
|
regs->gbl.ctrl = getreg32(LPC54_DMA_CTRL);
|
|
|
|
regs->gbl.intstat = getreg32(LPC54_DMA_INTSTAT);
|
|
|
|
regs->gbl.srambase = getreg32(LPC54_DMA_SRAMBASE);
|
|
|
|
regs->gbl.enableset0 = getreg32(LPC54_DMA_ENABLESET0);
|
|
|
|
regs->gbl.active0 = getreg32(LPC54_DMA_ACTIVE0);
|
|
|
|
regs->gbl.busy0 = getreg32(LPC54_DMA_BUSY0);
|
|
|
|
regs->gbl.errint0 = getreg32(LPC54_DMA_ERRINT0);
|
|
|
|
regs->gbl.intenset0 = getreg32(LPC54_DMA_INTENSET0);
|
|
|
|
regs->gbl.inta0 = getreg32(LPC54_DMA_INTA0);
|
|
|
|
regs->gbl.intb0 = getreg32(LPC54_DMA_INTB0);
|
|
|
|
|
|
|
|
/* Sample the DMA channel registers */
|
|
|
|
|
2017-12-24 21:28:39 +01:00
|
|
|
base = LPC54_DMA_CHAN_BASE(ch);
|
2017-12-24 17:55:46 +01:00
|
|
|
regs->ch.cfg = getreg32(base + LPC54_DMA_CFG_OFFSET);
|
|
|
|
regs->ch.ctlstat = getreg32(base + LPC54_DMA_CTLSTAT_OFFSET);
|
|
|
|
regs->ch.xfercfg = getreg32(base + LPC54_DMA_XFERCFG_OFFSET);
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_DEBUG_DMA */
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: lpc54_dmadump
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Dump previously sampled DMA register contents
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
#ifdef CONFIG_DEBUG_DMA
|
2017-12-24 21:28:39 +01:00
|
|
|
void lpc54_dmadump(int ch, const struct lpc54_dmaregs_s *regs,
|
|
|
|
const char *msg)
|
2017-12-24 17:55:46 +01:00
|
|
|
{
|
|
|
|
uintptr_t base;
|
|
|
|
|
2017-12-24 21:28:39 +01:00
|
|
|
DEBUGASSERT((unsigned)ch < LPC54_DMA_NCHANNELS && regs != NULL && msg != NULL);
|
2017-12-24 17:55:46 +01:00
|
|
|
|
|
|
|
/* Dump the sampled global DMA registers */
|
|
|
|
|
|
|
|
dmainfo("Global DMA Registers: %s\n", msg);
|
|
|
|
dmainfo(" CTRL[%08x]: %08lx\n",
|
|
|
|
LPC54_DMA_CTRL, (unsigned long)regs->gbl.ctrl);
|
|
|
|
dmainfo(" INTSTAT[%08x]: %08lx\n",
|
|
|
|
LPC54_DMA_INTSTAT, (unsigned long)regs->gbl.intstat);
|
|
|
|
dmainfo(" SRAMBASE[%08x]: %08lx\n",
|
|
|
|
LPC54_DMA_SRAMBASE, (unsigned long)regs->gbl.srambase);
|
|
|
|
dmainfo(" ENABLESET0[%08x]: %08lx\n",
|
|
|
|
LPC54_DMA_ENABLESET0, (unsigned long)regs->gbl.enableset0);
|
|
|
|
dmainfo(" ACTIVE0[%08x]: %08lx\n",
|
|
|
|
LPC54_DMA_ACTIVE0, (unsigned long)regs->gbl.active0);
|
|
|
|
dmainfo(" BUSY0[%08x]: %08lx\n",
|
|
|
|
LPC54_DMA_BUSY0, (unsigned long)regs->gbl.busy0);
|
|
|
|
dmainfo(" ERRINT0[%08x]: %08lx\n",
|
|
|
|
LPC54_DMA_ERRINT0, (unsigned long)regs->gbl.errint0);
|
|
|
|
dmainfo(" INTENSET0[%08x]: %08lx\n",
|
|
|
|
LPC54_DMA_INTENSET0, (unsigned long)regs->gbl.intenset0);
|
|
|
|
dmainfo(" INTA0[%08x]: %08lx\n",
|
|
|
|
LPC54_DMA_INTA0, (unsigned long)regs->gbl.inta0);
|
|
|
|
dmainfo(" INTB0[%08x]: %08lx\n",
|
|
|
|
LPC54_DMA_INTB0, (unsigned long)regs->gbl.intb0);
|
|
|
|
|
|
|
|
/* Dump the DMA channel registers */
|
|
|
|
|
2017-12-24 21:28:39 +01:00
|
|
|
base = LPC54_DMA_CHAN_BASE(ch);
|
2017-12-24 17:55:46 +01:00
|
|
|
|
2017-12-24 21:28:39 +01:00
|
|
|
dmainfo("Channel DMA Registers: %d\n", ch);
|
2017-12-24 17:55:46 +01:00
|
|
|
|
|
|
|
dmainfo(" CFG[%08x]: %08lx\n",
|
|
|
|
base + LPC54_DMA_CFG_OFFSET, (unsigned long)regs->ch.cfg);
|
|
|
|
dmainfo(" CTLSTAT[%08x]: %08lx\n",
|
|
|
|
base + LPC54_DMA_CTLSTAT_OFFSET, (unsigned long)regs->ch.ctlstat);
|
|
|
|
dmainfo(" XFERCFG[%08x]: %08lx\n",
|
|
|
|
base + LPC54_DMA_XFERCFG_OFFSET, (unsigned long)regs->ch.xfercfg);
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_DEBUG_DMA */
|
|
|
|
|
|
|
|
#endif /* CONFIG_LPC54_DMA */
|