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/****************************************************************************
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2012-07-06 14:50:43 +00:00
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* arch/arm/src/lpc43xx/lpc43_gpioint.h
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*
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2021-03-24 09:24:48 +01:00
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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2012-07-06 14:50:43 +00:00
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*
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2021-03-24 09:24:48 +01:00
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* http://www.apache.org/licenses/LICENSE-2.0
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2012-07-06 14:50:43 +00:00
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*
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2021-03-24 09:24:48 +01:00
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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2012-07-06 14:50:43 +00:00
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*
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****************************************************************************/
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2012-07-06 14:50:43 +00:00
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/* GPIO pin interrupts
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*
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2021-03-24 09:25:09 +01:00
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* From all available GPIO pins, up to eight pins can be selected in the
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* system control block to serve as external interrupt pins. The external
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* interrupt pins are connected to eight individual interrupts in the NVIC
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* and are created based on rising or falling edges or on the input level
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* on the pin.
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2012-07-06 14:50:43 +00:00
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*
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* GPIO group interrupt
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*
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2021-03-24 09:25:09 +01:00
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* For each port/pin connected to one of the two the GPIO Grouped Interrupt
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* blocks (GROUP0 and GROUP1), the GPIO grouped interrupt registers determine
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* which pins are enabled to generate interrupts and what the active
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* polarities of each of those inputs are. The GPIO grouped interrupt
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* registers also select whether the interrupt output will be level or edge
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* triggered and whether it will be based on the OR or the AND of all of the
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* enabled inputs.
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2012-07-06 14:50:43 +00:00
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*/
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#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_GPIOINT_H
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#define __ARCH_ARM_SRC_LPC43XX_LPC43_GPIOINT_H
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/****************************************************************************
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2012-07-06 14:50:43 +00:00
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* Included Files
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****************************************************************************/
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2012-07-06 14:50:43 +00:00
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#include <nuttx/config.h>
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#include "chip.h"
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2019-05-25 07:22:59 -06:00
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#include "hardware/lpc43_gpio.h"
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2012-07-06 14:50:43 +00:00
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#ifdef CONFIG_LPC43_GPIO_IRQ
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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2012-07-06 14:50:43 +00:00
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/****************************************************************************
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2012-07-06 17:04:08 +00:00
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* Name: lpc43_gpioint_grpinitialize
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2012-07-06 14:50:43 +00:00
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*
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* Description:
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* Initialize the properties of a GPIO group. The properties of the group
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* should be configured before any pins are added to the group by
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* lpc32_gpioint_grpconfig(). As side effects, this call also removes
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* all pins from the group and disables the group interrupt. On return,
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* this is a properly configured, empty GPIO interrupt group.
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure.
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*
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* Assumptions:
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* Interrupts are disabled so that read-modify-write operations are safe.
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*
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****************************************************************************/
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2014-10-21 06:36:27 -06:00
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int lpc43_gpioint_grpinitialize(int group, bool anded, bool level);
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/****************************************************************************
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2012-07-06 17:04:08 +00:00
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* Name: lpc43_gpioint_pinconfig
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*
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* Description:
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* Configure a GPIO pin as an GPIO pin interrupt source (after it has been
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* configured as an input). This function should *not* be called directly
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* from user application code; user code should call this function only
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* indirectly through lpc32_gpio_config().
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure.
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*
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* Assumptions:
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* Interrupts are disabled so that read-modify-write operations are safe.
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*
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****************************************************************************/
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2014-10-21 06:36:27 -06:00
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int lpc43_gpioint_pinconfig(uint16_t gpiocfg);
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2012-07-06 17:04:08 +00:00
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/****************************************************************************
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* Name: lpc43_gpioint_grpconfig
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*
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* Description:
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* Configure a GPIO pin as an GPIO group interrupt member (after it has
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* been configured as an input). This function should *not* be called
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* directly from user application code; user code should call this function
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* only indirectly through lpc32_gpio_config().
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure.
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*
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* Assumptions:
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* Interrupts are disabled so that read-modify-write operations are safe.
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2012-07-06 14:50:43 +00:00
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*
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2012-07-06 17:04:08 +00:00
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****************************************************************************/
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2012-07-06 14:50:43 +00:00
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2014-10-21 06:36:27 -06:00
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int lpc43_gpioint_grpconfig(uint16_t gpiocfg);
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2012-07-06 14:50:43 +00:00
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2016-06-04 00:28:53 -03:00
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/****************************************************************************
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* Name: lpc43_gpioint_ack
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*
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* Description:
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* Acknowledge the interrupt for a given pint interrupt number. Call this
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* inside the interrupt handler. For edge sensitive interrupts, the
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* interrupt status is cleared. For level sensitive interrupts, the
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* active-high/-low sensitivity is inverted.
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure.
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*
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****************************************************************************/
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int lpc43_gpioint_ack(uint8_t intnumber);
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2016-06-04 07:52:56 -06:00
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#endif /* CONFIG_LPC43_GPIO_IRQ */
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2012-07-06 14:50:43 +00:00
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#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_GPIOINT_H */
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