2021-03-04 08:02:21 +01:00
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/****************************************************************************
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2012-09-13 20:32:24 +02:00
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* drivers/lcd/s1d15g10.h
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*
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2021-03-04 07:10:42 +01:00
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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2012-09-13 20:32:24 +02:00
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*
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2021-03-04 07:10:42 +01:00
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* http://www.apache.org/licenses/LICENSE-2.0
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2012-09-13 20:32:24 +02:00
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*
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2021-03-04 07:10:42 +01:00
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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2012-09-13 20:32:24 +02:00
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*
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2021-03-04 08:02:21 +01:00
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****************************************************************************/
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2012-09-13 20:32:24 +02:00
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2021-03-04 07:10:42 +01:00
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/* Definitions for the Epson S1D15G0 LCD controller
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*
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* References: S1D15G0D08B000, Seiko Epson Corportation, 2002.
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*/
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2012-09-13 20:32:24 +02:00
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#ifndef __DRIVERS_LCD_S1D15G10_H
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#define __DRIVERS_LCD_S1D15G10_H
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/****************************************************************************
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2012-09-13 20:32:24 +02:00
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* Included Files
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****************************************************************************/
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2012-09-13 20:32:24 +02:00
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2021-03-04 08:02:21 +01:00
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/****************************************************************************
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2012-09-13 20:32:24 +02:00
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* Pre-processor Definitions
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****************************************************************************/
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2012-09-13 20:32:24 +02:00
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/* Epson S1D15G10 Command Set */
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#define S1D15G10_DISON 0xaf /* Display on; Data: none */
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#define S1D15G10_DISOFF 0xae /* Display off; Data: none */
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#define S1D15G10_DISNOR 0xa6 /* Normal display; Data: none */
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#define S1D15G10_DISINV 0xa7 /* Inverse display; Data: none */
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#define S1D15G10_COMSCN 0xbb /* Common scan direction; Data: (1) common scan direction */
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#define S1D15G10_DISCTL 0xca /* Display control; Data: Data: (1) CL div, F1/2 pat, (2) duty, (3) FR inverse (4) dispersion */
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#define S1D15G10_SLPIN 0x95 /* Sleep in; Data: none */
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#define S1D15G10_SLPOUT 0x94 /* Sleep out; Data: none */
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#define S1D15G10_PASET 0x75 /* Page address set; Data: (1) start page, (2) end page */
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#define S1D15G10_CASET 0x15 /* Column address set; Data: (1) start addr, (2) end addr */
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#define S1D15G10_DATCTL 0xbc /* Data scan direction, etc.; Data: (1) inverse, scan dir (2) RGB, (3) gray-scale */
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#define S1D15G10_RGBSET8 0xce /* 256-color position set; Data: (1-8) red tones, (9-16) green tones, (17-20) blue tones */
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#define S1D15G10_RAMWR 0x5c /* Writing to memory; Data: (1) write data */
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#define S1D15G10_RAMRD 0x5d /* Reading from memory; Data: (1) read data */
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#define S1D15G10_PTLIN 0xa8 /* Partial display in; Data: (1) start addr, (2) end addr */
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#define S1D15G10_PTLOUT 0xa9 /* Partial display out; Data: none */
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#define S1D15G10_RMWIN 0xe0 /* Read and modify write; Data: none */
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#define S1D15G10_RMWOUT 0xee /* End; Data: none */
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#define S1D15G10_ASCSET 0xaa /* Area scroll set; Data: (1) top addr, (2) bottom addr, (3) Num blocks, (4) scroll mode */
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#define S1D15G10_SCSTART 0xab /* Scroll start set; Data: (1) start block addr */
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#define S1D15G10_OSCON 0xd1 /* Internal oscillation on; Data: none */
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#define S1D15G10_OSCOFF 0xd2 /* Internal oscillation off; Data: none */
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#define S1D15G10_PWRCTR 0x20 /* Power control; Data: (1) LCD drive power */
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#define S1D15G10_VOLCTR 0x81 /* Electronic volume control; Data: (1) volume value, (2) resistance ratio */
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#define S1D15G10_VOLUP 0xd6 /* Increment electronic control by 1; Data: none */
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#define S1D15G10_VOLDOWN 0xd7 /* Decrement electronic control by 1; Data: none */
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#define S1D15G10_TMPGRD 0x82 /* Temperature gradient set; Data: (1-14) temperature gradient */
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#define S1D15G10_EPCTIN 0xcd /* Control EEPROM; Data: (1) read/write */
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#define S1D15G10_EPCOUT 0xcc /* Cancel EEPROM control; Data: none */
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#define S1D15G10_EPMWR 0xfc /* Write into EEPROM; Data: none */
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#define S1D15G10_EPMRD 0xfd /* Read from EEPROM; Data: none */
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#define S1D15G10_EPSRRD1 0x7c /* Read register 1; Data: none */
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#define S1D15G10_EPSRRD2 0x7d /* Read register 2; Data: none */
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#define S1D15G10_NOP 0x25 /* NOP instruction (0x45?); Data: none */
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#define S1D15G10_STREAD 0x20 /* Status read; Data: none */
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/* Display control (DISCTL) bit definitions */
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#define DISCTL_PERIOD_SHIFT (0) /* P1: Bits 0-1, F1 and F2 drive-pattern switching period */
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#define DISCTL_PERIOD_MASK (3 << DISCTL_PERIOD_SHIFT)
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# define DISCTL_PERIOD_8 (0 << DISCTL_PERIOD_SHIFT)
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# define DISCTL_PERIOD_4 (1 << DISCTL_PERIOD_SHIFT)
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# define DISCTL_PERIOD_16 (2 << DISCTL_PERIOD_SHIFT)
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# define DISCTL_PERIOD_FLD (3 << DISCTL_PERIOD_SHIFT)
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#define DISCTL_CLDIV_SHIFT (2) /* P1: Bits 2-4, Clock divider */
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#define DISCTL_CLDIV_MASK (7 << DISCTL_CLDIV_SHIFT)
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# define DISCTL_CLDIV_2 (0 << DISCTL_CLDIV_SHIFT)
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# define DISCTL_CLDIV_4 (1 << DISCTL_CLDIV_SHIFT)
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# define DISCTL_CLDIV_8 (2 << DISCTL_CLDIV_SHIFT)
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# define DISCTL_CLDIV_NONE (3 << DISCTL_CLDIV_SHIFT)
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/* Power control (PWRCTR) bit definitions */
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#define PWCTR_REFVOLTAGE (1 << 0) /* P1: Bit 0, Turn on reference voltage generation circuit. */
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#define PWCTR_REGULATOR (1 << 1) /* P1: Bit 1, Turn on voltage regulator and circuit voltage follower. */
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#define PWCTR_BOOSTER2 (1 << 2) /* P1: Bit 2, Turn on secondary booster/step-down circuit. */
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#define PWCTR_BOOSTER1 (1 << 3) /* P1: Bit 3, Turn on primary booster circuit. */
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#define PWCTR_EXTR (1 << 4) /* P1: Bit 4, Use external resistance to adjust voltage. */
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/* Data control (DATCTL) bit definitions */
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#define DATCTL_PGADDR_INV (1 << 0) /* P1: Bit 0, Inverse display of the page address. */
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#define DATCTL_COLADDR_REV (1 << 1) /* P1: Bit 1, Reverse turn of column address. */
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#define DATCTL_ADDR_PGDIR (1 << 2) /* P1: Bit 2, Address-scan direction in page (vs column) direction. */
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#define DATCTL_BGR (1 << 0) /* P2: Bit0, RGB->BGR */
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#define DATCTL_8GRAY (1) /* P3: Bits 0-2 = 001, 8 gray-scale */
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#define DATCTL_16GRAY_A (2) /* P3: Bits 0-2 = 010, 16 gray-scale display type A */
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#define DATCTL_16GRAY_B (4) /* P3: Bits 0-2 = 100, 16 gray-scale display type B */
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/* Status register bit definions (after reset or NOP) */
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#define S1D15G10_SR_PARTIAL (1 << 0) /* Bit 0: Partial display */
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#define S1D15G10_SR_NORMAL (1 << 1) /* Bit 1: Normal (vs. inverse) display */
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#define S1D15G10_SR_EEPROM (1 << 2) /* Bit 2: EEPROM access */
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#define S1D15G10_SR_DISPON (1 << 3) /* Bit 3: Display on */
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#define S1D15G10_SR_COLSCAN (1 << 4) /* Bit 4: Column (vs. page) scan direction */
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#define S1D15G10_SR_RMW (1 << 5) /* Bit 5: Read modify write */
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#define S1D15G10_SR_SCROLL (3 << 6) /* Bits 6-7: Area scroll mode */
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/* Status register bit definions (after EPSRRD1) */
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#define S1D15G10_SR_VOLUME 0x3f /* Bits 0-5: Electronic volume control values */
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/* Status register bit definions (after EPSRRD2) */
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#define S1D15G10_SR_RRATIO 0x07 /* Bits 0-2: Built-in resistance ratio */
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2015-10-02 22:17:29 +02:00
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#endif /* __DRIVERS_LCD_S1D15G10_H */
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