2018-12-19 19:36:35 +01:00
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/****************************************************************************
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2019-08-19 17:16:08 +02:00
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* boards/arm/stm32f0l0g0/b-l072z-lrwan1/include/board.h
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2018-12-19 19:36:35 +01:00
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*
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2020-10-10 14:44:33 +02:00
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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2018-12-19 19:36:35 +01:00
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*
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2020-10-10 14:44:33 +02:00
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* http://www.apache.org/licenses/LICENSE-2.0
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2018-12-19 19:36:35 +01:00
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*
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2020-10-10 14:44:33 +02:00
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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2018-12-19 19:36:35 +01:00
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*
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****************************************************************************/
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2019-08-19 17:16:08 +02:00
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#ifndef __BOARDS_ARM_STM32F0L0G0_B_L072Z_LRWAN1_INCLUDE_BOARD_H
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#define __BOARDS_ARM_STM32F0L0G0_B_L072Z_LRWAN1_INCLUDE_BOARD_H
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2018-12-19 19:36:35 +01:00
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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# include <stdbool.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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2019-02-16 21:53:16 +01:00
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/* HSI - Internal 16 MHz RC Oscillator
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2018-12-19 19:36:35 +01:00
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* LSI - 32 KHz RC
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2019-02-16 21:53:16 +01:00
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* HSE - 8 MHz from MCO output of ST-LINK (default OFF on board)
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2018-12-19 19:36:35 +01:00
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* LSE - 32.768 kHz
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*/
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#define STM32_BOARD_XTAL 8000000ul
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2019-02-16 21:53:16 +01:00
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#define STM32_HSI_FREQUENCY 16000000ul
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2018-12-19 19:36:35 +01:00
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#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_LSE_FREQUENCY 32768 /* X2 on board */
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2020-10-10 15:43:46 +02:00
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/* PLL source is HSI/1, PLL multipler is 4:
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* PLL frequency is 16MHz (XTAL) x 4 = 64MHz
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*/
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2018-12-19 19:36:35 +01:00
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2019-02-16 21:53:16 +01:00
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#define STM32_CFGR_PLLSRC 0
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2018-12-19 19:36:35 +01:00
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#define STM32_CFGR_PLLXTPRE 0
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2019-02-16 21:53:16 +01:00
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#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx4
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#define STM32_PLL_FREQUENCY (4*STM32_HSI_FREQUENCY)
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2018-12-19 19:36:35 +01:00
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/* Use the PLL and set the SYSCLK source to be the PLL/2 (32MHz) */
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#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL
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#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
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#define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_2
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#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY/2
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/* AHB clock (HCLK) is SYSCLK (32MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY
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/* APB2 clock (PCLK2) is HCLK (32MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
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#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
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#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY)
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/* APB1 clock (PCLK1) is HCLK/2 (16MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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2019-05-17 20:46:30 +02:00
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/* 48MHz clock configuration */
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2019-05-27 16:16:24 +02:00
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#if defined(CONFIG_STM32F0L0G0_USB) || defined(CONFIG_STM32F0L0G0_RNG)
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2019-05-17 20:46:30 +02:00
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# define STM32_USE_CLK48 1
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# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48
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# define STM32_HSI48_SYNCSRC SYNCSRC_NONE
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#endif
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2018-12-19 19:36:35 +01:00
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/* TODO: timers */
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/* LED definitions **********************************************************/
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2019-08-19 17:16:08 +02:00
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2018-12-19 19:36:35 +01:00
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/* The Nucleo LO73RZ board has three LEDs. Two of these are controlled by
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* logic on the board and are not available for software control:
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*
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* LD1 COM: LD1 default status is red. LD1 turns to green to indicate that
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* communications are in progress between the PC and the
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* ST-LINK/V2-1.
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* LD3 PWR: red LED indicates that the board is powered.
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*
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* And one can be controlled by software:
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*
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* User LD2: green LED is a user LED connected to the I/O PA5 of the
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* STM32LO73RZ.
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*
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* If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in
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* any way. The following definition is used to access the LED.
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_LED1 0 /* User LD2 */
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#define BOARD_NLEDS 1
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/* LED bits for use with board_userled_all() */
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#define BOARD_LED1_BIT (1 << BOARD_LED1)
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/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board
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* the Nucleo LO73RZ. The following definitions describe how NuttX controls
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* the LED:
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*
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* SYMBOL Meaning LED1 state
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* ------------------ ----------------------- ----------
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* LED_STARTED NuttX has been started OFF
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* LED_HEAPALLOCATE Heap has been allocated OFF
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* LED_IRQSENABLED Interrupts enabled OFF
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* LED_STACKCREATED Idle stack created ON
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* LED_INIRQ In an interrupt No change
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* LED_SIGNAL In a signal handler No change
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* LED_ASSERTION An assertion failed No change
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* LED_PANIC The system has crashed Blinking
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* LED_IDLE STM32 is is sleep mode Not used
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*/
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#define LED_STARTED 0
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#define LED_HEAPALLOCATE 0
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#define LED_IRQSENABLED 0
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#define LED_STACKCREATED 1
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#define LED_INIRQ 2
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#define LED_SIGNAL 2
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#define LED_ASSERTION 2
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#define LED_PANIC 1
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/* Button definitions *******************************************************/
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2019-08-19 17:16:08 +02:00
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2018-12-19 19:36:35 +01:00
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/* The Nucleo LO73RZ supports two buttons; only one button is controllable
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* by software:
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*
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2019-01-09 21:38:00 +01:00
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* B1 USER: user button connected to the I/O PB2/PA0 of the STM32LO73RZ.
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2018-12-19 19:36:35 +01:00
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* B2 RESET: push button connected to NRST is used to RESET the
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* STM32LO73RZ.
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*/
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#define BUTTON_USER 0
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#define NUM_BUTTONS 1
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#define BUTTON_USER_BIT (1 << BUTTON_USER)
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/* Alternate function pin selections ****************************************/
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2019-01-09 21:38:00 +01:00
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/* CMWX1ZZABZ-091 module pinout and internal connections
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*
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* STM32L072CZ | Function
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* ------------+-----------
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* PC0 | SX1276_CE (NRESET)
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* PA7 | SX1276_MOSI
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* PA6 | SX1276_MISO
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* PB3 | SX1276_SCK
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* PA15 | SX1276_NSS
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2019-01-20 14:03:11 +01:00
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* PB4 | SX1276_DIO0
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* PB1 | SX1276_DIO1
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* PB0 | SX1276_DIO2
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* PC13 | SX1276_DIO3
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* PA5 | SX1276_DIO4 optional / LED5
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2019-01-09 21:38:00 +01:00
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* PA4 | SX1276_DIO5 optional
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2019-01-20 14:03:11 +01:00
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* PA1 | CRF1
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* PC1 | CRF2
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* PC2 | CRF3
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2019-01-09 21:38:00 +01:00
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* PA3 | STLINK Virtual COM RX
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* PA2 | STLINK Virtual COM TX
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* PA10 | USART1_RX
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* PA9 | USART1_TX
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* PB15 | SPI2_MOSI
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* PB14 | SPI2_MISO
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* PB13 | SPI2_SCK
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* PB12 | SPI2_NSS
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2019-01-20 14:03:11 +01:00
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* PB5 | LPTIM1_INI / LED2
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* PB6 | LPTIM1_ETR / LED3
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* PB7 | LPTIM1_IN2 / LED4
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2019-01-09 21:38:00 +01:00
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* PB2 | LPTIM1_OUT / BUTTON
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* PA0 | BUTTON (optional)
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* PB9 | I2C1_SDA
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* PB8 | I2C1_SCL
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* PA12 | USB_DP optional / TCXO_VCC
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* PA11 | USB_DM optional
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*
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*/
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2018-12-19 19:36:35 +01:00
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2019-01-09 21:38:00 +01:00
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/* USART */
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2018-12-19 19:36:35 +01:00
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2019-01-09 21:38:00 +01:00
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/* USART1 */
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2018-12-19 19:36:35 +01:00
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2019-01-09 21:38:00 +01:00
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#define GPIO_USART1_RX GPIO_USART1_RX_1 /* PA10 */
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#define GPIO_USART1_TX GPIO_USART1_TX_1 /* PA9 */
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2018-12-19 19:36:35 +01:00
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/* By default the USART2 is connected to STLINK Virtual COM Port:
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* USART2_RX - PA3
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* USART2_TX - PA2
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*/
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#define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */
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#define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA2 */
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2019-01-09 21:38:00 +01:00
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/* SPI */
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/* SPI1 is connected to SX1276 radio */
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#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_2 /* PA7 */
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2019-02-16 21:53:16 +01:00
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#define GPIO_SPI1_MISO GPIO_SPI1_MISO_2 /* PA6 */
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2019-01-09 21:38:00 +01:00
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#define GPIO_SPI1_SCK GPIO_SPI1_SCK_2 /* PB3 */
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#define GPIO_SPI1_NSS GPIO_SPI1_NSS_1 /* PA15 */
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/* SPI2 */
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#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1 /* PB15 */
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#define GPIO_SPI2_MISO GPIO_SPI2_MISO_1 /* PB14 */
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#define GPIO_SPI2_SCK GPIO_SPI2_SCK_3 /* PB13 */
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#define GPIO_SPI2_NSS GPIO_SPI2_NSS_1 /* PB12 */
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/* I2C */
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/* I2C1 */
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#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2 /* PB9 */
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2019-05-15 10:20:28 +02:00
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#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2 /* PB8 */
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2018-12-19 19:36:35 +01:00
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/* DMA channels *************************************************************/
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2019-08-19 17:16:08 +02:00
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2018-12-19 19:36:35 +01:00
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/* ADC */
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2019-05-09 15:02:53 +02:00
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#define ADC1_DMA_CHAN DMACHAN_ADC1_1 /* DMA1_CH1 */
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2018-12-19 19:36:35 +01:00
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2019-08-19 17:16:08 +02:00
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#endif /* __BOARDS_ARM_STM32F0L0G0_B_L072Z_LRWAN1_INCLUDE_BOARD_H */
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