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nuttx/boards/arm64/qemu/qemu-armv8a/configs/nsh/defconfig

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arch: arm64: ARMv8-A support for NuttX N/A Summary: Arm64 support for NuttX, Features supported: 1. Cortex-a53 single core and SMP support: it's can run into nsh shell at qemu virt machine. 2. qemu-a53 board configuration support: it's only for evaluate propose 3. FPU support for armv8-a: FPU context switching at NEON/floating-point TRAP is supported. 4. psci interface, armv8 cache operation(data cache) and smccc support. 5. fix mass code style issue, thank for @xiaoxiang781216, @hartmannathan @pkarashchenko Please refer to boards/arm64/qemu/qemu-a53/README.txt for detail Note: 1. GCC MACOS issue The GCC 11.2 toolchain for MACOS may get crash while compiling float operation function, the following link describe the issue and give analyse at the issue: https://bugs.linaro.org/show_bug.cgi?id=5825 it's seem GCC give a wrong instruction at certain machine which without architecture features the new toolchain is not available still, so just disable the MACOS cibuild check at present Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2022-06-18 13:26:10 +02:00
#
# This file is autogenerated: PLEASE DO NOT EDIT IT.
#
# You can use "make menuconfig" to make any modifications to the installed .config file.
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
# modifications.
#
CONFIG_ARCH="arm64"
CONFIG_ARCH_ARM64=y
arm64: add Cortex-A57 and Cortex-A72 configurations This change adds the following: - Rename the board configuration name from qemu-a53 to qemu-v8a. - Add the configurations for Cortex-A57 and Cortex-A72. Signed-off-by: Hidenori Matsubayashi <hidenori.matsubayashi@gmail.com>
2022-10-13 15:32:59 +02:00
CONFIG_ARCH_BOARD="qemu-armv8a"
CONFIG_ARCH_BOARD_QEMU_ARMV8A=y
arch: arm64: ARMv8-A support for NuttX N/A Summary: Arm64 support for NuttX, Features supported: 1. Cortex-a53 single core and SMP support: it's can run into nsh shell at qemu virt machine. 2. qemu-a53 board configuration support: it's only for evaluate propose 3. FPU support for armv8-a: FPU context switching at NEON/floating-point TRAP is supported. 4. psci interface, armv8 cache operation(data cache) and smccc support. 5. fix mass code style issue, thank for @xiaoxiang781216, @hartmannathan @pkarashchenko Please refer to boards/arm64/qemu/qemu-a53/README.txt for detail Note: 1. GCC MACOS issue The GCC 11.2 toolchain for MACOS may get crash while compiling float operation function, the following link describe the issue and give analyse at the issue: https://bugs.linaro.org/show_bug.cgi?id=5825 it's seem GCC give a wrong instruction at certain machine which without architecture features the new toolchain is not available still, so just disable the MACOS cibuild check at present Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2022-06-18 13:26:10 +02:00
CONFIG_ARCH_CHIP="qemu"
CONFIG_ARCH_CHIP_QEMU=y
arm64/qemu/qemu-a53: Ensure the purity of the defconfig Configuring... Building NuttX... Normalize qemu-a53/nsh 13a14 > CONFIG_ARCH_CHIP_QEMU_A53=y Saving the new configuration file On branch master Your branch is up to date with 'origin/master'. Changes not staged for commit: (use "git add <file>..." to update what will be committed) (use "git restore <file>..." to discard changes in working directory) modified: boards/arm64/qemu/qemu-a53/configs/nsh/defconfig modified: boards/arm64/qemu/qemu-a53/configs/nsh_smp/defconfig retrigger ci build.
2022-10-13 15:48:07 +02:00
CONFIG_ARCH_CHIP_QEMU_A53=y
arm64: add ARCH_EARLY_PRINT support Summary: The aarch64 have EL0~El3 execute level and NS/S (security state), the NuttX should be execute at EL1 in NS(ARmv8-A) or S(ARmv8-R) state. but booting NuttX have different ELs and state while with different platform, if NuttX runing at wrong ELs or state it will be not normal anymore. So we need to print something in arm64_head.S to debug this situation. Enabling this option will need to implement up_earlyserialinit and up_lowputc functions just you see in qemu, if you not sure, keeping the option disable. Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-02-28 08:07:42 +01:00
CONFIG_ARCH_EARLY_PRINT=y
arch: arm64: ARMv8-A support for NuttX N/A Summary: Arm64 support for NuttX, Features supported: 1. Cortex-a53 single core and SMP support: it's can run into nsh shell at qemu virt machine. 2. qemu-a53 board configuration support: it's only for evaluate propose 3. FPU support for armv8-a: FPU context switching at NEON/floating-point TRAP is supported. 4. psci interface, armv8 cache operation(data cache) and smccc support. 5. fix mass code style issue, thank for @xiaoxiang781216, @hartmannathan @pkarashchenko Please refer to boards/arm64/qemu/qemu-a53/README.txt for detail Note: 1. GCC MACOS issue The GCC 11.2 toolchain for MACOS may get crash while compiling float operation function, the following link describe the issue and give analyse at the issue: https://bugs.linaro.org/show_bug.cgi?id=5825 it's seem GCC give a wrong instruction at certain machine which without architecture features the new toolchain is not available still, so just disable the MACOS cibuild check at present Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2022-06-18 13:26:10 +02:00
CONFIG_ARCH_INTERRUPTSTACK=4096
arm64: add hostfs support Sumary add hostfs support for arm64, it's a copy from arm32. Note: it's not support for opendir and readdir, command like ls will not work. Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-04-12 11:56:45 +02:00
CONFIG_ARM64_SEMIHOSTING_HOSTFS=y
CONFIG_ARM64_SEMIHOSTING_HOSTFS_CACHE_COHERENCE=y
arch: arm64: ARMv8-A support for NuttX N/A Summary: Arm64 support for NuttX, Features supported: 1. Cortex-a53 single core and SMP support: it's can run into nsh shell at qemu virt machine. 2. qemu-a53 board configuration support: it's only for evaluate propose 3. FPU support for armv8-a: FPU context switching at NEON/floating-point TRAP is supported. 4. psci interface, armv8 cache operation(data cache) and smccc support. 5. fix mass code style issue, thank for @xiaoxiang781216, @hartmannathan @pkarashchenko Please refer to boards/arm64/qemu/qemu-a53/README.txt for detail Note: 1. GCC MACOS issue The GCC 11.2 toolchain for MACOS may get crash while compiling float operation function, the following link describe the issue and give analyse at the issue: https://bugs.linaro.org/show_bug.cgi?id=5825 it's seem GCC give a wrong instruction at certain machine which without architecture features the new toolchain is not available still, so just disable the MACOS cibuild check at present Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2022-06-18 13:26:10 +02:00
CONFIG_BUILTIN=y
CONFIG_DEBUG_ASSERTIONS=y
CONFIG_DEBUG_ERROR=y
CONFIG_DEBUG_FEATURES=y
CONFIG_DEBUG_FULLOPT=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_SCHED=y
CONFIG_DEBUG_SCHED_ERROR=y
CONFIG_DEBUG_SCHED_INFO=y
CONFIG_DEBUG_SCHED_WARN=y
CONFIG_DEBUG_SYMBOLS=y
CONFIG_DEBUG_WARN=y
CONFIG_DEFAULT_TASK_STACKSIZE=8192
CONFIG_DEV_ZERO=y
CONFIG_EXAMPLES_HELLO=y
CONFIG_EXPERIMENTAL=y
arm64: add hostfs support Sumary add hostfs support for arm64, it's a copy from arm32. Note: it's not support for opendir and readdir, command like ls will not work. Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-04-12 11:56:45 +02:00
CONFIG_FS_HOSTFS=y
arch: arm64: ARMv8-A support for NuttX N/A Summary: Arm64 support for NuttX, Features supported: 1. Cortex-a53 single core and SMP support: it's can run into nsh shell at qemu virt machine. 2. qemu-a53 board configuration support: it's only for evaluate propose 3. FPU support for armv8-a: FPU context switching at NEON/floating-point TRAP is supported. 4. psci interface, armv8 cache operation(data cache) and smccc support. 5. fix mass code style issue, thank for @xiaoxiang781216, @hartmannathan @pkarashchenko Please refer to boards/arm64/qemu/qemu-a53/README.txt for detail Note: 1. GCC MACOS issue The GCC 11.2 toolchain for MACOS may get crash while compiling float operation function, the following link describe the issue and give analyse at the issue: https://bugs.linaro.org/show_bug.cgi?id=5825 it's seem GCC give a wrong instruction at certain machine which without architecture features the new toolchain is not available still, so just disable the MACOS cibuild check at present Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2022-06-18 13:26:10 +02:00
CONFIG_FS_PROCFS=y
arm64: Support for FPU profiling with procfs Summary: To reduce the count of FPU context switching will result at a performance improve with system. it need to balance between the using of FPU and counts of FPU trap the PR submit a base method to see performance counts for the FPU with NuttX procfs Please read README.txt at chapter of FPU Support and Performance for more information Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-03-13 04:10:40 +01:00
CONFIG_FS_PROCFS_REGISTER=y
arch: arm64: ARMv8-A support for NuttX N/A Summary: Arm64 support for NuttX, Features supported: 1. Cortex-a53 single core and SMP support: it's can run into nsh shell at qemu virt machine. 2. qemu-a53 board configuration support: it's only for evaluate propose 3. FPU support for armv8-a: FPU context switching at NEON/floating-point TRAP is supported. 4. psci interface, armv8 cache operation(data cache) and smccc support. 5. fix mass code style issue, thank for @xiaoxiang781216, @hartmannathan @pkarashchenko Please refer to boards/arm64/qemu/qemu-a53/README.txt for detail Note: 1. GCC MACOS issue The GCC 11.2 toolchain for MACOS may get crash while compiling float operation function, the following link describe the issue and give analyse at the issue: https://bugs.linaro.org/show_bug.cgi?id=5825 it's seem GCC give a wrong instruction at certain machine which without architecture features the new toolchain is not available still, so just disable the MACOS cibuild check at present Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2022-06-18 13:26:10 +02:00
CONFIG_FS_ROMFS=y
CONFIG_HAVE_CXX=y
CONFIG_HAVE_CXXINITIALIZE=y
CONFIG_IDLETHREAD_STACKSIZE=8192
CONFIG_INIT_ENTRYPOINT="nsh_main"
CONFIG_INTELHEX_BINARY=y
CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_READLINE=y
CONFIG_NSH_ROMFSETC=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PTHREAD_STACK_MIN=8192
CONFIG_RAMLOG=y
CONFIG_RAM_SIZE=134217728
CONFIG_RAM_START=0x40000000
CONFIG_RAW_BINARY=y
CONFIG_READLINE_CMD_HISTORY=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_HPWORK=y
CONFIG_SCHED_HPWORKPRIORITY=192
CONFIG_SPINLOCK=y
CONFIG_STACK_COLORATION=y
CONFIG_START_MONTH=3
CONFIG_START_YEAR=2022
CONFIG_SYMTAB_ORDEREDBYNAME=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_SYSTEM=y
arm64: add 64-bit time for all arm64 platform Summary For ARM64 architecture, the arch timer is 64-bit, the CONFIG_SYSTEM_TIME64 need to be enabled just like x86_64 and risc-v 64 Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-02-28 10:30:13 +01:00
CONFIG_SYSTEM_TIME64=y
arch: arm64: ARMv8-A support for NuttX N/A Summary: Arm64 support for NuttX, Features supported: 1. Cortex-a53 single core and SMP support: it's can run into nsh shell at qemu virt machine. 2. qemu-a53 board configuration support: it's only for evaluate propose 3. FPU support for armv8-a: FPU context switching at NEON/floating-point TRAP is supported. 4. psci interface, armv8 cache operation(data cache) and smccc support. 5. fix mass code style issue, thank for @xiaoxiang781216, @hartmannathan @pkarashchenko Please refer to boards/arm64/qemu/qemu-a53/README.txt for detail Note: 1. GCC MACOS issue The GCC 11.2 toolchain for MACOS may get crash while compiling float operation function, the following link describe the issue and give analyse at the issue: https://bugs.linaro.org/show_bug.cgi?id=5825 it's seem GCC give a wrong instruction at certain machine which without architecture features the new toolchain is not available still, so just disable the MACOS cibuild check at present Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2022-06-18 13:26:10 +02:00
CONFIG_TESTING_GETPRIME=y
CONFIG_TESTING_OSTEST=y
arch/arm64: change config order Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-05-10 02:47:05 +02:00
CONFIG_UART1_BASE=0x9000000
CONFIG_UART1_IRQ=33
CONFIG_UART1_PL011=y
arch: arm64: ARMv8-A support for NuttX N/A Summary: Arm64 support for NuttX, Features supported: 1. Cortex-a53 single core and SMP support: it's can run into nsh shell at qemu virt machine. 2. qemu-a53 board configuration support: it's only for evaluate propose 3. FPU support for armv8-a: FPU context switching at NEON/floating-point TRAP is supported. 4. psci interface, armv8 cache operation(data cache) and smccc support. 5. fix mass code style issue, thank for @xiaoxiang781216, @hartmannathan @pkarashchenko Please refer to boards/arm64/qemu/qemu-a53/README.txt for detail Note: 1. GCC MACOS issue The GCC 11.2 toolchain for MACOS may get crash while compiling float operation function, the following link describe the issue and give analyse at the issue: https://bugs.linaro.org/show_bug.cgi?id=5825 it's seem GCC give a wrong instruction at certain machine which without architecture features the new toolchain is not available still, so just disable the MACOS cibuild check at present Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2022-06-18 13:26:10 +02:00
CONFIG_UART1_SERIAL_CONSOLE=y
arch/arm64: change config order Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-05-10 02:47:05 +02:00
CONFIG_UART_PL011=y
arch: arm64: ARMv8-A support for NuttX N/A Summary: Arm64 support for NuttX, Features supported: 1. Cortex-a53 single core and SMP support: it's can run into nsh shell at qemu virt machine. 2. qemu-a53 board configuration support: it's only for evaluate propose 3. FPU support for armv8-a: FPU context switching at NEON/floating-point TRAP is supported. 4. psci interface, armv8 cache operation(data cache) and smccc support. 5. fix mass code style issue, thank for @xiaoxiang781216, @hartmannathan @pkarashchenko Please refer to boards/arm64/qemu/qemu-a53/README.txt for detail Note: 1. GCC MACOS issue The GCC 11.2 toolchain for MACOS may get crash while compiling float operation function, the following link describe the issue and give analyse at the issue: https://bugs.linaro.org/show_bug.cgi?id=5825 it's seem GCC give a wrong instruction at certain machine which without architecture features the new toolchain is not available still, so just disable the MACOS cibuild check at present Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2022-06-18 13:26:10 +02:00
CONFIG_USEC_PER_TICK=1000
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