97 lines
4.8 KiB
C
97 lines
4.8 KiB
C
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/****************************************************************************
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* arch/x86_64/include/hpet.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_X86_64_INCLUDE_HPET_H
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#define __ARCH_X86_64_INCLUDE_HPET_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register definitions */
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#define HPET_GCAPID_OFFSET (0x00)
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#define HPET_GCONF_OFFSET (0x10)
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#define HPET_GISR_OFFSET (0x20)
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#define HPET_MCNTR_OFFSET (0xf0)
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#define HPET_TCONF_OFFSET(n) (0x100 + (0x20 * (n)))
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#define HPET_TCOMP_OFFSET(n) (0x108 + (0x20 * (n)))
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#define HPET_TFSB_OFFSET(n) (0x110 + (0x20 * (n)))
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/* General Capabilities and ID Register */
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#define HPET_GCAPID_REVID_SHIFT (0ul) /* Bits 0-7: Revistion */
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# define HPET_GCAPID_REVID_MASK (0xfful << HPET_GCAPID_REVID_SHIFT)
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#define HPET_GCAPID_NUMTIM_SHIFT (8ul) /* Bits 8-12: Number of Timers */
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#define HPET_GCAPID_NUMTIM_MASK (0x1ful << HPET_GCAPID_NUMTIM_SHIFT)
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#define HPET_GCAPID_COUNTSIZE (1 << 13) /* Bit 13: Counter size, 0: 32 bit, 1: 64 bit */
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/* Bit 14: Reserved */
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#define HPET_GCAPID_LEGROUTE (1 << 15) /* Bit 15: LegacyReplacement Route Capable */
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#define HPET_GCAPID_VENDORID_SHIFT (16ul) /* Bits 16-31: Vendor ID */
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# define HPET_GCAPID_VENDORID_MASK (0x7ffful << HPET_GCAPID_VENDORID_SHIFT)
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#define HPET_GCAPID_CLKPER_SHIFT (32ul) /* Bits 32-63: Main Counter Tick Period in ps */
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# define HPET_GCAPID_CLKPER_MASK (0x7ffffffful << HPET_GCAPID_CLKPER_SHIFT)
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/* General Configuration Register */
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#define HPET_GCONF_LEGERT (1 << 0) /* Bit 0: LegacyReplacement Route */
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#define HPET_GCONF_ENABLE (1 << 1) /* Bit 1: Overall Enable */
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/* General Interrupt Status Register */
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#define HPET_GISR_TINT(n) (1 << (n)) /* Timer n Interrupt Active */
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/* Timer N Configuration and Capabilities Register */
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/* Bit 0: Reserved */
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#define HPET_TCONF_INTTYPE (1 << 1) /* Bit 1: Timer n Interrupt Type (0: edge, 1: level) */
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#define HPET_TCONF_INTEN (1 << 2) /* Bit 2: Timer n Interrupt Enable */
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#define HPET_TCONF_TYPE (1 << 3) /* Bit 3: Timer n Type (0: non-periodic, 1: periodic) */
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#define HPET_TCONF_PERCAP (1 << 4) /* Bit 4: Timer n Periodic Interrupt Capable */
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#define HPET_TCONF_SIZECAP (1 << 5) /* Bit 5: Timer n Size */
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#define HPET_TCONF_VALSET (1 << 6) /* Bit 6: Timer n Value Set */
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/* Bit 7: Reserved */
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#define HPET_TCONF_32MODE (1 << 8) /* Bit 8: Timer n 32-bit mode */
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#define HPET_TCONF_INTROUTE_SHIFT (9) /* Bits 9-13: Timer n Interrupt Route */
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# define HPET_TCONF_INTROUTE_MASK (0x7f << HPET_TCONF_INTROUTE_SHIFT)
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# define HPET_TCONF_INTROUTE(n) (((n) << HPET_TCONF_INTROUTE_SHIFT) & HPET_TCONF_INTROUTE_MASK)
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#define HPET_TCONF_FSBEN (1 << 14) /* Bit 14: Timer n FSB Interrupt Enable */
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#define HPET_TCONF_FSBCAP (1 << 15) /* Bit 15: Timer n FSB Interrupt Delivery */
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/* Bits 16-31: Reserved */
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#define HPET_TCONF_ROUTECAP_SHIFT (32) /* Bits 32-63: Timer n Interrupt Routing Capability */
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# define HPET_TCONF_ROUTECAP_MASK (0x7ffffffful << HPET_TCONF_ROUTECAP_SHIFT)
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/* Timer N FSB Interrupt Route Register */
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#define HPET_TFSB_INT_VAL_SHIFT (0)
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#define HPET_TFSB_INT_VAL_MASK (0x00000000ffffffff)
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#define HPET_TFSB_INT_ADDR_SHIFT (31)
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#define HPET_TFSB_INT_ADDR_MASK (0xffffffff00000000)
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/* HPET register space */
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#define HPET_REGION_SIZE (1024)
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#endif /* __ARCH_X86_64_INCLUDE_HPET_H */
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