The ESP32-C3 is an ultra-low-power and highly integrated SoC with a RISC-V
core and supports 2.4 GHz Wi-Fi and Bluetooth Low Energy.
* Address Space
- 800 KB of internal memory address space accessed from the instruction bus
- 560 KB of internal memory address space accessed from the data bus
- 1016 KB of peripheral address space
- 8 MB of external memory virtual address space accessed from the instruction bus
- 8 MB of external memory virtual address space accessed from the data bus
- 480 KB of internal DMA address space
* Internal Memory
- 384 KB ROM
- 400 KB SRAM (16 KB can be configured as Cache)
- 8 KB of SRAM in RTC
* External Memory
- Up to 16 MB of external flash
* Peripherals
- 35 peripherals
* GDMA
- 7 modules are capable of DMA operations.
ESP32-C3 Toolchain
==================
A generic RISC-V toolchain can be used to build ESP32-C3 projects.
SiFive's toolchain can be downloaded from: https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-ubuntu14.tar.gz
Second stage bootloader and partition table
===========================================
The NuttX port for now relies on IDF's second stage bootloader to carry on some hardware
initializations. The binaries for the bootloader and the partition table can be found in
this repository: https://github.com/espressif/esp-nuttx-bootloader
That repository contains a dummy IDF project that's used to build the bootloader and
partition table, these are then presented as Github assets and can be downloaded