2016-10-16 17:47:07 +02:00
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/****************************************************************************
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2020-12-17 19:56:12 +01:00
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* arch/risc-v/include/csr.h
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2016-10-16 17:47:07 +02:00
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*
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2021-04-10 08:50:57 +02:00
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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2016-10-16 17:47:07 +02:00
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*
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2021-04-10 08:50:57 +02:00
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* http://www.apache.org/licenses/LICENSE-2.0
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2016-10-16 17:47:07 +02:00
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*
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2021-04-10 08:50:57 +02:00
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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2016-10-16 17:47:07 +02:00
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*
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****************************************************************************/
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2020-04-05 23:00:04 +02:00
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/* This file should never be included directly but, rather, only indirectly
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2016-10-16 17:47:07 +02:00
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* through nuttx/irq.h
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*/
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2020-12-17 19:56:12 +01:00
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#ifndef __ARCH_RISCV_INCLUDE_CSR_H
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#define __ARCH_RISCV_INCLUDE_CSR_H
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2016-10-16 17:47:07 +02:00
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/****************************************************************************
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* Included Files
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****************************************************************************/
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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2020-04-09 05:47:26 +02:00
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/* User Trap Registers */
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#define CSR_USTATUS 0x000
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#define CSR_UIE 0x004
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#define CSR_UTVEC 0x005
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/* User Trap Handling Registers */
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#define CSR_USCRATCH 0x040
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#define CSR_UEPC 0x041
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#define CSR_UCAUSE 0x042
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#define CSR_UTVAL 0x043
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#define CSR_UIP 0x044
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/* User Floating-Point Registers */
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#define CSR_FFLAGS 0x001
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#define CSR_FRM 0x002
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#define CSR_FCSR 0x003
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/* User Counter/Times Registers */
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2022-03-12 21:16:38 +01:00
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#define CSR_CYCLE 0xc00
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#define CSR_TIME 0xc01
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#define CSR_INSTRET 0xc02
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#define CSR_HPCOUNTER3 0xc03
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#define CSR_HPCOUNTER4 0xc04
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#define CSR_HPCOUNTER5 0xc05
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#define CSR_HPCOUNTER6 0xc06
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#define CSR_HPCOUNTER7 0xc07
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#define CSR_HPCOUNTER8 0xc08
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#define CSR_HPCOUNTER9 0xc09
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#define CSR_HPCOUNTER10 0xc0a
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#define CSR_HPCOUNTER11 0xc0b
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#define CSR_HPCOUNTER12 0xc0c
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#define CSR_HPCOUNTER13 0xc0d
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#define CSR_HPCOUNTER14 0xc0e
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#define CSR_HPCOUNTER15 0xc0f
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#define CSR_HPCOUNTER16 0xc10
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#define CSR_HPCOUNTER17 0xc11
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#define CSR_HPCOUNTER18 0xc12
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#define CSR_HPCOUNTER19 0xc13
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#define CSR_HPCOUNTER20 0xc14
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#define CSR_HPCOUNTER21 0xc15
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#define CSR_HPCOUNTER22 0xc16
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#define CSR_HPCOUNTER24 0xc17
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#define CSR_HPCOUNTER25 0xc18
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#define CSR_HPCOUNTER26 0xc19
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#define CSR_HPCOUNTER27 0xc1a
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#define CSR_HPCOUNTER28 0xc1b
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#define CSR_HPCOUNTER29 0xc1c
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#define CSR_HPCOUNTER30 0xc1d
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#define CSR_HPCOUNTER31 0xc1f
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#define CSR_CYCLEH 0xc80
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#define CSR_TIMEH 0xc81
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#define CSR_INSTRETH 0xc82
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#define CSR_HPCOUNTER3H 0xc83
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#define CSR_HPCOUNTER4H 0xc84
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#define CSR_HPCOUNTER5H 0xc85
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#define CSR_HPCOUNTER6H 0xc86
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#define CSR_HPCOUNTER7H 0xc87
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#define CSR_HPCOUNTER8H 0xc88
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#define CSR_HPCOUNTER9H 0xc89
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#define CSR_HPCOUNTER10H 0xc8a
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#define CSR_HPCOUNTER11H 0xc8b
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#define CSR_HPCOUNTER12H 0xc8c
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#define CSR_HPCOUNTER13H 0xc8d
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#define CSR_HPCOUNTER14H 0xc8e
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#define CSR_HPCOUNTER15H 0xc8f
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#define CSR_HPCOUNTER16H 0xc90
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#define CSR_HPCOUNTER17H 0xc91
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#define CSR_HPCOUNTER18H 0xc92
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#define CSR_HPCOUNTER19H 0xc93
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#define CSR_HPCOUNTER20H 0xc94
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#define CSR_HPCOUNTER21H 0xc95
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#define CSR_HPCOUNTER22H 0xc96
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#define CSR_HPCOUNTER24H 0xc97
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#define CSR_HPCOUNTER25H 0xc98
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#define CSR_HPCOUNTER26H 0xc99
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#define CSR_HPCOUNTER27H 0xc9a
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#define CSR_HPCOUNTER28H 0xc9b
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#define CSR_HPCOUNTER29H 0xc9c
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#define CSR_HPCOUNTER30H 0xc9d
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#define CSR_HPCOUNTER31H 0xc9f
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2020-04-09 05:47:26 +02:00
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/* Supervisor Trap Setup Registers */
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#define CSR_SSTATUS 0x100
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#define CSR_SEDELEG 0x102
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#define CSR_SIDELEG 0x103
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#define CSR_SIE 0x104
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#define CSR_STVEC 0x105
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#define CSR_SCOUNTEREN 0x106
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/* Supervisor Trap Handling Registers */
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#define CSR_SSCRATCH 0x140
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#define CSR_SEPC 0x141
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#define CSR_SCAUSE 0x142
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#define CSR_STVAL 0x143
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#define CSR_SIP 0x144
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2024-04-15 13:12:20 +02:00
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/* Supervisor Environment Configuration Registers */
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#define CSR_SENVCFG 0x10a
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2020-04-09 05:47:26 +02:00
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/* Supervisor Protection and Translation Registers */
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#define CSR_SATP 0x180
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2024-04-15 13:12:20 +02:00
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/* Supervisor Time Registers */
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#define CSR_STIMECMP 0x14d
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#define CSR_STIMECMPH 0x15d
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2016-10-16 17:47:07 +02:00
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/* Machine Information Registers */
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2022-03-12 21:16:38 +01:00
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#define CSR_MVENDORID 0xf11
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#define CSR_MARCHID 0xf12
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#define CSR_MIMPID 0xf13
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#define CSR_MHARTID 0xf14
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2016-10-16 17:47:07 +02:00
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/* Machine Trap Registers */
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2020-04-09 05:47:26 +02:00
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#define CSR_MSTATUS 0x300
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#define CSR_MISA 0x301
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#define CSR_MEDELEG 0x302
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#define CSR_MIDELEG 0x303
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#define CSR_MIE 0x304
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#define CSR_MTVEC 0x305
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#define CSR_MCOUNTEREN 0x306
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2016-10-16 17:47:07 +02:00
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/* Machine Trap Handling */
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2020-04-09 05:47:26 +02:00
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#define CSR_MSCRATCH 0x340
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#define CSR_MEPC 0x341
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#define CSR_MCAUSE 0x342
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#define CSR_MTVAL 0x343
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#define CSR_MIP 0x344
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2024-04-15 13:12:20 +02:00
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/* Machine Environment Configuration Registers */
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#define CSR_MENVCFG 0x30a
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#define CSR_MENVCFGH 0x31a
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2020-04-09 05:47:26 +02:00
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/* Machine Protection and Translation */
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2022-03-12 21:16:38 +01:00
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#define CSR_PMPCFG0 0x3a0
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#define CSR_PMPCFG1 0x3a1
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#define CSR_PMPCFG2 0x3a2
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#define CSR_PMPCFG3 0x3a3
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#define CSR_PMPADDR0 0x3b0
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#define CSR_PMPADDR1 0x3b1
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#define CSR_PMPADDR2 0x3b2
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#define CSR_PMPADDR3 0x3b3
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#define CSR_PMPADDR4 0x3b4
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#define CSR_PMPADDR5 0x3b5
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#define CSR_PMPADDR6 0x3b6
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#define CSR_PMPADDR7 0x3b7
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#define CSR_PMPADDR8 0x3b8
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#define CSR_PMPADDR9 0x3b9
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#define CSR_PMPADDR10 0x3ba
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#define CSR_PMPADDR11 0x3bb
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#define CSR_PMPADDR12 0x3bc
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#define CSR_PMPADDR13 0x3bd
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#define CSR_PMPADDR14 0x3be
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#define CSR_PMPADDR15 0x3bf
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2016-10-16 17:47:07 +02:00
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/* Machine Timers and Counters */
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2022-03-12 21:16:38 +01:00
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#define CSR_MCYCLE 0xb00
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#define CSR_MINSTRET 0xb02
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#define CSR_MHPMCOUNTER3 0xb03
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#define CSR_MHPMCOUNTER4 0xb04
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#define CSR_MHPMCOUNTER5 0xb05
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#define CSR_MHPMCOUNTER6 0xb06
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#define CSR_MHPMCOUNTER7 0xb07
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#define CSR_MHPMCOUNTER8 0xb08
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#define CSR_MHPMCOUNTER9 0xb09
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#define CSR_MHPMCOUNTER10 0xb0a
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#define CSR_MHPMCOUNTER11 0xb0b
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#define CSR_MHPMCOUNTER12 0xb0c
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#define CSR_MHPMCOUNTER13 0xb0d
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#define CSR_MHPMCOUNTER14 0xb0e
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#define CSR_MHPMCOUNTER15 0xb0f
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#define CSR_MHPMCOUNTER16 0xb10
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#define CSR_MHPMCOUNTER17 0xb11
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#define CSR_MHPMCOUNTER18 0xb12
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#define CSR_MHPMCOUNTER19 0xb13
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#define CSR_MHPMCOUNTER20 0xb14
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#define CSR_MHPMCOUNTER21 0xb15
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#define CSR_MHPMCOUNTER22 0xb16
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#define CSR_MHPMCOUNTER23 0xb17
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#define CSR_MHPMCOUNTER24 0xb18
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#define CSR_MHPMCOUNTER25 0xb19
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#define CSR_MHPMCOUNTER26 0xb1a
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#define CSR_MHPMCOUNTER27 0xb1b
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#define CSR_MHPMCOUNTER28 0xb1c
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#define CSR_MHPMCOUNTER29 0xb1d
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#define CSR_MHPMCOUNTER30 0xb1e
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#define CSR_MHPMCOUNTER31 0xb1f
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#define CSR_MCYCLEH 0xb80
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#define CSR_MINSTRETH 0xb82
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#define CSR_MHPMCOUNTER3H 0xb83
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#define CSR_MHPMCOUNTER4H 0xb84
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#define CSR_MHPMCOUNTER5H 0xb85
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#define CSR_MHPMCOUNTER6H 0xb86
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#define CSR_MHPMCOUNTER7H 0xb87
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#define CSR_MHPMCOUNTER8H 0xb88
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#define CSR_MHPMCOUNTER9H 0xb89
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#define CSR_MHPMCOUNTER10H 0xb8a
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#define CSR_MHPMCOUNTER11H 0xb8b
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#define CSR_MHPMCOUNTER12H 0xb8c
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#define CSR_MHPMCOUNTER13H 0xb8d
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#define CSR_MHPMCOUNTER14H 0xb8e
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#define CSR_MHPMCOUNTER15H 0xb8f
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#define CSR_MHPMCOUNTER16H 0xb90
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#define CSR_MHPMCOUNTER17H 0xb91
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#define CSR_MHPMCOUNTER18H 0xb92
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#define CSR_MHPMCOUNTER19H 0xb93
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#define CSR_MHPMCOUNTER20H 0xb94
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#define CSR_MHPMCOUNTER21H 0xb95
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#define CSR_MHPMCOUNTER22H 0xb96
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#define CSR_MHPMCOUNTER23H 0xb97
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#define CSR_MHPMCOUNTER24H 0xb98
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#define CSR_MHPMCOUNTER25H 0xb99
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#define CSR_MHPMCOUNTER26H 0xb9a
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#define CSR_MHPMCOUNTER27H 0xb9b
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#define CSR_MHPMCOUNTER28H 0xb9c
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#define CSR_MHPMCOUNTER29H 0xb9d
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#define CSR_MHPMCOUNTER30H 0xb9e
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#define CSR_MHPMCOUNTER31H 0xb9f
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2020-04-09 05:47:26 +02:00
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/* Machine Counter Setup */
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#define CSR_MPHEVENT3 0x323
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#define CSR_MPHEVENT4 0x324
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#define CSR_MPHEVENT5 0x325
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#define CSR_MPHEVENT6 0x326
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#define CSR_MPHEVENT7 0x327
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#define CSR_MPHEVENT8 0x328
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#define CSR_MPHEVENT9 0x329
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2022-03-12 21:16:38 +01:00
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#define CSR_MPHEVENT10 0x32a
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#define CSR_MPHEVENT11 0x32b
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#define CSR_MPHEVENT12 0x32c
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#define CSR_MPHEVENT13 0x32d
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#define CSR_MPHEVENT14 0x32e
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#define CSR_MPHEVENT15 0x32f
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2020-04-09 05:47:26 +02:00
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#define CSR_MPHEVENT16 0x330
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#define CSR_MPHEVENT17 0x331
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#define CSR_MPHEVENT18 0x332
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#define CSR_MPHEVENT19 0x333
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#define CSR_MPHEVENT20 0x334
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#define CSR_MPHEVENT21 0x335
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#define CSR_MPHEVENT22 0x336
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#define CSR_MPHEVENT23 0x337
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#define CSR_MPHEVENT24 0x338
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#define CSR_MPHEVENT25 0x339
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2022-03-12 21:16:38 +01:00
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#define CSR_MPHEVENT26 0x33a
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#define CSR_MPHEVENT27 0x33b
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#define CSR_MPHEVENT28 0x33c
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#define CSR_MPHEVENT29 0x33d
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#define CSR_MPHEVENT30 0x33e
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#define CSR_MPHEVENT31 0x33f
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2020-04-09 05:47:26 +02:00
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/* Debug/Trace Registers */
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2024-04-10 09:55:44 +02:00
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#define CSR_TSELECT 0x7a0 /* Trigger Select */
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#define CSR_TDATA1 0x7a1 /* Trigger Data 1 */
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#define CSR_TDATA2 0x7a2 /* Trigger Data 2 */
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#define CSR_TDATA3 0x7a3 /* Trigger Data 3 */
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#define CSR_TINFO 0x7a4 /* Trigger Info */
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#define CSR_TCONTROL 0x7a5 /* Trigger Control */
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#define CSR_MCONTEXT 0x7a8 /* Machine Context */
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#define CSR_MSCONTEXT 0x7aa /* Machine Supervisor Context */
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#define CSR_SCONTEXT 0x5a8 /* Supervisor Context */
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#define CSR_HCONTEXT 0x5aa /* Hypervisor Context */
|
2016-10-16 17:47:07 +02:00
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2024-06-24 11:41:46 +02:00
|
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|
/* In tcontrol register */
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#define CSR_TCONTROL_MTE (0x1 << 3) /* M-mode trigger enable */
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#define CSR_TCONTROL_MPTE (0x1 << 7) /* M-mode previous trigger enable */
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|
2016-10-16 17:47:07 +02:00
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/* Debug interface CSRs */
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|
2024-04-10 09:55:44 +02:00
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#define CSR_DCSR 0x7b0 /* Debug Control and Status */
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#define CSR_DPC 0x7b1 /* Debug PC */
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#define CSR_DSCRATCH0 0x7b2 /* Debug Scratch 0 */
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#define CSR_DSCRATCH1 0x7b3 /* Debug Scratch 1 */
|
2020-04-09 05:47:26 +02:00
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2024-04-18 10:44:57 +02:00
|
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/* Vector CSRs */
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#define CSR_VSTART 0x008 /* Vector Start Position */
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#define CSR_VXSAT 0x009 /* Fixed-Point Saturate Flag */
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#define CSR_VXRM 0x00a /* Fixed-Point Rounding Mode */
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#define CSR_VCSR 0x00f /* Vector Control and Status */
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#define CSR_VL 0xc20 /* Vector Length */
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#define CSR_VTYPE 0xc21 /* Vector Data Type */
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#define CSR_VLENB 0xc22 /* Vector Length in Bytes (VLEN/8) */
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2024-06-14 12:22:30 +02:00
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/* Indirect CSR Access CSRs */
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#define CSR_MISELECT 0x350 /* Machine indirect register select */
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#define CSR_MIREG 0x351 /* Machine indirect register alias */
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#define CSR_MIREG2 0x352 /* Machine indirect register alias 2 */
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#define CSR_MIREG3 0x353 /* Machine indirect register alias 3 */
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#define CSR_MIREG4 0x355 /* Machine indirect register alias 4 */
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#define CSR_MIREG5 0x356 /* Machine indirect register alias 5 */
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#define CSR_MIREG6 0x357 /* Machine indirect register alias 6 */
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#define CSR_SISELECT 0x150 /* Supervisor indirect register select */
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#define CSR_SIREG 0x151 /* Supervisor indirect register alias */
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#define CSR_SIREG2 0x152 /* Supervisor indirect register alias 2 */
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#define CSR_SIREG3 0x153 /* Supervisor indirect register alias 3 */
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#define CSR_SIREG4 0x155 /* Supervisor indirect register alias 4 */
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#define CSR_SIREG5 0x156 /* Supervisor indirect register alias 5 */
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#define CSR_SIREG6 0x157 /* Supervisor indirect register alias 6 */
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#define CSR_VSISELECT 0x250 /* Virtual supervisor indirect register select */
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#define CSR_VSIREG 0x251 /* Virtual supervisor indirect register alias */
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#define CSR_VSIREG2 0x252 /* Virtual supervisor indirect register alias 2 */
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#define CSR_VSIREG3 0x253 /* Virtual supervisor indirect register alias 3 */
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#define CSR_VSIREG4 0x255 /* Virtual supervisor indirect register alias 4 */
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#define CSR_VSIREG5 0x256 /* Virtual supervisor indirect register alias 5 */
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#define CSR_VSIREG6 0x257 /* Virtual supervisor indirect register alias 6 */
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|
2024-06-14 15:46:59 +02:00
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/* CLIC CSRs */
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#define CSR_MTVT 0x307 /* Trap-handler vector table base address */
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#define CSR_MNXTI 0x345 /* Interrupt handler address and enable modifier */
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#define CSR_MINTSTATUS 0xfb1 /* Current interrupt levels */
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#define CSR_MINTTHRESH 0x347 /* Interrupt-level threshold */
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#define CSR_MSCRATCHCSW 0x348 /* Conditional scratch swap on priv mode change */
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#define CSR_MSCRATCHCSWL 0x349 /* Conditional scratch swap on level change */
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#define CSR_STVT 0x107 /* Trap-handler vector table base address */
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#define CSR_SNXTI 0x145 /* Interrupt handler address and enable modifier */
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#define CSR_SINTSTATUS 0xdb1 /* Current interrupt levels */
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#define CSR_SINTTHRESH 0x147 /* Interrupt-level threshold */
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#define CSR_SSCRATCHCSW 0x148 /* Conditional scratch swap on priv mode change */
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#define CSR_SSCRATCHCSWL 0x149 /* Conditional scratch swap on level change */
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#define CSR_UTVT 0x007 /* Trap-handler vector table base address */
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#define CSR_UNXTI 0x045 /* Interrupt handler address and enable modifier */
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#define CSR_UINTSTATUS 0xcb1 /* Current interrupt levels */
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#define CSR_UINTTHRESH 0x047 /* Interrupt-level threshold */
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#define CSR_USCRATCHCSWL 0x049 /* Conditional scratch swap on level change */
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|
2024-06-15 05:06:51 +02:00
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/* CLIC Indirect CSRs */
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|
#define MISELECT_CLICCFG 0x14a0 /* MIREG */
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|
#define MISELECT_CLICINTCTL 0x1000 /* MIREG */
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|
#define MISELECT_CLICINTATTR 0x1000 /* MIREG2 */
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|
#define MISELECT_CLICINTIP 0x1400 /* MIREG */
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|
#define MISELECT_CLICINTIE 0x1400 /* MIREG2 */
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|
#define MISELECT_CLICINTTRIG 0x1480 /* MIREG */
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|
2020-12-19 18:39:14 +01:00
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|
/* In mstatus register */
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|
|
2022-04-01 23:09:23 +02:00
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|
|
#define MSTATUS_UIE (0x1 << 0) /* User Interrupt Enable */
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|
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#define MSTATUS_SIE (0x1 << 1) /* Supervisor Interrupt Enable */
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|
#define MSTATUS_MIE (0x1 << 3) /* Machine Interrupt Enable */
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|
|
#define MSTATUS_SPIE (0x1 << 5) /* Supervisor Previous Interrupt Enable */
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|
#define MSTATUS_MPIE (0x1 << 7) /* Machine Previous Interrupt Enable */
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#define MSTATUS_SPPU (0x0 << 8) /* Supervisor Previous Privilege (u-mode) */
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|
#define MSTATUS_SPPS (0x1 << 8) /* Supervisor Previous Privilege (s-mode) */
|
2024-01-28 13:09:46 +01:00
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|
#define MSTATUS_VS (0x3 << 9) /* Machine Vector-extension Status */
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|
|
#define MSTATUS_VS_INIT (0x1 << 9)
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|
#define MSTATUS_VS_CLEAN (0x2 << 9)
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|
#define MSTATUS_VS_DIRTY (0x3 << 9)
|
2022-04-01 23:09:23 +02:00
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|
#define MSTATUS_MPPU (0x0 << 11) /* Machine Previous Privilege (u-mode) */
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#define MSTATUS_MPPS (0x1 << 11) /* Machine Previous Privilege (s-mode) */
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|
#define MSTATUS_MPPM (0x3 << 11) /* Machine Previous Privilege (m-mode) */
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|
|
#define MSTATUS_MPP_MASK (0x3 << 11)
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|
|
#define MSTATUS_FS (0x3 << 13) /* Machine Floating-point Status */
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|
|
#define MSTATUS_FS_INIT (0x1 << 13)
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|
#define MSTATUS_FS_CLEAN (0x2 << 13)
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|
#define MSTATUS_FS_DIRTY (0x3 << 13)
|
2024-01-28 13:09:46 +01:00
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|
|
#define MSTATUS_XS (0x3 << 15) /* Machine additional-extension Status */
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|
|
#define MSTATUS_XS_INIT (0x1 << 15)
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|
#define MSTATUS_XS_CLEAN (0x2 << 15)
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|
#define MSTATUS_XS_DIRTY (0x3 << 15)
|
2022-04-01 23:09:23 +02:00
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|
|
#define MSTATUS_MPRV (0x1 << 17) /* Modify Privilege */
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|
|
#define MSTATUS_SUM (0x1 << 18) /* S mode access to U mode memory */
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|
|
#define MSTATUS_MXR (0x1 << 19) /* Make executable / readable */
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|
|
#define MSTATUS_TVM (0x1 << 20) /* Trap access to satp from S mode */
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|
|
#define MSTATUS_TW (0x1 << 21) /* Trap WFI instruction from S mode */
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|
|
#define MSTATUS_TSR (0x1 << 22) /* Trap supervisor return (sret) */
|
2020-12-19 18:39:14 +01:00
|
|
|
|
2022-03-18 05:20:15 +01:00
|
|
|
/* Mask of preserved bits for mstatus */
|
|
|
|
|
|
|
|
#ifdef CONFIG_ARCH_RV32
|
2022-04-01 23:09:23 +02:00
|
|
|
#define MSTATUS_WPRI (0xff << 23 | 0x15)
|
2022-03-18 05:20:15 +01:00
|
|
|
#else
|
2022-04-01 23:09:23 +02:00
|
|
|
#define MSTATUS_WPRI (UINT64_C(0x1ffffff) << 38 | UINT64_C(0x1ff) << 23 | 0x15)
|
2022-03-18 05:20:15 +01:00
|
|
|
#endif
|
|
|
|
|
2024-04-15 13:12:20 +02:00
|
|
|
/* In menvcfg register */
|
|
|
|
#define MENVCFG_FIOM (0x1 << 0)
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|
|
|
#define MENVCFG_CBIE (0x3 << 4)
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|
|
#define MENVCFG_CBIE_ILL (0x0 << 4)
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|
|
|
#define MENVCFG_CBIE_FLUSH (0x1 << 4)
|
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|
|
#define MENVCFG_CBIE_INV (0x3 << 4)
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|
|
|
#define MENVCFG_CBCFE (0x1 << 6)
|
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|
|
#define MENVCFG_CBZE (0x1 << 7)
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|
|
|
|
|
|
|
#ifdef CONFIG_ARCH_RV32
|
|
|
|
#define MENVCFG_PBMTE (0x1 << 30)
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|
|
|
#define MENVCFG_STCE (0x1 << 31)
|
|
|
|
#else
|
|
|
|
#define MENVCFG_PBMTE (UINT64_C(0x1) << 62)
|
|
|
|
#define MENVCFG_STCE (UINT64_C(0x1) << 63)
|
|
|
|
#endif
|
|
|
|
|
2020-12-19 18:39:14 +01:00
|
|
|
/* In mie (machine interrupt enable) register */
|
|
|
|
|
2022-04-01 23:09:23 +02:00
|
|
|
#define MIE_SSIE (0x1 << 1) /* Supervisor Software Interrupt Enable */
|
|
|
|
#define MIE_MSIE (0x1 << 3) /* Machine Software Interrupt Enable */
|
|
|
|
#define MIE_STIE (0x1 << 5) /* Supervisor Timer Interrupt Enable */
|
|
|
|
#define MIE_MTIE (0x1 << 7) /* Machine Timer Interrupt Enable */
|
|
|
|
#define MIE_SEIE (0x1 << 9) /* Supervisor External Interrupt Enable */
|
|
|
|
#define MIE_MEIE (0x1 << 11) /* Machine External Interrupt Enable */
|
2020-12-19 18:39:14 +01:00
|
|
|
|
|
|
|
/* In mip (machine interrupt pending) register */
|
|
|
|
|
2022-04-01 23:09:23 +02:00
|
|
|
#define MIP_SSIP (0x1 << 1)
|
2024-04-12 11:27:00 +02:00
|
|
|
#define MIP_MSIP (0x1 << 3)
|
2022-04-01 23:09:23 +02:00
|
|
|
#define MIP_STIP (0x1 << 5)
|
|
|
|
#define MIP_MTIP (0x1 << 7)
|
|
|
|
#define MIP_SEIP (0x1 << 9)
|
2024-04-12 11:27:00 +02:00
|
|
|
#define MIP_MEIP (0x1 << 11)
|
2022-03-17 10:20:42 +01:00
|
|
|
|
|
|
|
/* In sstatus register (which is a view of mstatus) */
|
|
|
|
|
|
|
|
#define SSTATUS_SIE MSTATUS_SIE
|
|
|
|
#define SSTATUS_SPIE MSTATUS_SPIE
|
|
|
|
#define SSTATUS_SPPU MSTATUS_SPPU
|
|
|
|
#define SSTATUS_SPPS MSTATUS_SPPS
|
2024-01-28 13:09:46 +01:00
|
|
|
#define SSTATUS_VS MSTATUS_VS
|
|
|
|
#define SSTATUS_VS_INIT MSTATUS_VS_INIT
|
|
|
|
#define SSTATUS_VS_CLEAN MSTATUS_VS_CLEAN
|
|
|
|
#define SSTATUS_VS_DIRTY MSTATUS_VS_DIRTY
|
2022-03-17 10:20:42 +01:00
|
|
|
#define SSTATUS_FS MSTATUS_FS
|
|
|
|
#define SSTATUS_FS_INIT MSTATUS_FS_INIT
|
|
|
|
#define SSTATUS_FS_CLEAN MSTATUS_FS_CLEAN
|
|
|
|
#define SSTATUS_FS_DIRTY MSTATUS_FS_DIRTY
|
2024-01-28 13:09:46 +01:00
|
|
|
#define SSTATUS_XS MSTATUS_XS
|
|
|
|
#define SSTATUS_XS_INIT MSTATUS_XS_INIT
|
|
|
|
#define SSTATUS_XS_CLEAN MSTATUS_XS_CLEAN
|
|
|
|
#define SSTATUS_XS_DIRTY MSTATUS_XS_DIRTY
|
2022-03-17 10:20:42 +01:00
|
|
|
#define SSTATUS_SUM MSTATUS_SUM
|
|
|
|
#define SSTATUS_MXR MSTATUS_MXR
|
|
|
|
|
|
|
|
/* In sie register (which is a view of mie) */
|
|
|
|
|
|
|
|
#define SIE_SSIE MIE_SSIE
|
|
|
|
#define SIE_STIE MIE_STIE
|
|
|
|
#define SIE_SEIE MIE_SEIE
|
|
|
|
|
|
|
|
/* In sip register (which is a view of mip) */
|
|
|
|
|
|
|
|
#define SIP_SSIP MIP_SSIP
|
|
|
|
#define SIP_STIP MIP_STIP
|
|
|
|
#define SIP_SEIP MIP_SEIP
|
2020-12-19 18:39:14 +01:00
|
|
|
|
2024-04-15 13:12:20 +02:00
|
|
|
/* In senvcfg register */
|
|
|
|
#define SENVCFG_FIOM MENVCFG_FIOM
|
|
|
|
#define SENVCFG_CBIE MENVCFG_CBIE
|
|
|
|
#define SENVCFG_CBIE_ILL MENVCFG_CBIE_ILL
|
|
|
|
#define SENVCFG_CBIE_FLUSH MENVCFG_CBIE_FLUSH
|
|
|
|
#define SENVCFG_CBIE_INV MENVCFG_CBIE_INV
|
|
|
|
#define SENVCFG_CBCFE MENVCFG_CBCFE
|
|
|
|
#define SENVCFG_CBZE MENVCFG_CBZE
|
|
|
|
|
2021-03-27 15:32:10 +01:00
|
|
|
/* In pmpcfg (PMP configuration) register */
|
|
|
|
|
2022-04-01 23:09:23 +02:00
|
|
|
#define PMPCFG_R (1 << 0) /* readable ? */
|
|
|
|
#define PMPCFG_W (1 << 1) /* writable ? */
|
|
|
|
#define PMPCFG_X (1 << 2) /* executable ? */
|
|
|
|
#define PMPCFG_RWX_MASK (7 << 0) /* access rights mask */
|
|
|
|
#define PMPCFG_A_OFF (0 << 3) /* null region (disabled) */
|
|
|
|
#define PMPCFG_A_TOR (1 << 3) /* top of range */
|
|
|
|
#define PMPCFG_A_NA4 (2 << 3) /* naturally aligned four-byte region */
|
|
|
|
#define PMPCFG_A_NAPOT (3 << 3) /* naturally aligned power-of-two region */
|
|
|
|
#define PMPCFG_A_MASK (3 << 3) /* address-matching mode mask */
|
|
|
|
#define PMPCFG_L (1 << 7) /* locked ? */
|
2021-03-27 15:32:10 +01:00
|
|
|
|
2024-04-15 13:12:20 +02:00
|
|
|
/* In mcounteren/scounteren register */
|
|
|
|
#define COUNTEREN_CY (0x1 << 0)
|
|
|
|
#define COUNTEREN_TM (0x1 << 1)
|
|
|
|
#define COUNTEREN_IR (0x1 << 2)
|
|
|
|
#define COUNTEREN_HPM3 (0x1 << 3)
|
|
|
|
#define COUNTEREN_HPM4 (0x1 << 4)
|
|
|
|
#define COUNTEREN_HPM5 (0x1 << 5)
|
|
|
|
#define COUNTEREN_HPM6 (0x1 << 6)
|
|
|
|
#define COUNTEREN_HPM7 (0x1 << 7)
|
|
|
|
#define COUNTEREN_HPM8 (0x1 << 8)
|
|
|
|
#define COUNTEREN_HPM9 (0x1 << 9)
|
|
|
|
#define COUNTEREN_HPM10 (0x1 << 10)
|
|
|
|
#define COUNTEREN_HPM11 (0x1 << 11)
|
|
|
|
#define COUNTEREN_HPM12 (0x1 << 12)
|
|
|
|
#define COUNTEREN_HPM13 (0x1 << 13)
|
|
|
|
#define COUNTEREN_HPM14 (0x1 << 14)
|
|
|
|
#define COUNTEREN_HPM15 (0x1 << 15)
|
|
|
|
#define COUNTEREN_HPM16 (0x1 << 16)
|
|
|
|
#define COUNTEREN_HPM17 (0x1 << 17)
|
|
|
|
#define COUNTEREN_HPM18 (0x1 << 18)
|
|
|
|
#define COUNTEREN_HPM19 (0x1 << 19)
|
|
|
|
#define COUNTEREN_HPM20 (0x1 << 20)
|
|
|
|
#define COUNTEREN_HPM21 (0x1 << 21)
|
|
|
|
#define COUNTEREN_HPM22 (0x1 << 22)
|
|
|
|
#define COUNTEREN_HPM23 (0x1 << 23)
|
|
|
|
#define COUNTEREN_HPM24 (0x1 << 24)
|
|
|
|
#define COUNTEREN_HPM25 (0x1 << 25)
|
|
|
|
#define COUNTEREN_HPM26 (0x1 << 26)
|
|
|
|
#define COUNTEREN_HPM27 (0x1 << 27)
|
|
|
|
#define COUNTEREN_HPM28 (0x1 << 28)
|
|
|
|
#define COUNTEREN_HPM29 (0x1 << 29)
|
|
|
|
#define COUNTEREN_HPM30 (0x1 << 30)
|
|
|
|
#define COUNTEREN_HPM31 (0x1 << 31)
|
|
|
|
|
2016-10-16 17:47:07 +02:00
|
|
|
/****************************************************************************
|
|
|
|
* Public Types
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Public Function Prototypes
|
|
|
|
****************************************************************************/
|
|
|
|
|
2020-12-17 19:56:12 +01:00
|
|
|
#endif /* __ARCH_RISCV_INCLUDE_CSR_H */
|