2019-08-19 17:16:08 +02:00
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/****************************************************************************
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* boards/arm/stm32/olimex-stm32-e407/include/board.h
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2016-06-27 13:41:41 +02:00
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*
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2021-03-31 12:17:21 +02:00
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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2016-06-27 13:41:41 +02:00
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*
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2021-03-31 12:17:21 +02:00
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* http://www.apache.org/licenses/LICENSE-2.0
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2016-06-27 13:41:41 +02:00
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*
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2021-03-31 12:17:21 +02:00
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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2016-06-27 13:41:41 +02:00
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*
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2019-08-19 17:16:08 +02:00
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****************************************************************************/
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2016-06-27 13:41:41 +02:00
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2019-08-19 17:16:08 +02:00
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#ifndef __BOARDS_ARM_STM32_OLIMEX_STM32_E407_INCLUDE_BOARD_H
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2020-01-31 19:07:39 +01:00
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#define __BOARDS_ARM_STM32_OLIMEX_STM32_E407_INCLUDE_BOARD_H
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2016-06-27 13:41:41 +02:00
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2019-08-19 17:16:08 +02:00
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/****************************************************************************
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2016-06-27 13:41:41 +02:00
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* Included Files
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2019-08-19 17:16:08 +02:00
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****************************************************************************/
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2016-06-27 13:41:41 +02:00
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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# include <stdbool.h>
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#endif
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2019-08-19 17:16:08 +02:00
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/****************************************************************************
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2016-06-27 13:41:41 +02:00
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* Pre-processor Definitions
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2019-08-19 17:16:08 +02:00
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****************************************************************************/
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2016-06-27 13:41:41 +02:00
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2021-04-01 08:20:14 +02:00
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/* Clocking *****************************************************************/
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2016-06-27 13:41:41 +02:00
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/* The Olimex-STM32-E407 board features a 12MHz crystal and
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* a 32kHz RTC backup crystal.
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*
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* This is the canonical configuration:
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2021-04-01 08:20:14 +02:00
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* System Clock source : PLL (HSE)
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* SYSCLK(Hz) : 168000000 Determined by PLL configuration
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* HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE)
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* AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE)
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* APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1)
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* APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2)
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* HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL)
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* PLLM : 8 (STM32_PLLCFG_PLLM)
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* PLLN : 336 (STM32_PLLCFG_PLLN)
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* PLLP : 2 (STM32_PLLCFG_PLLP)
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* PLLQ : 7 (STM32_PLLCFG_PLLQ)
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* Main regulator output
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* voltage : Scale1 mode Needed for high speed SYSCLK
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* Flash Latency(WS) : 5
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* Prefetch Buffer : OFF
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* Instruction cache : ON
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* Data cache : ON
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* Require 48MHz for : Enabled
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* USB OTG FS,
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2016-06-27 13:41:41 +02:00
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* SDIO and RNG clock
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*/
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/* HSI - 16 MHz RC factory-trimmed
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* LSI - 32 KHz RC (30-60KHz, uncalibrated)
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* HSE - On-board crystal frequency is 12MHz
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* LSE - 32.768 kHz
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* STM32F407ZGT6 - too 168Mhz
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*/
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#define STM32_BOARD_XTAL 12000000ul
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#define STM32_HSI_FREQUENCY 16000000ul
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#define STM32_LSI_FREQUENCY 32000
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_LSE_FREQUENCY 32768
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/* Main PLL Configuration.
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*
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* PLL source is HSE
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* PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
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* = (25,000,000 / 12) * 360
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* = 240,000,000
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* SYSCLK = PLL_VCO / PLLP
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* = 240,000,000 / 2 = 120,000,000
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* USB OTG FS, SDIO and RNG Clock
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* = PLL_VCO / PLLQ
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* = 240,000,000 / 5 = 48,000,000
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* = 48,000,000
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*
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* Xtal /M *n /P SysClk AHB HCLK APB1 PCLK1
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* 12Mhz HSE /12 336 /2 PLLCLK 168Mhz /1 168 /4 42Mhz
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* 12Mhz HSE /6 168 /2 PLLCLK 168Mhz /1 168 /4 42Mhz
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*/
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(3)
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(84)
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
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#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(5)
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#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7)
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#define STM32_SYSCLK_FREQUENCY 168000000ul
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/* AHB clock (HCLK) is SYSCLK (168MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
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/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
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/* Timers driven from APB1 will be twice PCLK1 */
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
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/* APB2 clock (PCLK2) is HCLK/2 */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* Timers driven from APB2 will be twice PCLK2 */
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#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY)
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2017-02-25 17:04:28 +01:00
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/* Timer Frequencies, if APBx is set to 1, frequency is same as APBx
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2016-06-27 13:41:41 +02:00
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* otherwise frequency is 2xAPBx.
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* Note: TIM1,8 are on APB2, others on APB1
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*/
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2017-02-25 17:04:28 +01:00
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#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
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2016-06-27 13:41:41 +02:00
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2021-04-01 08:20:14 +02:00
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/* LED definitions **********************************************************/
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/* If CONFIG_ARCH_LEDS is not defined, then the user can control the status
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* LED in any way.
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* The following definitions are used to access individual LEDs.
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2016-06-27 13:41:41 +02:00
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_LED_STATUS 0
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#define BOARD_NLEDS 1
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/* LED bits for use with board_userled_all() */
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#define BOARD_LED_STATUS_BIT (1 << BOARD_LED1)
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2021-04-01 08:20:14 +02:00
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/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the status LED of
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* the Olimex STM32-E405.
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* The following definitions describe how NuttX controls the LEDs:
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2016-06-27 13:41:41 +02:00
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*/
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#define LED_STARTED 0 /* LED_STATUS on */
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#define LED_HEAPALLOCATE 1 /* no change */
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#define LED_IRQSENABLED 2 /* no change */
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#define LED_STACKCREATED 3 /* no change */
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#define LED_INIRQ 4 /* no change */
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#define LED_SIGNAL 5 /* no change */
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#define LED_ASSERTION 6 /* LED_STATUS off */
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#define LED_PANIC 7 /* LED_STATUS blinking */
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2021-04-01 08:20:14 +02:00
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/* Button definitions *******************************************************/
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2016-06-27 13:41:41 +02:00
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/* The Olimex STM32-E405 supports one buttons: */
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#define BUTTON_BUT 0
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#define NUM_BUTTONS 1
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#define BUTTON_BUT_BIT (1 << BUTTON_BUT)
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2021-04-01 08:20:14 +02:00
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/* Alternate function pin selections ****************************************/
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2016-06-27 13:41:41 +02:00
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/* USART1 */
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2019-07-10 15:39:35 +02:00
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2016-06-27 13:41:41 +02:00
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#define GPIO_USART1_RX GPIO_USART1_RX_2 /* PB7 */
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#define GPIO_USART1_TX GPIO_USART1_TX_2 /* PB6 */
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/* USART2 */
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2016-06-27 13:41:41 +02:00
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#define GPIO_USART2_RX GPIO_USART2_RX_2 /* PD6 */
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#define GPIO_USART2_TX GPIO_USART2_TX_2 /* PD5 */
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/* USART3 */
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2016-06-27 13:41:41 +02:00
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#define GPIO_USART3_RX GPIO_USART3_RX_1 /* PB11 */
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#define GPIO_USART3_TX GPIO_USART3_TX_1 /* PB10 */
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/* CAN */
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2019-07-10 15:39:35 +02:00
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#define GPIO_CAN1_RX GPIO_CAN1_RX_2 /* PB8 */
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#define GPIO_CAN1_TX GPIO_CAN1_TX_2 /* PB9 */
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/* I2C */
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#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1 /* PB6 */
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#define GPIO_I2C1_SDA GPIO_I2C1_SDA_1 /* PB7 */
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/* SPI1 */
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#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 /* PA5 */
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#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_2 /* PB5 */
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#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 /* PA6 */
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2016-06-27 13:41:41 +02:00
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2021-04-01 08:20:14 +02:00
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/* Ethernet *****************************************************************/
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#if defined(CONFIG_STM32_ETHMAC)
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/* RMII interface to the LAN8710 PHY (works with LAN8720 driver) */
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# ifndef CONFIG_STM32_RMII
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# error CONFIG_STM32_RMII must be defined
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# endif
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/* Clocking is provided by an external 50Mhz XTAL */
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# ifndef CONFIG_STM32_RMII_EXTCLK
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# error CONFIG_STM32_RMII_EXTCLK must be defined
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# endif
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/* Pin disambiguation */
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2021-04-01 08:20:14 +02:00
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# define GPIO_ETH_MII_COL GPIO_ETH_MII_COL_1 /* PA3 */
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# define GPIO_ETH_RMII_TXD0 GPIO_ETH_RMII_TXD0_2 /* PG13 */
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# define GPIO_ETH_RMII_TXD1 GPIO_ETH_RMII_TXD1_2 /* PG14 */
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# define GPIO_ETH_RMII_TX_EN GPIO_ETH_RMII_TX_EN_2 /* PG11 */
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#endif
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2019-08-19 17:16:08 +02:00
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#endif /* __BOARDS_ARM_STM32_OLIMEX_STM32_E407_INCLUDE_BOARD_H */
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