204 lines
7.3 KiB
C
204 lines
7.3 KiB
C
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/****************************************************************************
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* boards/arm/stm32/emw3162/include/board.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_STM32_EMW3162_INCLUDE_BOARD_H
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#define __BOARDS_ARM_STM32_EMW3162_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdbool.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* The EMW3162 board features a single 26MHz crystal.
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*
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* This is the canonical configuration:
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* System Clock source : PLL (HSE)
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* SYSCLK(Hz) : 120000000 Determined by PLL
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* configuration
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* HCLK(Hz) : 120000000 (STM32_RCC_CFGR_HPRE)
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* AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE)
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* APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1)
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* APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2)
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* HSE Frequency(Hz) : 26000000 (STM32_BOARD_XTAL)
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* PLLM : 26 (STM32_PLLCFG_PLLM)
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* PLLN : 240 (STM32_PLLCFG_PLLN)
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* PLLP : 2 (STM32_PLLCFG_PLLP)
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* PLLQ : 5 (STM32_PLLCFG_PLLQ)
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* Main regulator output voltage : Scale1 mode Needed for high speed
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* SYSCLK
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* Flash Latency(WS) : 3
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* Prefetch Buffer : OFF
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* Instruction cache : ON
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* Data cache : ON
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* Require 48MHz for USB OTG HS : Enabled
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* SDIO and RNG clock
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*/
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/* HSI - 16 MHz RC factory-trimmed
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* LSI - 32 KHz RC
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* HSE - On-board crystal frequency is 26MHz
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* LSE - 32.768 kHz
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*/
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#define STM32_BOARD_XTAL 26000000ul
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#define STM32_HSI_FREQUENCY 16000000ul
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#define STM32_LSI_FREQUENCY 32000
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_LSE_FREQUENCY 32768
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/* Main PLL Configuration.
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*
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* PLL source is HSE
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* PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
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* = (26,000,000 / 26) * 240
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* = 240,000,000
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* SYSCLK = PLL_VCO / PLLP
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* = 240,000,000 / 2 = 120,000,000
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* USB OTG FS, SDIO and RNG Clock
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* = PLL_VCO / PLLQ
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* = 48,000,000
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*/
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(26)
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(240)
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
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#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(5)
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#define STM32_SYSCLK_FREQUENCY 120000000ul
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/* AHB clock (HCLK) is SYSCLK (120MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
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/* APB1 clock (PCLK1) is HCLK/4 (30MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
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/* APB2 clock (PCLK2) is HCLK/2 (60MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* LED definitions **********************************************************/
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/* LED index values for use with board_userled() */
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#define BOARD_LED1 0
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#define BOARD_NLEDS 1
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/* LED bits for use with board_userled_all() */
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#define BOARD_LED1_BIT (1 << BOARD_LED1)
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/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
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* defined. In that case, the usage by the board port is defined in
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* include/board.h and src/sam_autoleds.c. The LEDs are used to encode
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* OS-related events as follows:
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*
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* ------------------- ---------------------------- ------
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* SYMBOL Meaning LED
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* ------------------- ---------------------------- ------
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*/
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#define LED_STARTED 0 /* NuttX has been started OFF */
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#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF */
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#define LED_IRQSENABLED 0 /* Interrupts enabled OFF */
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#define LED_STACKCREATED 1 /* Idle stack created ON */
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#define LED_INIRQ 2 /* In an interrupt N/C */
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#define LED_SIGNAL 2 /* In a signal handler N/C */
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#define LED_ASSERTION 2 /* An assertion failed N/C */
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#define LED_PANIC 3 /* The system has crashed FLASH */
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#undef LED_IDLE /* MCU is is sleep mode Not used */
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/* Thus if LED is statically on, NuttX has successfully booted and is,
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* apparently, running normally. If LED is flashing at approximately
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* 2Hz, then a fatal error has been detected and the system has halted.
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*/
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/* Alternate function pin selections ****************************************/
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/* UART1 */
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#ifdef CONFIG_STM32_USART1
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# define GPIO_USART1_RX GPIO_USART1_RX_1
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# define GPIO_USART1_TX GPIO_USART1_TX_1
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#endif
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/* SDIO definitions *********************************************************/
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/* Note that slower clocking is required when DMA is disabled in order
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* to avoid RX overrun/TX underrun errors due to delayed responses
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* to service FIFOs in interrupt driven mode.
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*
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* These values have not been tuned!!!
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*
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* SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz
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*/
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#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT)
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/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz
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* DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz
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*/
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#ifdef CONFIG_SDIO_DMA
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# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
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#else
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# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
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#endif
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/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz
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* DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz
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*/
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#ifdef CONFIG_SDIO_DMA
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# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
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#else
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# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
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#endif
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/* DMA Channel/Stream Selections ********************************************/
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/* Stream selections are arbitrary for now but might become important in the
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* future if we set aside more DMA channels/streams.
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*
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* SDIO DMA
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* DMAMAP_SDIO_1 = Channel 4, Stream 3
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* DMAMAP_SDIO_2 = Channel 4, Stream 6
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*/
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#define DMAMAP_SDIO DMAMAP_SDIO_1
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#endif /* __BOARDS_ARM_STM32_EMW3162_INCLUDE_BOARD_H */
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