2023-05-31 15:00:31 +02:00
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/****************************************************************************
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* arch/arm/include/fvp-v8r-aarch32/chip.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_FVP_V8R_CHIP_H
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#define __ARCH_ARM_INCLUDE_FVP_V8R_CHIP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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2023-12-10 03:53:03 +01:00
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/* Number of bytes in x kibibytes/mebibytes/gibibytes */
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2023-05-31 15:00:31 +02:00
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#define KB(x) ((x) << 10)
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#define MB(x) (KB(x) << 10)
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#define GB(x) (MB(UINT64_C(x)) << 10)
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#if defined(CONFIG_ARCH_CHIP_FVP_ARMV8R_AARCH32)
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#define CONFIG_GICD_BASE 0xAF000000
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#define CONFIG_GICR_BASE 0xAF100000
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#define CONFIG_GICR_OFFSET 0x20000
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#define CONFIG_RAMBANK_ADDR 0x00000000
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#define CONFIG_RAMBANK_SIZE MB(128)
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#define CONFIG_RAMBANK_END \
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(CONFIG_RAMBANK_ADDR + CONFIG_RAMBANK_SIZE)
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#define CONFIG_DEVICEIO1_BASEADDR 0xAF000000
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#define CONFIG_DEVICEIO1_SIZE MB(128)
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#define CONFIG_DEVICEIO1_END \
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(CONFIG_DEVICEIO1_BASEADDR + CONFIG_DEVICEIO1_SIZE)
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#define CONFIG_DEVICEIO2_BASEADDR 0x9C000000
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#define CONFIG_DEVICEIO2_SIZE MB(128)
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#define CONFIG_DEVICEIO2_END \
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(CONFIG_DEVICEIO2_BASEADDR + CONFIG_DEVICEIO2_SIZE)
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#define CONFIG_LOAD_BASE 0x00000000
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#define MPID_TO_CLUSTER_ID(mpid) ((mpid) & ~0xff)
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#endif
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#endif /* __ARCH_ARM_INCLUDE_FVP_V8R_CHIP_H */
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