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/****************************************************************************
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* arch/arm/include/nrf53/nrf5340_irq_cpunet.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_NRF53_NRF5340_IRQ_CPUNET_H
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#define __ARCH_ARM_INCLUDE_NRF53_NRF5340_IRQ_CPUNET_H
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* Cortex-M33 External interrupts (vectors >= 16) */
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/* Network core */
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#define NRF53_IRQ_POWER_CLOCK (NRF53_IRQ_EXTINT+5) /* Power, Clock, Bprot */
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#define NRF53_IRQ_RADIO (NRF53_IRQ_EXTINT+8) /* Radio controller */
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#define NRF53_IRQ_RNG (NRF53_IRQ_EXTINT+9) /* Random Number Generator */
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#define NRF53_IRQ_GPIOTE (NRF53_IRQ_EXTINT+10) /* GPIO Task & Event */
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#define NRF53_IRQ_WDT (NRF53_IRQ_EXTINT+11) /* Watchdog Timer */
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#define NRF53_IRQ_TIMER0 (NRF53_IRQ_EXTINT+12) /* Timer 0 */
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#define NRF53_IRQ_ECB (NRF53_IRQ_EXTINT+13) /* AES ECB Mode Encryption */
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#define NRF53_IRQ_CCM_AAR (NRF53_IRQ_EXTINT+14) /* AES CCM Mode Encryption/Accel. Address Resolve */
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#define NRF53_IRQ_TEMP (NRF53_IRQ_EXTINT+16) /* Temperature Sensor */
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#define NRF53_IRQ_RTC0 (NRF53_IRQ_EXTINT+17) /* Real-time counter 0 */
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#define NRF53_IRQ_IPC (NRF53_IRQ_EXTINT+18) /* IPC */
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2023-05-19 18:10:55 +02:00
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#define NRF53_IRQ_SERIAL0 (NRF53_IRQ_EXTINT+19) /* UART/SPI/TWI 0 */
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2022-09-18 13:05:23 +02:00
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#define NRF53_IRQ_EGU0 (NRF53_IRQ_EXTINT+20) /* Event Gen. Unit 0 */
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#define NRF53_IRQ_RTC1 (NRF53_IRQ_EXTINT+22) /* Real-time counter 1 */
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#define NRF53_IRQ_TIMER1 (NRF53_IRQ_EXTINT+24) /* Timer 1 */
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#define NRF53_IRQ_TIMER2 (NRF53_IRQ_EXTINT+25) /* Timer 2 */
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#define NRF53_IRQ_SWI0 (NRF53_IRQ_EXTINT+26) /* Software interrupt 0 */
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#define NRF53_IRQ_SWI1 (NRF53_IRQ_EXTINT+27) /* Software interrupt 1 */
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#define NRF53_IRQ_SWI2 (NRF53_IRQ_EXTINT+28) /* Software interrupt 2 */
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#define NRF53_IRQ_SWI3 (NRF53_IRQ_EXTINT+29) /* Software interrupt 3 / Event Gen. Unit 3 */
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#define NRF53_IRQ_NEXTINT (30)
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#define NRF53_IRQ_NIRQS (NRF53_IRQ_EXTINT+NRF53_IRQ_NEXTINT)
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/* Total number of IRQ numbers */
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#define NR_IRQS NRF53_IRQ_NIRQS
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#endif /* __ARCH_ARM_INCLUDE_NRF53_NRF5340_IRQ_CPUNET_H */
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