2011-03-26 02:04:10 +01:00
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/************************************************************************************
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* arm/arm/src/stm32/stm32_tim.c
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*
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* Copyright (C) 2011 Uros Platise. All rights reserved.
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* Author: Uros Platise <uros.platise@isotel.eu>
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*
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2011-12-16 20:29:41 +01:00
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* With modifications and updates by:
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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2011-03-26 02:04:10 +01:00
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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2011-12-16 20:29:41 +01:00
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/************************************************************************************
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* Included Files
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************************************************************************************/
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2011-03-26 02:04:10 +01:00
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#include <nuttx/config.h>
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#include <nuttx/arch.h>
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#include <nuttx/irq.h>
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#include <sys/types.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <semaphore.h>
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#include <errno.h>
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#include <debug.h>
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#include <arch/board/board.h>
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#include "chip.h"
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#include "up_internal.h"
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#include "up_arch.h"
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#include "stm32_internal.h"
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#include "stm32_gpio.h"
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#include "stm32_tim.h"
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2011-12-16 20:29:41 +01:00
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/************************************************************************************
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* Private Types
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************************************************************************************/
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/* Configuration ********************************************************************/
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/* Timer devices may be used for different purposes. Such special purposes include:
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*
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* - To generate modulated outputs for such things as motor control. If CONFIG_STM32_TIMn
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* is defined then the CONFIG_STM32_TIMn_PWM may also be defined to indicate that
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* the timer is intended to be used for pulsed output modulation.
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*
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* - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is defined then
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* CONFIG_STM32_TIMn_ADC may also be defined to indicate that timer "n" is intended
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* to be used for that purpose.
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*
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* - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined then
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* CONFIG_STM32_TIMn_DAC may also be defined to indicate that timer "n" is intended
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* to be used for that purpose.
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*
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* In any of these cases, the timer will not be used by this timer module.
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*/
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#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || defined(CONFIG_STM32_TIM1_DAC)
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# undef CONFIG_STM32_TIM1
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#endif
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#if defined(CONFIG_STM32_TIM2_PWM || defined (CONFIG_STM32_TIM2_ADC) || defined(CONFIG_STM32_TIM2_DAC)
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# undef CONFIG_STM32_TIM2
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#endif
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#if defined(CONFIG_STM32_TIM3_PWM || defined (CONFIG_STM32_TIM3_ADC) || defined(CONFIG_STM32_TIM3_DAC)
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# undef CONFIG_STM32_TIM3
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#endif
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#if defined(CONFIG_STM32_TIM4_PWM || defined (CONFIG_STM32_TIM4_ADC) || defined(CONFIG_STM32_TIM4_DAC)
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# undef CONFIG_STM32_TIM4
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#endif
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#if defined(CONFIG_STM32_TIM5_PWM || defined (CONFIG_STM32_TIM5_ADC) || defined(CONFIG_STM32_TIM5_DAC)
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# undef CONFIG_STM32_TIM5
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#endif
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#if defined(CONFIG_STM32_TIM6_PWM || defined (CONFIG_STM32_TIM6_ADC) || defined(CONFIG_STM32_TIM6_DAC)
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# undef CONFIG_STM32_TIM6
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#endif
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#if defined(CONFIG_STM32_TIM7_PWM || defined (CONFIG_STM32_TIM7_ADC) || defined(CONFIG_STM32_TIM7_DAC)
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# undef CONFIG_STM32_TIM7
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#endif
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#if defined(CONFIG_STM32_TIM8_PWM || defined (CONFIG_STM32_TIM8_ADC) || defined(CONFIG_STM32_TIM8_DAC)
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# undef CONFIG_STM32_TIM8
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#endif
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#if defined(CONFIG_STM32_TIM9_PWM || defined (CONFIG_STM32_TIM9_ADC) || defined(CONFIG_STM32_TIM9_DAC)
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# undef CONFIG_STM32_TIM9
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#endif
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#if defined(CONFIG_STM32_TIM10_PWM || defined (CONFIG_STM32_TIM10_ADC) || defined(CONFIG_STM32_TIM10_DAC)
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# undef CONFIG_STM32_TIM10
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#endif
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#if defined(CONFIG_STM32_TIM11_PWM || defined (CONFIG_STM32_TIM11_ADC) || defined(CONFIG_STM32_TIM11_DAC)
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# undef CONFIG_STM32_TIM11
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#endif
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#if defined(CONFIG_STM32_TIM12_PWM || defined (CONFIG_STM32_TIM12_ADC) || defined(CONFIG_STM32_TIM12_DAC)
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# undef CONFIG_STM32_TIM12
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#endif
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#if defined(CONFIG_STM32_TIM13_PWM || defined (CONFIG_STM32_TIM13_ADC) || defined(CONFIG_STM32_TIM13_DAC)
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# undef CONFIG_STM32_TIM13
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#endif
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#if defined(CONFIG_STM32_TIM14_PWM || defined (CONFIG_STM32_TIM14_ADC) || defined(CONFIG_STM32_TIM14_DAC)
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# undef CONFIG_STM32_TIM14
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#endif
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/* This module then only compiles if there are enabled timers that are not intended for
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* some other purpose.
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*/
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2011-03-28 17:01:43 +02:00
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#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32_TIM3) || \
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defined(CONFIG_STM32_TIM4) || defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \
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defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8)
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2011-03-26 02:04:10 +01:00
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/************************************************************************************
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* Private Types
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************************************************************************************/
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/** TIM Device Structure
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*/
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struct stm32_tim_priv_s {
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struct stm32_tim_ops_s *ops;
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stm32_tim_mode_t mode;
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2011-03-28 17:01:43 +02:00
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uint32_t base; /** TIMn base address */
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2011-03-26 02:04:10 +01:00
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};
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/************************************************************************************
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* Private Functions
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************************************************************************************/
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/** Get register value by offset */
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static inline uint16_t stm32_tim_getreg(FAR struct stm32_tim_dev_s *dev, uint8_t offset)
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{
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return getreg16( ((struct stm32_tim_priv_s *)dev)->base + offset);
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}
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/** Put register value by offset */
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static inline void stm32_tim_putreg(FAR struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t value)
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{
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//printf("putreg(%8x)=%4x\n", ((struct stm32_tim_priv_s *)dev)->base + offset, value );
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putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset);
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}
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/** Modify register value by offset */
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static inline void stm32_tim_modifyreg(FAR struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits)
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{
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modifyreg16( ((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, setbits);
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}
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static void stm32_tim_reload_counter(FAR struct stm32_tim_dev_s *dev)
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{
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uint16_t val = stm32_tim_getreg(dev, STM32_BTIM_EGR_OFFSET);
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val |= ATIM_EGR_UG;
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stm32_tim_putreg(dev, STM32_BTIM_EGR_OFFSET, val);
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}
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static void stm32_tim_enable(FAR struct stm32_tim_dev_s *dev)
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{
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uint16_t val = stm32_tim_getreg(dev, STM32_BTIM_CR1_OFFSET);
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val |= ATIM_CR1_CEN;
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stm32_tim_reload_counter(dev);
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stm32_tim_putreg(dev, STM32_BTIM_CR1_OFFSET, val);
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}
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static void stm32_tim_disable(FAR struct stm32_tim_dev_s *dev)
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{
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uint16_t val = stm32_tim_getreg(dev, STM32_BTIM_CR1_OFFSET);
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val &= ~ATIM_CR1_CEN;
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stm32_tim_putreg(dev, STM32_BTIM_CR1_OFFSET, val);
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}
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/** Reset timer into system default state, but do not affect output/input pins */
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static void stm32_tim_reset(FAR struct stm32_tim_dev_s *dev)
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{
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((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED;
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stm32_tim_disable(dev);
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}
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2011-03-27 17:03:49 +02:00
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static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode)
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{
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/** \todo Added support for input capture and bipolar dual outputs for TIM8 */
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if (mode & STM32_TIM_CH_MODE_MASK) {
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stm32_configgpio(cfg);
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}
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else {
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stm32_unconfiggpio(cfg);
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}
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}
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2011-03-26 02:04:10 +01:00
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/************************************************************************************
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* Basic Functions
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************************************************************************************/
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static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq)
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{
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int prescaler;
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ASSERT(dev);
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/* Disable Timer? */
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if (freq == 0) {
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stm32_tim_disable(dev);
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return 0;
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}
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#if STM32_NATIM > 0
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if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE ||
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((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE)
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prescaler = STM32_TIM18_FREQUENCY / freq;
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else
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#endif
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prescaler = STM32_TIM27_FREQUENCY / freq;
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/* we need to decrement value for '1', but only, if we are allowed to
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* not to cause underflow. Check for overflow.
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*/
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if (prescaler > 0) prescaler--;
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if (prescaler > 0xFFFF) prescaler = 0xFFFF;
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stm32_tim_putreg(dev, STM32_BTIM_PSC_OFFSET, prescaler);
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stm32_tim_enable(dev);
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return prescaler;
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}
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static void stm32_tim_setperiod(FAR struct stm32_tim_dev_s *dev, uint16_t period)
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{
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ASSERT(dev);
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stm32_tim_putreg(dev, STM32_BTIM_ARR_OFFSET, period);
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}
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static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, int (*handler)(int irq, void *context), int source)
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{
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int vectorno;
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ASSERT(dev);
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ASSERT(source==0);
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switch( ((struct stm32_tim_priv_s *)dev)->base ) {
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2011-03-28 17:01:43 +02:00
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#if CONFIG_STM32_TIM2
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case STM32_TIM2_BASE: vectorno = STM32_IRQ_TIM2; break;
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#endif
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#if CONFIG_STM32_TIM3
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2011-03-26 02:04:10 +01:00
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case STM32_TIM3_BASE: vectorno = STM32_IRQ_TIM3; break;
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2011-03-28 17:01:43 +02:00
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#endif
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#if CONFIG_STM32_TIM4
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case STM32_TIM4_BASE: vectorno = STM32_IRQ_TIM4; break;
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#endif
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#if CONFIG_STM32_TIM5
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case STM32_TIM5_BASE: vectorno = STM32_IRQ_TIM5; break;
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#endif
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#if STM32_NBTIM > 0
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#if CONFIG_STM32_TIM6
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case STM32_TIM6_BASE: vectorno = STM32_IRQ_TIM6; break;
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#endif
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#endif
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#if STM32_NBTIM > 1
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#if CONFIG_STM32_TIM7
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case STM32_TIM7_BASE: vectorno = STM32_IRQ_TIM7; break;
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#endif
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#endif
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2011-03-26 02:04:10 +01:00
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#if STM32_NATIM > 0
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/** \todo add support for multiple sources and callbacks */
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2011-03-28 17:01:43 +02:00
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#if CONFIG_STM32_TIM1
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2011-03-26 02:04:10 +01:00
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case STM32_TIM1_BASE: vectorno = STM32_IRQ_TIM1UP; break;
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2011-03-28 17:01:43 +02:00
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#endif
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#if CONFIG_STM32_TIM8
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2011-03-26 02:04:10 +01:00
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case STM32_TIM8_BASE: vectorno = STM32_IRQ_TIM8UP; break;
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2011-03-28 17:01:43 +02:00
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#endif
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2011-03-26 02:04:10 +01:00
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#endif
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default: return ERROR;
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}
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/* Disable interrupt when callback is removed */
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if (!handler) {
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up_disable_irq(vectorno);
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irq_detach(vectorno);
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return OK;
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}
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/* Otherwise set callback and enable interrupt */
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irq_attach(vectorno, handler);
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up_enable_irq(vectorno);
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// up_prioritize_irq(vectorno, NVIC_SYSH_PRIORITY_DEFAULT);
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return OK;
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}
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static void stm32_tim_enableint(FAR struct stm32_tim_dev_s *dev, int source)
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{
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ASSERT(dev);
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stm32_tim_modifyreg(dev, STM32_BTIM_DIER_OFFSET, 0, ATIM_DIER_UIE);
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}
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|
|
|
|
|
|
|
|
|
|
|
static void stm32_tim_disableint(FAR struct stm32_tim_dev_s *dev, int source)
|
|
|
|
{
|
|
|
|
ASSERT(dev);
|
|
|
|
stm32_tim_modifyreg(dev, STM32_BTIM_DIER_OFFSET, ATIM_DIER_UIE, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static void stm32_tim_ackint(FAR struct stm32_tim_dev_s *dev, int source)
|
|
|
|
{
|
|
|
|
stm32_tim_putreg(dev, STM32_BTIM_SR_OFFSET, ~ATIM_SR_UIF);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
* General Functions
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode)
|
|
|
|
{
|
|
|
|
uint16_t val = ATIM_CR1_CEN | ATIM_CR1_ARPE;
|
|
|
|
|
|
|
|
ASSERT(dev);
|
|
|
|
|
|
|
|
/* This function is not supported on basic timers. To enable or
|
|
|
|
* disable it, simply set its clock to valid frequency or zero.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#if STM32_NBTIM > 0
|
|
|
|
if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE
|
|
|
|
#endif
|
|
|
|
#if STM32_NBTIM > 1
|
|
|
|
|| ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE
|
|
|
|
#endif
|
|
|
|
#if STM32_NBTIM > 0
|
|
|
|
) return ERROR;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* Decode operational modes */
|
|
|
|
|
|
|
|
switch(mode & STM32_TIM_MODE_MASK) {
|
|
|
|
|
|
|
|
case STM32_TIM_MODE_DISABLED:
|
|
|
|
val = 0;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case STM32_TIM_MODE_DOWN:
|
|
|
|
val |= ATIM_CR1_DIR;
|
|
|
|
|
|
|
|
case STM32_TIM_MODE_UP:
|
|
|
|
break;
|
|
|
|
|
|
|
|
case STM32_TIM_MODE_UPDOWN:
|
|
|
|
val |= ATIM_CR1_CENTER1;
|
|
|
|
// Our default: Interrupts are generated on compare, when counting down
|
|
|
|
break;
|
|
|
|
|
|
|
|
case STM32_TIM_MODE_PULSE:
|
|
|
|
val |= ATIM_CR1_OPM;
|
|
|
|
break;
|
|
|
|
|
|
|
|
default: return ERROR;
|
|
|
|
}
|
|
|
|
|
|
|
|
stm32_tim_reload_counter(dev);
|
|
|
|
stm32_tim_putreg(dev, STM32_BTIM_CR1_OFFSET, val);
|
|
|
|
|
|
|
|
#if STM32_NATIM > 0
|
|
|
|
/* Advanced registers require Main Output Enable */
|
|
|
|
|
|
|
|
if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE ||
|
|
|
|
((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) {
|
|
|
|
stm32_tim_modifyreg(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel, stm32_tim_channel_t mode)
|
|
|
|
{
|
|
|
|
uint16_t ccmr_val = 0;
|
|
|
|
uint16_t ccer_val = stm32_tim_getreg(dev, STM32_GTIM_CCER_OFFSET);
|
|
|
|
uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET;
|
|
|
|
|
|
|
|
ASSERT(dev);
|
|
|
|
|
|
|
|
/* Further we use range as 0..3; if channel=0 it will also overflow here */
|
|
|
|
|
|
|
|
if (--channel > 4) return ERROR;
|
|
|
|
|
|
|
|
/* Assume that channel is disabled and polarity is active high */
|
|
|
|
|
|
|
|
ccer_val &= ~(3 << (channel << 2));
|
|
|
|
|
|
|
|
/* This function is not supported on basic timers. To enable or
|
|
|
|
* disable it, simply set its clock to valid frequency or zero.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#if STM32_NBTIM > 0
|
|
|
|
if ( ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE
|
|
|
|
#endif
|
|
|
|
#if STM32_NBTIM > 1
|
|
|
|
|| ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE
|
|
|
|
#endif
|
|
|
|
#if STM32_NBTIM > 0
|
|
|
|
) return ERROR;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* Decode configuration */
|
|
|
|
|
|
|
|
switch(mode & STM32_TIM_CH_MODE_MASK) {
|
|
|
|
|
|
|
|
case STM32_TIM_CH_DISABLED:
|
|
|
|
break;
|
|
|
|
|
|
|
|
case STM32_TIM_CH_OUTPWM:
|
|
|
|
ccmr_val = (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) + ATIM_CCMR1_OC1PE;
|
|
|
|
ccer_val |= ATIM_CCER_CC1E << (channel << 2);
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
return ERROR;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Set polarity */
|
|
|
|
|
|
|
|
if (mode & STM32_TIM_CH_POLARITY_NEG)
|
|
|
|
ccer_val |= ATIM_CCER_CC1P << (channel << 2);
|
|
|
|
|
|
|
|
/* define its position (shift) and get register offset */
|
|
|
|
|
|
|
|
if (channel & 1) ccmr_val <<= 8;
|
|
|
|
if (channel > 1) ccmr_offset = STM32_GTIM_CCMR2_OFFSET;
|
|
|
|
|
|
|
|
stm32_tim_putreg(dev, ccmr_offset, ccmr_val);
|
|
|
|
stm32_tim_putreg(dev, STM32_GTIM_CCER_OFFSET, ccer_val);
|
|
|
|
|
2011-03-27 17:03:49 +02:00
|
|
|
/* set GPIO */
|
|
|
|
|
|
|
|
switch( ((struct stm32_tim_priv_s *)dev)->base ) {
|
2011-03-28 17:01:43 +02:00
|
|
|
#if CONFIG_STM32_TIM2
|
2011-03-27 17:03:49 +02:00
|
|
|
case STM32_TIM2_BASE:
|
|
|
|
switch(channel) {
|
|
|
|
case 0: stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); break;
|
|
|
|
case 1: stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); break;
|
|
|
|
case 2: stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); break;
|
|
|
|
case 3: stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); break;
|
|
|
|
}
|
|
|
|
break;
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
|
|
|
#if CONFIG_STM32_TIM3
|
2011-03-27 17:03:49 +02:00
|
|
|
case STM32_TIM3_BASE:
|
|
|
|
switch(channel) {
|
|
|
|
case 0: stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); break;
|
|
|
|
case 1: stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); break;
|
|
|
|
case 2: stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); break;
|
|
|
|
case 3: stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); break;
|
|
|
|
}
|
|
|
|
break;
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
|
|
|
#if CONFIG_STM32_TIM4
|
2011-03-27 17:03:49 +02:00
|
|
|
case STM32_TIM4_BASE:
|
|
|
|
switch(channel) {
|
|
|
|
case 0: stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); break;
|
|
|
|
case 1: stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); break;
|
|
|
|
case 2: stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); break;
|
|
|
|
case 3: stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); break;
|
|
|
|
}
|
|
|
|
break;
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
|
|
|
#if CONFIG_STM32_TIM5
|
2011-03-27 17:03:49 +02:00
|
|
|
case STM32_TIM5_BASE:
|
|
|
|
switch(channel) {
|
|
|
|
case 0: stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); break;
|
|
|
|
case 1: stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); break;
|
|
|
|
case 2: stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); break;
|
|
|
|
case 3: stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); break;
|
|
|
|
}
|
|
|
|
break;
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
2011-03-27 17:03:49 +02:00
|
|
|
|
2011-03-27 21:53:36 +02:00
|
|
|
#if STM32_NATIM > 0
|
2011-03-28 17:01:43 +02:00
|
|
|
#if CONFIG_STM32_TIM1
|
2011-03-27 21:53:36 +02:00
|
|
|
case STM32_TIM1_BASE:
|
|
|
|
switch(channel) {
|
|
|
|
case 0: stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break;
|
|
|
|
case 1: stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break;
|
|
|
|
case 2: stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break;
|
|
|
|
case 3: stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break;
|
|
|
|
}
|
|
|
|
break;
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
|
|
|
#if CONFIG_STM32_TIM8
|
2011-03-27 17:03:49 +02:00
|
|
|
case STM32_TIM8_BASE:
|
|
|
|
switch(channel) {
|
|
|
|
case 0: stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break;
|
|
|
|
case 1: stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break;
|
|
|
|
case 2: stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break;
|
|
|
|
case 3: stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break;
|
|
|
|
}
|
|
|
|
break;
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
2011-03-27 21:53:36 +02:00
|
|
|
#endif
|
2011-03-27 17:03:49 +02:00
|
|
|
default: return ERROR;
|
|
|
|
}
|
|
|
|
|
2011-03-26 02:04:10 +01:00
|
|
|
return OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static int stm32_tim_setcompare(FAR struct stm32_tim_dev_s *dev, uint8_t channel, uint16_t compare)
|
|
|
|
{
|
|
|
|
ASSERT(dev);
|
|
|
|
|
|
|
|
switch(channel) {
|
|
|
|
case 1: stm32_tim_putreg(dev, STM32_GTIM_CCR1_OFFSET, compare); break;
|
|
|
|
case 2: stm32_tim_putreg(dev, STM32_GTIM_CCR2_OFFSET, compare); break;
|
|
|
|
case 3: stm32_tim_putreg(dev, STM32_GTIM_CCR3_OFFSET, compare); break;
|
|
|
|
case 4: stm32_tim_putreg(dev, STM32_GTIM_CCR4_OFFSET, compare); break;
|
|
|
|
default: return ERROR;
|
|
|
|
}
|
|
|
|
return OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static int stm32_tim_getcapture(FAR struct stm32_tim_dev_s *dev, uint8_t channel)
|
|
|
|
{
|
|
|
|
ASSERT(dev);
|
|
|
|
|
|
|
|
switch(channel) {
|
|
|
|
case 1: return stm32_tim_getreg(dev, STM32_GTIM_CCR1_OFFSET);
|
|
|
|
case 2: return stm32_tim_getreg(dev, STM32_GTIM_CCR2_OFFSET);
|
|
|
|
case 3: return stm32_tim_getreg(dev, STM32_GTIM_CCR3_OFFSET);
|
|
|
|
case 4: return stm32_tim_getreg(dev, STM32_GTIM_CCR4_OFFSET);
|
|
|
|
}
|
|
|
|
return ERROR;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
* Advanced Functions
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
/** \todo Advanced functions for the STM32_ATIM */
|
|
|
|
|
|
|
|
|
|
|
|
/************************************************************************************
|
|
|
|
* Device Structures, Instantiation
|
|
|
|
************************************************************************************/
|
|
|
|
|
|
|
|
struct stm32_tim_ops_s stm32_tim_ops = {
|
|
|
|
.setmode = &stm32_tim_setmode,
|
|
|
|
.setclock = &stm32_tim_setclock,
|
|
|
|
.setperiod = &stm32_tim_setperiod,
|
|
|
|
.setchannel = &stm32_tim_setchannel,
|
|
|
|
.setcompare = &stm32_tim_setcompare,
|
|
|
|
.getcapture = &stm32_tim_getcapture,
|
|
|
|
.setisr = &stm32_tim_setisr,
|
|
|
|
.enableint = &stm32_tim_enableint,
|
|
|
|
.disableint = &stm32_tim_disableint,
|
|
|
|
.ackint = &stm32_tim_ackint
|
|
|
|
};
|
|
|
|
|
2011-03-28 17:01:43 +02:00
|
|
|
#if CONFIG_STM32_TIM2
|
|
|
|
struct stm32_tim_priv_s stm32_tim2_priv = {
|
|
|
|
.ops = &stm32_tim_ops,
|
|
|
|
.mode = STM32_TIM_MODE_UNUSED,
|
|
|
|
.base = STM32_TIM2_BASE,
|
|
|
|
};
|
|
|
|
#endif
|
2011-03-26 02:04:10 +01:00
|
|
|
|
2011-03-28 17:01:43 +02:00
|
|
|
#if CONFIG_STM32_TIM3
|
2011-03-26 02:04:10 +01:00
|
|
|
struct stm32_tim_priv_s stm32_tim3_priv = {
|
|
|
|
.ops = &stm32_tim_ops,
|
|
|
|
.mode = STM32_TIM_MODE_UNUSED,
|
|
|
|
.base = STM32_TIM3_BASE,
|
|
|
|
};
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#if CONFIG_STM32_TIM4
|
|
|
|
struct stm32_tim_priv_s stm32_tim4_priv = {
|
|
|
|
.ops = &stm32_tim_ops,
|
|
|
|
.mode = STM32_TIM_MODE_UNUSED,
|
|
|
|
.base = STM32_TIM4_BASE,
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#if CONFIG_STM32_TIM5
|
|
|
|
struct stm32_tim_priv_s stm32_tim5_priv = {
|
|
|
|
.ops = &stm32_tim_ops,
|
|
|
|
.mode = STM32_TIM_MODE_UNUSED,
|
|
|
|
.base = STM32_TIM5_BASE,
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#if STM32_NBTIM > 0
|
|
|
|
#if CONFIG_STM32_TIM6
|
|
|
|
struct stm32_tim_priv_s stm32_tim6_priv = {
|
|
|
|
.ops = &stm32_tim_ops,
|
|
|
|
.mode = STM32_TIM_MODE_UNUSED,
|
|
|
|
.base = STM32_TIM6_BASE,
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#if STM32_NBTIM > 1
|
|
|
|
#if CONFIG_STM32_TIM7
|
|
|
|
struct stm32_tim_priv_s stm32_tim7_priv = {
|
|
|
|
.ops = &stm32_tim_ops,
|
|
|
|
.mode = STM32_TIM_MODE_UNUSED,
|
|
|
|
.base = STM32_TIM7_BASE,
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
#endif
|
2011-03-26 02:04:10 +01:00
|
|
|
|
|
|
|
#if STM32_NATIM > 0
|
|
|
|
|
2011-07-06 23:18:34 +02:00
|
|
|
#if CONFIG_STM32_TIM1
|
2011-03-26 02:04:10 +01:00
|
|
|
struct stm32_tim_priv_s stm32_tim1_priv = {
|
|
|
|
.ops = &stm32_tim_ops,
|
|
|
|
.mode = STM32_TIM_MODE_UNUSED,
|
|
|
|
.base = STM32_TIM1_BASE,
|
|
|
|
};
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
2011-03-26 02:04:10 +01:00
|
|
|
|
2011-03-28 17:01:43 +02:00
|
|
|
#if CONFIG_STM32_TIM8
|
2011-03-26 02:04:10 +01:00
|
|
|
struct stm32_tim_priv_s stm32_tim8_priv = {
|
|
|
|
.ops = &stm32_tim_ops,
|
|
|
|
.mode = STM32_TIM_MODE_UNUSED,
|
|
|
|
.base = STM32_TIM8_BASE,
|
|
|
|
};
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2011-03-28 17:01:43 +02:00
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#endif
|
2011-03-26 02:04:10 +01:00
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|
#endif
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|
|
/************************************************************************************
|
|
|
|
* Public Function - Initialization
|
|
|
|
************************************************************************************/
|
|
|
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|
|
|
|
FAR struct stm32_tim_dev_s * stm32_tim_init(int timer)
|
|
|
|
{
|
|
|
|
struct stm32_tim_dev_s * dev = NULL;
|
|
|
|
|
|
|
|
/* Get structure and enable power */
|
|
|
|
|
|
|
|
switch(timer) {
|
2011-03-28 17:01:43 +02:00
|
|
|
#if CONFIG_STM32_TIM2
|
|
|
|
case 2:
|
|
|
|
dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv;
|
|
|
|
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM2EN);
|
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|
|
break;
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|
|
|
#endif
|
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|
|
#if CONFIG_STM32_TIM3
|
2011-03-26 02:04:10 +01:00
|
|
|
case 3:
|
|
|
|
dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv;
|
|
|
|
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN);
|
|
|
|
break;
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
|
|
|
#if CONFIG_STM32_TIM4
|
|
|
|
case 4:
|
|
|
|
dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv;
|
|
|
|
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM4EN);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#if CONFIG_STM32_TIM5
|
|
|
|
case 5:
|
|
|
|
dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv;
|
|
|
|
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM5EN);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#if STM32_NBTIM > 0
|
|
|
|
#if CONFIG_STM32_TIM6
|
|
|
|
case 6:
|
|
|
|
dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv;
|
|
|
|
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM6EN);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#endif
|
|
|
|
#if STM32_NBTIM > 1
|
|
|
|
#if CONFIG_STM32_TIM7
|
|
|
|
case 7:
|
|
|
|
dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv;
|
|
|
|
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM7EN);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#endif
|
|
|
|
|
2011-03-26 02:04:10 +01:00
|
|
|
#if STM32_NATIM > 0
|
2011-03-28 17:01:43 +02:00
|
|
|
#if CONFIG_STM32_TIM1
|
2011-03-26 02:04:10 +01:00
|
|
|
case 1:
|
|
|
|
dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv;
|
|
|
|
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN);
|
|
|
|
break;
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
|
|
|
#if CONFIG_STM32_TIM8
|
2011-03-26 02:04:10 +01:00
|
|
|
case 8:
|
|
|
|
dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv;
|
|
|
|
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN);
|
|
|
|
break;
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
2011-03-26 02:04:10 +01:00
|
|
|
#endif
|
|
|
|
default: return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Is device already allocated */
|
|
|
|
|
|
|
|
if ( ((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
stm32_tim_reset(dev);
|
|
|
|
|
|
|
|
return dev;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2011-03-28 17:01:43 +02:00
|
|
|
/** \todo Detach interrupts, and close down all TIM Channels */
|
2011-03-26 02:04:10 +01:00
|
|
|
int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev)
|
|
|
|
{
|
|
|
|
ASSERT(dev);
|
|
|
|
|
|
|
|
/* Disable power */
|
|
|
|
|
|
|
|
switch( ((struct stm32_tim_priv_s *)dev)->base ) {
|
2011-03-28 17:01:43 +02:00
|
|
|
#if CONFIG_STM32_TIM2
|
|
|
|
case STM32_TIM2_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0); break;
|
|
|
|
#endif
|
|
|
|
#if CONFIG_STM32_TIM3
|
2011-03-26 02:04:10 +01:00
|
|
|
case STM32_TIM3_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM3EN, 0); break;
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
|
|
|
#if CONFIG_STM32_TIM4
|
|
|
|
case STM32_TIM4_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM4EN, 0); break;
|
|
|
|
#endif
|
|
|
|
#if CONFIG_STM32_TIM5
|
|
|
|
case STM32_TIM5_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0); break;
|
|
|
|
#endif
|
|
|
|
#if STM32_NBTIM > 0
|
|
|
|
#if CONFIG_STM32_TIM6
|
|
|
|
case STM32_TIM6_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM6EN, 0); break;
|
|
|
|
#endif
|
|
|
|
#endif
|
|
|
|
#if STM32_NBTIM > 1
|
|
|
|
#if CONFIG_STM32_TIM7
|
|
|
|
case STM32_TIM7_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM7EN, 0); break;
|
|
|
|
#endif
|
|
|
|
#endif
|
2011-03-26 02:04:10 +01:00
|
|
|
|
|
|
|
#if STM32_NATIM > 0
|
2011-03-28 17:01:43 +02:00
|
|
|
#if CONFIG_STM32_TIM1
|
2011-03-26 02:04:10 +01:00
|
|
|
case STM32_TIM1_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break;
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
|
|
|
#if CONFIG_STM32_TIM8
|
2011-03-26 02:04:10 +01:00
|
|
|
case STM32_TIM8_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break;
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif
|
2011-03-26 02:04:10 +01:00
|
|
|
#endif
|
|
|
|
default: return ERROR;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Mark it as free */
|
|
|
|
|
|
|
|
((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED;
|
|
|
|
|
|
|
|
return OK;
|
|
|
|
}
|
2011-03-27 21:53:36 +02:00
|
|
|
|
2011-03-28 17:01:43 +02:00
|
|
|
#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM8) */
|