2023-10-14 22:11:19 +02:00
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/****************************************************************************
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* boards/arm/stm32/stm32f401rc-rs485/include/board.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_STM32F401RC_RS485_INCLUDE_BOARD_H
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#define __BOARDS_ARM_STM32F401RC_RS485_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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2023-11-11 20:44:03 +01:00
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/* The STM32F401RC-RS485 uses an external 32kHz cristal (X2) to enable HSE
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* clock.
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2023-10-14 22:11:19 +02:00
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*
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* System Clock source : PLL (HSI)
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* SYSCLK(Hz) : 84000000 Determined by PLL
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* configuration
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* HCLK(Hz) : 84000000 (STM32_RCC_CFGR_HPRE)
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* AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE)
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* APB1 Prescaler : 2 (STM32_RCC_CFGR_PPRE1)
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* APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2)
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* HSI Frequency(Hz) : 16000000 (nominal)
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* PLLM : 16 (STM32_PLLCFG_PLLM)
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* PLLN : 336 (STM32_PLLCFG_PLLN)
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* PLLP : 4 (STM32_PLLCFG_PLLP)
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* PLLQ : 7 (STM32_PLLCFG_PPQ)
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* Flash Latency(WS) : 5
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* Prefetch Buffer : OFF
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* Instruction cache : ON
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* Data cache : ON
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* Require 48MHz for USB OTG FS, : Enabled
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* SDIO and RNG clock
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*/
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/* HSI - 16 MHz RC factory-trimmed
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* LSI - 32 KHz RC
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* HSE - not installed
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* LSE - not installed
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*/
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#define STM32_HSI_FREQUENCY 16000000ul
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#define STM32_LSI_FREQUENCY 32000
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#define STM32_BOARD_USEHSI 1
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/* Main PLL Configuration.
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*
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* Formulae:
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*
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* VCO input frequency = PLL input clock frequency / PLLM,
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* 2 <= PLLM <= 63
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* VCO output frequency = VCO input frequency × PLLN,
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* 192 <= PLLN <= 432
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* PLL output clock frequency = VCO frequency / PLLP,
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* PLLP = 2, 4, 6, or 8
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* USB OTG FS clock frequency = VCO frequency / PLLQ,
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* 2 <= PLLQ <= 15
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*
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* We would like to have SYSYCLK=84MHz and we must have the USB clock= 48MHz.
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* Some possible solutions include:
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*
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* PLLN=210 PLLM=5 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000
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* PLLN=210 PLLM=10 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000
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* PLLN=336 PLLM=8 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000
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* PLLN=336 PLLM=16 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000
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* PLLN=420 PLLM=10 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000
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* PLLN=420 PLLM=20 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000
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*
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* We will configure like this
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*
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* PLL source is HSI
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* PLL_VCO = (STM32_HSI_FREQUENCY / PLLM) * PLLN
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* = (16,000,000 / 16) * 336
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* = 336,000,000
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* SYSCLK = PLL_VCO / PLLP
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* = 336,000,000 / 4 = 84,000,000
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* USB OTG FS and SDIO Clock
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* = PLL_VCO / PLLQ
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* = 336,000,000 / 7 = 48,000,000
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*
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* REVISIT: Trimming of the HSI is not yet supported.
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*/
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(16)
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336)
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4
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#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7)
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#define STM32_SYSCLK_FREQUENCY 84000000ul
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/* AHB clock (HCLK) is SYSCLK (84MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
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/* APB1 clock (PCLK1) is HCLK/2 (42MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* Timers driven from APB1 will be twice PCLK1 */
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/* REVISIT */
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
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/* APB2 clock (PCLK2) is HCLK (84MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1)
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/* Timers driven from APB2 will be twice PCLK2 */
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/* REVISIT */
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#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY)
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
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* otherwise frequency is 2xAPBx.
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* Note: TIM1,8 are on APB2, others on APB1
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*/
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/* REVISIT */
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#define BOARD_TIM1_FREQUENCY (2*STM32_PCLK2_FREQUENCY)
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#define BOARD_TIM2_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM3_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM4_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM5_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM6_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM7_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM8_FREQUENCY (2*STM32_PCLK2_FREQUENCY)
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/* SDIO dividers. Note that slower clocking is required when DMA is disabled
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* in order to avoid RX overrun/TX underrun errors due to delayed responses
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* to service FIFOs in interrupt driven mode. These values have not been
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* tuned!!!
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*
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* HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz
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*/
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/* REVISIT */
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#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT)
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/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz
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* DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz
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*/
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/* REVISIT */
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#ifdef CONFIG_SDIO_DMA
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# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
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#else
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# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT)
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#endif
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/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz
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* DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz
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*/
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/* REVISIT */
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#ifdef CONFIG_SDIO_DMA
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# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
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#else
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# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT)
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#endif
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* DMA Channel/Stream Selections ********************************************/
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/* Stream selections are arbitrary for now but might become important in
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* the future is we set aside more DMA channels/streams.
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*
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* SDIO DMA
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* DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA
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* DMAMAP_SDIO_2 = Channel 4, Stream 6
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*/
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#define DMAMAP_SDIO DMAMAP_SDIO_1
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/* Need to VERIFY fwb */
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#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1
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#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1
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#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX
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#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX
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/* Alternate function pin selections ****************************************/
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/* USART1:
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* RXD: PA10 CN9 pin 3, CN10 pin 33
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* PB7 CN7 pin 21
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* TXD: PA9 CN5 pin 1, CN10 pin 21
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* PB6 CN5 pin 3, CN10 pin 17
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*/
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#if 1
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# define GPIO_USART1_RX GPIO_USART1_RX_1 /* PA10 */
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# define GPIO_USART1_TX GPIO_USART1_TX_1 /* PA9 */
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#else
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# define GPIO_USART1_RX GPIO_USART1_RX_2 /* PB7 */
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# define GPIO_USART1_TX GPIO_USART1_TX_2 /* PB6 */
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#endif
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/* USART2:
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* RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37
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* PD6
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* TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35
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* PD5
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*/
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#define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */
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#define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA2 */
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#define GPIO_USART2_RTS GPIO_USART2_RTS_2
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#define GPIO_USART2_CTS GPIO_USART2_CTS_2
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/* USART6:
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* RXD: PC7 CN5 pin2, CN10 pin 19
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* PA12 CN10, pin 12
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* TXD: PC6 CN10, pin 4
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* PA11 CN10, pin 14
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*/
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#define GPIO_USART6_RX GPIO_USART6_RX_1 /* PC7 */
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#define GPIO_USART6_TX GPIO_USART6_TX_1 /* PC6 */
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/* UART RX DMA configurations */
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#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2
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#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2
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/* I2C
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*
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* The optional _GPIO configurations allow the I2C driver to manually
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* reset the bus to clear stuck slaves. They match the pin configuration,
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* but are normally-high GPIOs.
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*/
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#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2
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#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2
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#define GPIO_I2C1_SCL_GPIO \
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(GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8)
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#define GPIO_I2C1_SDA_GPIO \
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(GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9)
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#define GPIO_I2C2_SCL GPIO_I2C2_SCL_1
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#define GPIO_I2C2_SDA GPIO_I2C2_SDA_1
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#define GPIO_I2C2_SCL_GPIO \
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(GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN10)
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#define GPIO_I2C2_SDA_GPIO \
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(GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN11)
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/* SPI
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*
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* There are sensors on SPI1, and SPI2 is connected to the FRAM.
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*/
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#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1
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#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1
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#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1
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#define GPIO_SPI2_MISO GPIO_SPI2_MISO_1
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#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1
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#define GPIO_SPI2_SCK GPIO_SPI2_SCK_2
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/* LEDs
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*
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2023-11-11 20:44:03 +01:00
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* The STM32F401RC-RS485 boards provide 4 blue user LEDs. LD1, LD2, LD3
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* and LD4 that are connected to MCU I/O pins PC0, PC1, PC2 and PC3.
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2023-10-14 22:11:19 +02:00
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* - When the I/O is HIGH value, the LED is on.
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* - When the I/O is LOW, the LED is off.
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*/
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/* LED index values for use with board_userled() */
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2023-11-11 20:44:03 +01:00
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#define BOARD_LD1 0
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#define BOARD_LD2 1
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#define BOARD_LD3 2
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#define BOARD_LD4 3
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#define BOARD_NLEDS 4
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2023-10-14 22:11:19 +02:00
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/* LED bits for use with board_userled_all() */
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2023-11-11 20:44:03 +01:00
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#define BOARD_LED1_BIT (1 << BOARD_LD1)
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#define BOARD_LED2_BIT (1 << BOARD_LD2)
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#define BOARD_LED3_BIT (1 << BOARD_LD3)
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#define BOARD_LED4_BIT (1 << BOARD_LD4)
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2023-10-14 22:11:19 +02:00
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/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
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* defined. In that case, the usage by the board port is defined in
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* include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related
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* events as follows when the red LED (PE24) is available:
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*
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* SYMBOL Meaning LD2
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* ------------------- ----------------------- -----------
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* LED_STARTED NuttX has been started OFF
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* LED_HEAPALLOCATE Heap has been allocated OFF
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* LED_IRQSENABLED Interrupts enabled OFF
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* LED_STACKCREATED Idle stack created ON
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* LED_INIRQ In an interrupt No change
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* LED_SIGNAL In a signal handler No change
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* LED_ASSERTION An assertion failed No change
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* LED_PANIC The system has crashed Blinking
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* LED_IDLE MCU is is sleep mode Not used
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|
*
|
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|
|
* Thus if LD2, NuttX has successfully booted and is, apparently, running
|
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|
* normally. If LD2 is flashing at approximately 2Hz, then a fatal error
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|
* has been detected and the system has halted.
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|
*/
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|
|
#define LED_STARTED 0
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|
#define LED_HEAPALLOCATE 0
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|
#define LED_IRQSENABLED 0
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|
#define LED_STACKCREATED 1
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|
#define LED_INIRQ 2
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|
#define LED_SIGNAL 2
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|
|
#define LED_ASSERTION 2
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|
|
#define LED_PANIC 1
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|
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|
|
/* Buttons
|
2023-11-18 15:18:42 +01:00
|
|
|
|
* The STM32F401RC-RS485 has 4 user buttons: SW3, SW4, SW5 and
|
|
|
|
|
|
* SW6. They are connected to PB13, PB14, PB15 and PC6 respectively.
|
2023-10-14 22:11:19 +02:00
|
|
|
|
*/
|
|
|
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|
|
|
2023-11-18 15:18:42 +01:00
|
|
|
|
#define BUTTON_SW3 0
|
|
|
|
|
|
#define BUTTON_SW4 1
|
|
|
|
|
|
#define BUTTON_SW5 2
|
|
|
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|
#define BUTTON_SW6 3
|
|
|
|
|
|
#define NUM_BUTTONS 4
|
2023-10-14 22:11:19 +02:00
|
|
|
|
|
2023-11-18 15:18:42 +01:00
|
|
|
|
#define BUTTON_SW3_BIT (1 << BUTTON_SW3)
|
|
|
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|
#define BUTTON_SW4_BIT (1 << BUTTON_SW4)
|
|
|
|
|
|
#define BUTTON_SW5_BIT (1 << BUTTON_SW5)
|
|
|
|
|
|
#define BUTTON_SW6_BIT (1 << BUTTON_SW6)
|
2023-10-14 22:11:19 +02:00
|
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|
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|
|
#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_1 | GPIO_PULLUP)
|
|
|
|
|
|
#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1 | GPIO_PULLUP)
|
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|
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|
|
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|
|
#endif /* __BOARDS_ARM_STM32F401RC_RS485_INCLUDE_BOARD_H */
|
