2010-06-15 03:12:44 +02:00
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/****************************************************************************
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* arch/arm/src/lpc17xx/lpc17_spi.c
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*
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* Copyright (C) 2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <semaphore.h>
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#include <errno.h>
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#include <debug.h>
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#include <arch/board/board.h>
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#include <nuttx/arch.h>
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#include <nuttx/spi.h>
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#include "up_internal.h"
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#include "up_arch.h"
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#include "chip.h"
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#include "lpc17_internal.h"
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#include "lpc17_syscon.h"
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#include "lpc17_pinconn.h"
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#include "lpc17_spi.h"
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#ifdef CONFIG_LPC17_SPI
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/****************************************************************************
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* Definitions
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****************************************************************************/
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/* Enables debug output from this file (needs CONFIG_DEBUG too) */
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#undef SPI_DEBUG /* Define to enable debug */
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#undef SPI_VERBOSE /* Define to enable verbose debug */
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#ifdef SPI_DEBUG
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# define spidbg lldbg
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# ifdef SPI_VERBOSE
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# define spivdbg lldbg
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# else
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# define spivdbg(x...)
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# endif
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#else
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# undef SPI_VERBOSE
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# define spidbg(x...)
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# define spivdbg(x...)
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#endif
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/* SPI Clocking.
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*
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* The CPU clock by 1, 2, 4, or 8 to get the SPI peripheral clock (SPI_CLOCK).
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* SPI_CLOCK may be further divided by 8-254 to get the SPI clock. If we
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* want a usable range of 4KHz to 25MHz for the SPI, then:
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*
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* 1. SPICLK must be greater than (8*25MHz) = 200MHz (so we can't reach 25MHz),
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* and
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* 2. SPICLK must be less than (254*40Khz) = 101.6MHz.
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*
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* If we assume that CCLK less than or equal to 100MHz, we can just
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* use the CCLK undivided to get the SPI_CLOCK.
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*/
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#define SPI_PCLKSET_DIV SYSCON_PCLKSEL_CCLK
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#define SPI_CLOCK LPC17_CCLK
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/****************************************************************************
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* Private Types
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****************************************************************************/
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struct lpc17_spidev_s
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{
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struct spi_dev_s spidev; /* Externally visible part of the SPI interface */
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#ifndef CONFIG_SPI_OWNBUS
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sem_t exclsem; /* Held while chip is selected for mutual exclusion */
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uint32_t frequency; /* Requested clock frequency */
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uint32_t actual; /* Actual clock frequency */
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2010-06-15 16:46:53 +02:00
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uint8_t nbits; /* Width of word in bits (8 to 16) */
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2010-06-15 03:12:44 +02:00
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uint8_t mode; /* Mode 0,1,2,3 */
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#endif
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};
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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/* SPI methods */
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#ifndef CONFIG_SPI_OWNBUS
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static int spi_lock(FAR struct spi_dev_s *dev, bool lock);
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#endif
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static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
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static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency);
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static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode);
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static void spi_setbits(FAR struct spi_dev_s *dev, int nbits);
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static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t ch);
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static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords);
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static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords);
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/****************************************************************************
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* Private Data
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****************************************************************************/
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static const struct spi_ops_s g_spiops =
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{
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#ifndef CONFIG_SPI_OWNBUS
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.lock = spi_lock,
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#endif
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.select = lpc17_spiselect,
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.setfrequency = spi_setfrequency,
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.setmode = spi_setmode,
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.setbits = spi_setbits,
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.status = lpc17_spistatus,
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.send = spi_send,
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.sndblock = spi_sndblock,
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.recvblock = spi_recvblock,
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.registercallback = 0, /* Not implemented */
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};
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static struct lpc17_spidev_s g_spidev =
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{
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.spidev = { &g_spiops },
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};
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: spi_lock
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*
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* Description:
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* On SPI busses where there are multiple devices, it will be necessary to
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* lock SPI to have exclusive access to the busses for a sequence of
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* transfers. The bus should be locked before the chip is selected. After
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* locking the SPI bus, the caller should then also call the setfrequency,
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* setbits, and setmode methods to make sure that the SPI is properly
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* configured for the device. If the SPI buss is being shared, then it
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* may have been left in an incompatible state.
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*
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* Input Parameters:
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* dev - Device-specific state data
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* lock - true: Lock spi bus, false: unlock SPI bus
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#ifndef CONFIG_SPI_OWNBUS
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static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
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{
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FAR struct lpc17_spidev_s *priv = (FAR struct lpc17_spidev_s *)dev;
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if (lock)
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{
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/* Take the semaphore (perhaps waiting) */
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while (sem_wait(&priv->exclsem) != 0)
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{
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/* The only case that an error should occur here is if the wait was awakened
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* by a signal.
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*/
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ASSERT(errno == EINTR);
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}
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}
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else
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{
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(void)sem_post(&priv->exclsem);
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}
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return OK;
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}
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#endif
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/****************************************************************************
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* Name: spi_setfrequency
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*
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* Description:
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* Set the SPI frequency.
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*
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* Input Parameters:
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* dev - Device-specific state data
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* frequency - The SPI frequency requested
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*
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* Returned Value:
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* Returns the actual frequency selected
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*
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****************************************************************************/
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static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
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{
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FAR struct lpc17_spidev_s *priv = (FAR struct lpc17_spidev_s *)dev;
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uint32_t divisor;
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uint32_t actual;
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/* Check if the requested frequence is the same as the frequency selection */
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DEBUGASSERT(priv && frequency <= SPI_CLOCK / 2);
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#ifndef CONFIG_SPI_OWNBUS
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if (priv->frequency == frequency)
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{
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/* We are already at this frequency. Return the actual. */
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return priv->actual;
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}
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#endif
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/* frequency = SPI_CLOCK / divisor, or divisor = SPI_CLOCK / frequency */
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divisor = SPI_CLOCK / frequency;
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/* The SPI CCR register must contain an even number greater than or equal to 8. */
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if (divisor < 8)
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{
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divisor = 8;
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}
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else if (divisor > 254)
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{
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divisor = 254;
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}
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divisor = (divisor + 1) & ~1;
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/* Save the new divisor value */
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putreg32(divisor, LPC17_SPI_CCR);
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/* Calculate the new actual */
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actual = SPI_CLOCK / divisor;
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/* Save the frequency setting */
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#ifndef CONFIG_SPI_OWNBUS
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priv->frequency = frequency;
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priv->actual = actual;
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#endif
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spidbg("Frequency %d->%d\n", frequency, actual);
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return actual;
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}
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/****************************************************************************
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* Name: spi_setmode
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*
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* Description:
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* Set the SPI mode. Optional. See enum spi_mode_e for mode definitions
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*
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* Input Parameters:
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* dev - Device-specific state data
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* mode - The SPI mode requested
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*
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* Returned Value:
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* none
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*
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****************************************************************************/
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static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
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{
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FAR struct lpc17_spidev_s *priv = (FAR struct lpc17_spidev_s *)dev;
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uint32_t regval;
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/* Has the mode changed? */
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#ifndef CONFIG_SPI_OWNBUS
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if (mode != priv->mode)
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{
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#endif
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/* Yes... Set CR appropriately */
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regval = getreg32(LPC17_SPI_CR);
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regval &= ~(SPI_CR_CPOL|SPI_CR_CPHA);
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switch (mode)
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{
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case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
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break;
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case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
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regval |= SPI_CR_CPHA;
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break;
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case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
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regval |= SPI_CR_CPOL;
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break;
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case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
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regval |= (SPI_CR_CPOL|SPI_CR_CPHA);
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break;
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default:
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DEBUGASSERT(FALSE);
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return;
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}
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putreg32(regval, LPC17_SPI_CR);
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/* Save the mode so that subsequent re-configuratins will be faster */
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#ifndef CONFIG_SPI_OWNBUS
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priv->mode = mode;
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}
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#endif
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}
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/****************************************************************************
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* Name: spi_setbits
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*
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* Description:
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* Set the number if bits per word.
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*
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* Input Parameters:
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* dev - Device-specific state data
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* nbits - The number of bits requests
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*
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* Returned Value:
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* none
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*
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****************************************************************************/
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static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
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{
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FAR struct lpc17_spidev_s *priv = (FAR struct lpc17_spidev_s *)dev;
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uint32_t regval;
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/* Has the number of bits changed? */
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DEBUGASSERT(priv && nbits > 7 && nbits < 17);
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#ifndef CONFIG_SPI_OWNBUS
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if (nbits != priv->nbits)
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{
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#endif
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/* Yes... Set CR appropriately */
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regval = getreg32(LPC17_SPI_CR);
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regval &= ~SPI_CR_BITS_MASK;
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regval |= (nbits << SPI_CR_BITS_SHIFT) & SPI_CR_BITS_MASK;
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regval |= SPI_CR_BITENABLE;
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regval = getreg32(LPC17_SPI_CR);
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/* Save the selection so the subsequence re-configurations will be faster */
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#ifndef CONFIG_SPI_OWNBUS
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priv->nbits = nbits;
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}
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#endif
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}
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/****************************************************************************
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* Name: spi_send
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*
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* Description:
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|
* Exchange one word on SPI
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* dev - Device-specific state data
|
|
|
|
* wd - The word to send. the size of the data is determined by the
|
|
|
|
* number of bits selected for the SPI interface.
|
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* response
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd)
|
|
|
|
{
|
|
|
|
/* Write the data to transmitted to the SPI Data Register */
|
|
|
|
|
|
|
|
putreg32((uint32_t)wd, LPC17_SPI_DR);
|
|
|
|
|
|
|
|
/* Wait for the SPIF bit in the SPI Status Register to be set to 1. The
|
|
|
|
* SPIF bit will be set after the last sampling clock edge of the SPI
|
|
|
|
* data transfer.
|
|
|
|
*/
|
|
|
|
|
|
|
|
while ((getreg32(LPC17_SPI_SR) & SPI_SR_SPIF) == 0);
|
|
|
|
|
|
|
|
/* Read the SPI Status Register again to clear the status bit */
|
|
|
|
|
|
|
|
(void)getreg32(LPC17_SPI_SR);
|
|
|
|
return (uint16_t)getreg32(LPC17_SPI_DR);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*************************************************************************
|
|
|
|
* Name: spi_sndblock
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Send a block of data on SPI
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* dev - Device-specific state data
|
|
|
|
* buffer - A pointer to the buffer of data to be sent
|
|
|
|
* nwords - the length of data to send from the buffer in number of words.
|
|
|
|
* The wordsize is determined by the number of bits-per-word
|
|
|
|
* selected for the SPI interface. If nbits <= 8, the data is
|
|
|
|
* packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
|
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* None
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords)
|
|
|
|
{
|
|
|
|
FAR uint8_t *ptr = (FAR uint8_t*)buffer;
|
|
|
|
uint8_t data;
|
|
|
|
|
|
|
|
spidbg("nwords: %d\n", nwords);
|
|
|
|
while (nwords)
|
|
|
|
{
|
|
|
|
/* Write the data to transmitted to the SPI Data Register */
|
|
|
|
|
|
|
|
data = *ptr++;
|
|
|
|
putreg32((uint32_t)data, LPC17_SPI_DR);
|
|
|
|
|
|
|
|
/* Wait for the SPIF bit in the SPI Status Register to be set to 1. The
|
|
|
|
* SPIF bit will be set after the last sampling clock edge of the SPI
|
|
|
|
* data transfer.
|
|
|
|
*/
|
|
|
|
|
|
|
|
while ((getreg32(LPC17_SPI_SR) & SPI_SR_SPIF) == 0);
|
|
|
|
|
|
|
|
/* Read the SPI Status Register again to clear the status bit */
|
|
|
|
|
|
|
|
(void)getreg32(LPC17_SPI_SR);
|
|
|
|
nwords--;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: spi_recvblock
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Revice a block of data from SPI
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* dev - Device-specific state data
|
|
|
|
* buffer - A pointer to the buffer in which to recieve data
|
|
|
|
* nwords - the length of data that can be received in the buffer in number
|
|
|
|
* of words. The wordsize is determined by the number of bits-per-word
|
|
|
|
* selected for the SPI interface. If nbits <= 8, the data is
|
|
|
|
* packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
|
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* None
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords)
|
|
|
|
{
|
|
|
|
FAR uint8_t *ptr = (FAR uint8_t*)buffer;
|
|
|
|
|
|
|
|
spidbg("nwords: %d\n", nwords);
|
|
|
|
while (nwords)
|
|
|
|
{
|
2010-06-15 16:46:53 +02:00
|
|
|
/* Write some dummy data to the SPI Data Register in order to clock the
|
|
|
|
* read data.
|
|
|
|
*/
|
2010-06-15 03:12:44 +02:00
|
|
|
|
|
|
|
putreg32(0xff, LPC17_SPI_DR);
|
|
|
|
|
|
|
|
/* Wait for the SPIF bit in the SPI Status Register to be set to 1. The
|
|
|
|
* SPIF bit will be set after the last sampling clock edge of the SPI
|
|
|
|
* data transfer.
|
|
|
|
*/
|
|
|
|
|
|
|
|
while ((getreg32(LPC17_SPI_SR) & SPI_SR_SPIF) == 0);
|
|
|
|
|
|
|
|
/* Read the SPI Status Register again to clear the status bit */
|
|
|
|
|
|
|
|
(void)getreg32(LPC17_SPI_SR);
|
|
|
|
|
|
|
|
/* Read the received data from the SPI Data Register */
|
|
|
|
|
|
|
|
*ptr++ = (uint8_t)getreg32(LPC17_SPI_DR);
|
|
|
|
nwords--;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Public Functions
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: up_spiinitialize
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Initialize the selected SPI port
|
|
|
|
*
|
|
|
|
* Input Parameter:
|
|
|
|
* Port number (for hardware that has mutiple SPI interfaces)
|
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* Valid SPI device structure reference on succcess; a NULL on failure
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
FAR struct spi_dev_s *up_spiinitialize(int port)
|
|
|
|
{
|
|
|
|
FAR struct lpc17_spidev_s *priv = &g_spidev;
|
|
|
|
irqstate_t flags;
|
|
|
|
uint32_t regval;
|
|
|
|
|
|
|
|
/* Configure multiplexed pins as connected on the board. Chip select
|
|
|
|
* pins must be configured by board-specific logic. All SPI pins and
|
|
|
|
* one SPI1 pin (SCK) have multiple, alternative pin selection.
|
|
|
|
* Definitions in the board.h file must be provided to resolve the
|
|
|
|
* board-specific pin configuration like:
|
|
|
|
*
|
|
|
|
* #define GPIO_SPI_SCK GPIO_SPI_SCK_1
|
|
|
|
*/
|
|
|
|
|
|
|
|
flags = irqsave();
|
|
|
|
lpc17_configgpio(GPIO_SPI_SCK);
|
|
|
|
lpc17_configgpio(GPIO_SPI_MISO);
|
|
|
|
lpc17_configgpio(GPIO_SPI_MOSI);
|
|
|
|
|
|
|
|
/* Configure clocking */
|
|
|
|
|
|
|
|
regval = getreg32(LPC17_SYSCON_PCLKSEL0);
|
|
|
|
regval &= ~SYSCON_PCLKSEL0_SPI_MASK;
|
|
|
|
regval |= (SPI_PCLKSET_DIV << SYSCON_PCLKSEL0_SPI_SHIFT);
|
|
|
|
putreg32(regval, LPC17_SYSCON_PCLKSEL0);
|
|
|
|
|
|
|
|
/* Enable peripheral clocking to SPI and SPI1 */
|
|
|
|
|
|
|
|
regval = getreg32(LPC17_SYSCON_PCONP);
|
|
|
|
regval |= SYSCON_PCONP_PCSPI;
|
|
|
|
putreg32(regval, LPC17_SYSCON_PCONP);
|
|
|
|
irqrestore(flags);
|
|
|
|
|
|
|
|
/* Configure 8-bit SPI mode and master mode */
|
|
|
|
|
|
|
|
putreg32(SPI_CR_BITS_8BITS|SPI_CR_BITENABLE|SPI_CR_MSTR, LPC17_SPI_CR);
|
|
|
|
|
|
|
|
/* Set the initial SPI configuration */
|
|
|
|
|
|
|
|
#ifndef CONFIG_SPI_OWNBUS
|
|
|
|
priv->frequency = 0;
|
|
|
|
priv->nbits = 8;
|
|
|
|
priv->mode = SPIDEV_MODE0;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* Select a default frequency of approx. 400KHz */
|
|
|
|
|
|
|
|
spi_setfrequency((FAR struct spi_dev_s *)priv, 400000);
|
|
|
|
|
|
|
|
/* Initialize the SPI semaphore that enforces mutually exclusive access */
|
|
|
|
|
|
|
|
#ifndef CONFIG_SPI_OWNBUS
|
|
|
|
sem_init(&priv->exclsem, 0, 1);
|
|
|
|
#endif
|
|
|
|
return &priv->spidev;
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_LPC17_SPI */
|
|
|
|
|