nuttx/boards/arm/imxrt/imxrt1170-evk/scripts/memory.ld

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Base IMXRT1170 port Co-authored-by: Jari van Ewijk <jari.vanewijk@nxp.com> Co-authored-by: David Sidrane <david.sidrane@nscdg.com> Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com> imxrt:Kconfig fix formatting imxrt:usbphy move IMXRT_USBPHY{1|[2]}_BASE to memory map imxrt:lpspi Fix build breakage from adding 1170 imxrt:Finish 1170 iomux and clockconfig versioning imxrt:Remove duplicate imxrt_clock{off|all}_lpi2c4 imxrt:pmu remove duplicate dcd non 117x header imxrt:lpspi Fix unused var warnings imxrt:lpi2c Fix unused var warnings imxrt:lowputs Fix unused var warnings imxrt:imxrt117x_dmamux fix duplicate entries imxtr:serial Use IOMUX_PULL_{UP|DOWN} and map IOMUX V1 to them imxrt:MPU Support the 1170 imxrt:dmamux Alias IMXRT_DMAMUX0_BASE as IMXRT_DMAMUX_BASE imx1170:ccm Alias CCM_CCGR_DMA & CCM_CCGR_SNVS_LP for compatiblity Author: Peter van der Perk <peter.vanderperk@nxp.com> IMXRT7 Add LPUART 9/10/11/12 support Author: David Sidrane <david.sidrane@nscdg.com> imxrt:1170pinmux Add QTIMER pins imxrt:1170pinmux Add GPT pins imxrt:1170pinmux Add FLEXPWM pins imxrt1170:pinmap Add GPIO_ENET_1G pinning imxrt:enet Support ENET_1G imxrt:periphclks rt1170 does not have canX_serial clock imxrt:flexcan:Layer imxrt_ioctl imxrt117x:memorymap added CAN3 imxrt:ADC support ver1 and ver2 for imxrt117x imxrt:imxrt117x_ccm Align timer naming with other imxrt QTIMERn->TIMERn imxrt:imxrt117x_ccm align CCM names with rt106x imxrt:XBAR support larger number of selects needed on imxrt1170 Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com> FlexSPI AHB Region support, PIT rename for compatiblity imxrt:USB Analog add VBUS_VALID_3V FlexSPI expand prefetch registers for IMXRT117X imxrt:Support Initialization of FlexRam without Running from OCRAM imxrt: ocotp add UNIQUE_ID register definition imxrt: enet use ocotp unique_id imxrt: enet fixes for imxrt117x imxrt: ethernet pinmux sion enable imxrt:imxrt_periphclk_configure add memory sync Flush the pipeline to prevent bus faults, by insuring a peripheral is clocked before being accessed on return from this function. imxrt:Restructure gpioN to padmux mapping imxrt:Add imxrt1170 daisy imxrt: correct power modes for imxrt117x fixing hang on WFI imxrt: imxrt117x TCM MPU config imxrt: FlexRAM clocking DIV0 setup imxrt: 117x periphclocks wait for status bit imxrt: iomucx set pad settings correctly and allow reconfiguration imxrt: enet align buffers 64-byte for optimal performance Add DSC barriers for write-through cache support imxrt: imxrt1170 use FlexCAN FD/ECC features imxrt:iomuxc_ver2 (117x) SD_B1 and DISP_B1 use PULL feild not PUE/PUS imxrt:Fix 1170 SNVS addressing imxrt: enet set mii clock after ifdown so that phy keep working nxstyle fixes imxrt: preprocessor and include fixes Fix configs imxrt1170-evk clean defconfig
2023-01-25 15:40:00 +01:00
/****************************************************************************
* boards/arm/imxrt/imxrt1170-evk/scripts/memory.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* The i.MXRT1064-EVK has 8MiB of Hyper FLASH beginning at address,
* 0x0060:0000, Up to 512Kb of DTCM RAM beginning at 0x2000:0000, and 1MiB OCRAM
* beginning at 0x2020:0000. Neither DTCM or SDRAM are used in this
* configuration.
*
* The user and kernel space partitions will be spanned with a single
* region of size 2**n bytes. As a consequence, as the partitions increase
* in size, the alignment requirement also increases. The sizes below give
* the largest possible user address spaces (but leave far too much for the
* OS).
*
* The solution to this wasted memory is to (1) use more than one region to
* span the user spaces, or (2) poke holes in a larger region (via sub-
* regions) to trim it to fit better.
*
* A detailed memory map for the 512KB SRAM region is as follows:
*
* 0x2020 0000: Kernel .data region. Typical size: 0.1KB
* ------ ---- Kernel .bss region. Typical size: 1.8KB
* 0x2020 0800: Kernel IDLE thread stack (approximate). Size is
* determined by CONFIG_IDLETHREAD_STACKSIZE and
* adjustments for alignment. Typical is 1KB.
* ------ ---- Padded to 4KB
* 0x2040 0000: User .data region. Size is variable.
* ------- ---- User .bss region Size is variable.
* 0x2042 0000: Beginning of kernel heap. Size determined by
* CONFIG_MM_KERNEL_HEAPSIZE.
* ------ ---- Beginning of user heap. Can vary with other settings.
* 0x2080 0000: End+1 of mappable OCRAM
*/
/* Specify the memory areas */
MEMORY
{
/* 16MiB of QSPI */
kflash (rx) : ORIGIN = 0x30000000, LENGTH = 1M
uflash (rx) : ORIGIN = 0x30200000, LENGTH = 1M
flash (rx) : ORIGIN = 0x30400000, LENGTH = 14M
/* 1MiB of OCRAM */
dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
kocram (rwx) : ORIGIN = 0x20240000, LENGTH = 512K
uocram (rwx) : ORIGIN = 0x20280000, LENGTH = 512K
}
_ram_size = LENGTH(kocram) + LENGTH(uocram);