2020-02-08 00:10:23 +01:00
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/****************************************************************************
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* libs/libc/machine/risc-v/rv64/arch_elf.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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2020-11-22 09:25:46 +01:00
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#include <inttypes.h>
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2020-02-08 00:10:23 +01:00
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#include <stdlib.h>
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#include <errno.h>
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#include <debug.h>
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#include <assert.h>
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#include <arch/elf.h>
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#include <nuttx/elf.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define OPCODE_SW 0x23
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/****************************************************************************
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* Private Data Types
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****************************************************************************/
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#ifdef CONFIG_DEBUG_BINFMT_INFO
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struct rname_code_s
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{
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const char *name;
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int type;
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};
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#endif
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/****************************************************************************
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* Private Data
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****************************************************************************/
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#ifdef CONFIG_DEBUG_BINFMT_INFO
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static struct rname_code_s _rname_table[] =
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{
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{"RELAX", R_RISCV_RELAX},
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{"RISCV_64", R_RISCV_64},
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{"PCREL_LO12_I", R_RISCV_PCREL_LO12_I},
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{"PCREL_LO12_S", R_RISCV_PCREL_LO12_S},
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{"PCREL_HI20", R_RISCV_PCREL_HI20},
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{"CALL", R_RISCV_CALL},
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{"BRANCH", R_RISCV_BRANCH},
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{"RVC_JUMP", R_RISCV_RVC_JUMP},
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{"RVC_BRANCH", R_RISCV_RVC_BRANCH},
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};
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#endif
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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#ifdef CONFIG_DEBUG_BINFMT_INFO
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const char *_get_rname(int type)
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{
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int i = 0;
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for (i = 0; i < sizeof(_rname_table) / sizeof(struct rname_code_s); i++)
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{
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if (_rname_table[i].type == type)
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{
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return _rname_table[i].name;
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}
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}
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/* Not found in the table */
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return "?????";
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}
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#endif
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/****************************************************************************
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* Name: _get_val, set_val, _add_val
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*
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* Description:
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* These functions are used when relocating an instruction because we can
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* not assume the instruction is word-aligned.
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*
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****************************************************************************/
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static uint32_t _get_val(uint16_t *addr)
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{
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uint32_t ret;
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ret = *addr | (*(addr + 1)) << 16;
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return ret;
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}
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static void _set_val(uint16_t *addr, uint32_t val)
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{
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*addr = (val & 0xffff);
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*(addr + 1) = (val >> 16);
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/* NOTE: Ensure relocation before execution */
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asm volatile ("fence.i");
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}
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static void _add_val(uint16_t *addr, uint32_t val)
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{
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uint32_t cur = _get_val(addr);
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_set_val(addr, cur + val);
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}
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/****************************************************************************
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* Name: _calc_imm
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*
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* Description:
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* Given offset and obtain imm_hi (20bit) and imm_lo (12bit)
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*
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* Input Parameters:
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* offset - signed 64bit
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* imm_hi - signed 20bit
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* imm_lo - signed 12bit
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*
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* Returned Value:
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* none
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*
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****************************************************************************/
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static void _calc_imm(long offset, long *imm_hi, long *imm_lo)
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{
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long lo;
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long hi = offset / 4096;
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long r = offset % 4096;
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if (2047 < r)
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{
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hi++;
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}
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2020-06-25 07:54:27 +02:00
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else if (r < -2048)
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2020-02-08 00:10:23 +01:00
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{
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hi--;
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}
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lo = offset - (hi * 4096);
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binfo("offset=%ld: hi=%ld lo=%ld \n",
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offset, hi, lo);
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ASSERT(-2048 <= lo && lo <= 2047);
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*imm_lo = lo;
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*imm_hi = hi;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_checkarch
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*
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* Description:
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* Given the ELF header in 'hdr', verify that the ELF file is appropriate
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* for the current, configured architecture. Every architecture that uses
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* the ELF loader must provide this function.
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*
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* Input Parameters:
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* hdr - The ELF header read from the ELF file.
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*
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* Returned Value:
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* True if the architecture supports this ELF file.
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*
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****************************************************************************/
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bool up_checkarch(FAR const Elf64_Ehdr *ehdr)
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{
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/* Make sure it's an RISCV executable */
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if (ehdr->e_machine != EM_RISCV)
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{
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berr("ERROR: Not for RISCV: e_machine=%04x\n", ehdr->e_machine);
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return false;
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}
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/* Make sure that 64-bit objects are supported */
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if (ehdr->e_ident[EI_CLASS] != ELFCLASS64)
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{
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berr("ERROR: Need 64-bit objects: e_ident[EI_CLASS]=%02x\n",
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ehdr->e_ident[EI_CLASS]);
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return false;
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}
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/* Verify endian-ness */
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#ifdef CONFIG_ENDIAN_BIG
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if (ehdr->e_ident[EI_DATA] != ELFDATA2MSB)
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#else
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if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB)
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#endif
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{
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berr("ERROR: Wrong endian-ness: e_ident[EI_DATA]=%02x\n",
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ehdr->e_ident[EI_DATA]);
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return false;
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}
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/* Make sure the entry point address is properly aligned */
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if ((ehdr->e_entry & 1) != 0)
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{
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2020-11-22 09:25:46 +01:00
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berr("ERROR: Entry point is not properly aligned: %08" PRIx64 "\n",
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2020-02-08 00:10:23 +01:00
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ehdr->e_entry);
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}
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/* TODO: Check ABI here. */
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return true;
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}
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/****************************************************************************
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* Name: up_relocate and up_relocateadd
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*
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* Description:
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* Perform on architecture-specific ELF relocation. Every architecture
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* that uses the ELF loader must provide this function.
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*
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* Input Parameters:
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* rel - The relocation type
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* sym - The ELF symbol structure containing the fully resolved value.
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* There are a few relocation types for a few architectures that do
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* not require symbol information. For those, this value will be
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* NULL. Implementations of these functions must be able to handle
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* that case.
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* addr - The address that requires the relocation.
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*
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* Returned Value:
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* Zero (OK) if the relocation was successful. Otherwise, a negated errno
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* value indicating the cause of the relocation failure.
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*
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****************************************************************************/
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int up_relocate(FAR const Elf64_Rel *rel, FAR const Elf64_Sym *sym,
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uintptr_t addr)
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{
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berr("Not implemented\n");
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return -ENOSYS;
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}
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int up_relocateadd(FAR const Elf64_Rela *rel, FAR const Elf64_Sym *sym,
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uintptr_t addr)
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{
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long offset;
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unsigned int relotype;
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/* All relocations depend upon having valid symbol information */
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relotype = ELF64_R_TYPE(rel->r_info);
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if (relotype == R_RISCV_RELAX)
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{
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/* NOTE: RELAX has no symbol, so just return */
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2020-11-22 09:25:46 +01:00
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binfo("%s at %08" PRIxPTR " [%08" PRIx32 "] \n",
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2020-02-08 00:10:23 +01:00
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_get_rname(relotype),
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2020-11-22 09:25:46 +01:00
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addr, _get_val((uint16_t *)addr));
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2020-02-08 00:10:23 +01:00
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return OK;
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}
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if (sym == NULL && relotype != R_RISCV_NONE)
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{
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return -EINVAL;
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}
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/* Do relocation based on relocation type */
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switch (relotype)
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{
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case R_RISCV_64:
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{
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2020-11-22 09:25:46 +01:00
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binfo("%s at %08" PRIxPTR " [%08" PRIx32 "] "
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"to sym=%p st_value=%08" PRIx64 "\n",
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2020-02-08 00:10:23 +01:00
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_get_rname(relotype),
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2020-11-22 09:25:46 +01:00
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addr, _get_val((uint16_t *)addr),
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sym, sym->st_value);
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2020-02-08 00:10:23 +01:00
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_set_val((uint16_t *)addr,
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(uint32_t)(sym->st_value + rel->r_addend));
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}
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break;
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case R_RISCV_PCREL_LO12_I:
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case R_RISCV_PCREL_LO12_S:
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{
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2020-11-22 09:25:46 +01:00
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binfo("%s at %08" PRIxPTR " [%08" PRIx32 "] "
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"to sym=%p st_value=%08" PRIx64 "\n",
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2020-02-08 00:10:23 +01:00
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_get_rname(relotype),
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2020-11-22 09:25:46 +01:00
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addr, _get_val((uint16_t *)addr),
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sym, sym->st_value);
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2020-02-08 00:10:23 +01:00
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/* NOTE: imm value for mv has been adjusted in previous HI20 */
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}
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break;
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case R_RISCV_PCREL_HI20:
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case R_RISCV_CALL:
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{
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2020-11-22 09:25:46 +01:00
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binfo("%s at %08" PRIxPTR " [%08" PRIx32 "] "
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"to sym=%p st_value=%08" PRIx64 "\n",
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2020-02-08 00:10:23 +01:00
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_get_rname(relotype),
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2020-11-22 09:25:46 +01:00
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addr, _get_val((uint16_t *)addr),
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sym, sym->st_value);
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2020-02-08 00:10:23 +01:00
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offset = (long)sym->st_value - (long)addr;
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long imm_hi;
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long imm_lo;
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_calc_imm(offset, &imm_hi, &imm_lo);
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/* Adjust auipc (add upper immediate to pc) : 20bit */
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_add_val((uint16_t *)addr, (imm_hi << 12));
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if ((_get_val((uint16_t *)(addr + 4)) & 0x7f) == OPCODE_SW)
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{
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/* Adjust imm for SW : S-type */
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uint32_t val =
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(((int32_t)imm_lo >> 5) << 25) +
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(((int32_t)imm_lo & 0x1f) << 7);
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2020-11-22 09:25:46 +01:00
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binfo("imm_lo=%ld (%lx), val=%x \n", imm_lo, imm_lo, val);
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2020-02-08 00:10:23 +01:00
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_add_val((uint16_t *)(addr + 4), val);
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}
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else
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{
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/* Adjust imm for MV(ADDI)/JALR : I-type */
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_add_val((uint16_t *)(addr + 4), ((int32_t)imm_lo << 20));
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}
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}
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break;
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case R_RISCV_BRANCH:
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{
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binfo("%s at %08lx [%08x] to sym=%p st_value=%08lx\n",
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_get_rname(relotype),
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(long)addr, _get_val((uint16_t *)addr),
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sym, (long)sym->st_value);
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/* P.23 Conditinal Branches : B type (imm=12bit) */
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offset = (long)sym->st_value - (long)addr;
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uint32_t val = _get_val((uint16_t *)addr) & 0xfe000f80;
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/* NOTE: we assume that a compiler adds an immediate value */
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ASSERT(offset && val);
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2020-11-22 09:25:46 +01:00
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binfo("offset for Bx=%ld (0x%lx) (val=0x%08x) already set! \n",
|
2020-02-08 00:10:23 +01:00
|
|
|
offset, offset, val);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case R_RISCV_RVC_JUMP:
|
|
|
|
{
|
|
|
|
binfo("%s at %08lx [%04x] to sym=%p st_value=%08lx\n",
|
|
|
|
_get_rname(relotype),
|
|
|
|
(long)addr, _get_val((uint16_t *)addr),
|
|
|
|
sym, (long)sym->st_value);
|
|
|
|
|
|
|
|
/* P.111 Table 16.6 : Instruction listings for RVC */
|
|
|
|
|
|
|
|
offset = ((long)sym->st_value - (long)addr);
|
|
|
|
ASSERT(-2048 <= offset && offset <= 2047);
|
|
|
|
|
|
|
|
uint16_t val = (*(uint16_t *)addr) & 0x1ffc;
|
|
|
|
|
|
|
|
/* NOTE: we assume that a compiler adds an immediate value */
|
|
|
|
|
|
|
|
ASSERT(offset && val);
|
|
|
|
|
2020-11-22 09:25:46 +01:00
|
|
|
binfo("offset for C.J=%ld (0x%lx) (val=0x%04x) already set! \n",
|
2020-02-08 00:10:23 +01:00
|
|
|
offset, offset, val);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case R_RISCV_RVC_BRANCH:
|
|
|
|
{
|
|
|
|
binfo("%s at %08lx [%04x] to sym=%p st_value=%08lx\n",
|
|
|
|
_get_rname(relotype),
|
|
|
|
(long)addr, _get_val((uint16_t *)addr),
|
|
|
|
sym, (long)sym->st_value);
|
|
|
|
|
|
|
|
/* P.111 Table 16.6 : Instruction listings for RVC */
|
|
|
|
|
|
|
|
offset = ((long)sym->st_value - (long)addr);
|
|
|
|
ASSERT(-256 <= offset && offset <= 255);
|
|
|
|
|
|
|
|
uint16_t val = (*(uint16_t *)addr) & 0x1c7c;
|
|
|
|
|
|
|
|
/* NOTE: we assume that a compiler adds an immediate value */
|
|
|
|
|
|
|
|
ASSERT(offset && val);
|
|
|
|
|
2020-11-22 09:25:46 +01:00
|
|
|
binfo("offset for C.Bx=%ld (0x%lx) (val=0x%04x) already set!\n",
|
2020-02-08 00:10:23 +01:00
|
|
|
offset, offset, val);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
2020-11-22 09:25:46 +01:00
|
|
|
berr("ERROR: Unsupported relocation: %" PRId64 "\n",
|
2020-02-08 00:10:23 +01:00
|
|
|
ELF64_R_TYPE(rel->r_info));
|
|
|
|
ASSERT(false);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return OK;
|
|
|
|
}
|