2009-05-12 20:53:10 +02:00
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/****************************************************************************
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2013-01-09 15:48:55 +01:00
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* arch/arm/src/lm/lm_serial.c
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2009-05-12 20:53:10 +02:00
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*
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2012-02-11 04:50:52 +01:00
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* Copyright (C) 2009-2010, 2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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2009-05-12 20:53:10 +02:00
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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2009-05-17 19:18:19 +02:00
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2009-12-16 21:05:51 +01:00
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#include <sys/types.h>
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#include <stdint.h>
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#include <stdbool.h>
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2009-05-12 20:53:10 +02:00
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#include <unistd.h>
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#include <semaphore.h>
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#include <string.h>
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#include <errno.h>
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#include <debug.h>
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2009-05-17 19:18:19 +02:00
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2009-05-12 20:53:10 +02:00
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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2012-03-21 20:47:23 +01:00
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#include <nuttx/serial/serial.h>
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2010-05-09 18:36:07 +02:00
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2009-05-12 20:53:10 +02:00
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#include <arch/serial.h>
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2010-05-09 18:36:07 +02:00
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#include <arch/board/board.h>
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2009-05-12 20:53:10 +02:00
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#include "chip.h"
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#include "up_arch.h"
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#include "up_internal.h"
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2009-05-19 22:50:47 +02:00
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#include "os_internal.h"
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2009-05-12 20:53:10 +02:00
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/****************************************************************************
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2009-12-16 21:05:51 +01:00
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* Pre-processor Definitions
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2009-05-12 20:53:10 +02:00
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****************************************************************************/
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/* Some sanity checks *******************************************************/
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2010-05-07 04:32:56 +02:00
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#if LM3S_NUARTS < 2
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2013-01-09 15:48:55 +01:00
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# undef CONFIG_LM_UART1
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2010-05-07 04:32:56 +02:00
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# undef CONFIG_UART1_SERIAL_CONSOLE
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#endif
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#if LM3S_NUARTS < 3
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2013-01-09 15:48:55 +01:00
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# undef CONFIG_LM_UART2
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2010-05-07 04:32:56 +02:00
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# undef CONFIG_UART2_SERIAL_CONSOLE
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#endif
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2009-05-12 20:53:10 +02:00
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/* Is there a UART enabled? */
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2013-01-09 15:48:55 +01:00
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#if !defined(CONFIG_LM_UART0) && !defined(CONFIG_LM_UART1) && !defined(CONFIG_LM_UART2)
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2009-05-12 20:53:10 +02:00
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# error "No UARTs enabled"
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#endif
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/* Is there a serial console? */
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2013-01-09 15:48:55 +01:00
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#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LM_UART0)
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2009-05-12 20:53:10 +02:00
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# undef CONFIG_UART1_SERIAL_CONSOLE
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2010-05-07 04:32:56 +02:00
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# undef CONFIG_UART2_SERIAL_CONSOLE
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2009-05-12 20:53:10 +02:00
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# define HAVE_CONSOLE 1
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2013-01-09 15:48:55 +01:00
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#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_LM_UART1)
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2009-05-12 20:53:10 +02:00
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# undef CONFIG_UART0_SERIAL_CONSOLE
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2010-05-07 04:32:56 +02:00
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# undef CONFIG_UART2_SERIAL_CONSOLE
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# define HAVE_CONSOLE 1
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2013-01-09 15:48:55 +01:00
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#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_LM_UART2)
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2010-05-07 04:32:56 +02:00
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# undef CONFIG_UART0_SERIAL_CONSOLE
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# undef CONFIG_UART1_SERIAL_CONSOLE
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2009-05-12 20:53:10 +02:00
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# define HAVE_CONSOLE 1
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#else
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# warning "No valid CONFIG_UARTn_SERIAL_CONSOLE Setting"
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# undef CONFIG_UART0_SERIAL_CONSOLE
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# undef CONFIG_UART1_SERIAL_CONSOLE
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2010-05-07 04:32:56 +02:00
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# undef CONFIG_UART2_SERIAL_CONSOLE
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2009-05-12 20:53:10 +02:00
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# undef HAVE_CONSOLE
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#endif
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2009-05-17 19:18:19 +02:00
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/* If we are not using the serial driver for the console, then we
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* still must provide some minimal implementation of up_putc.
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*/
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2012-02-11 04:50:52 +01:00
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#ifdef USE_SERIALDRIVER
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2009-05-17 19:18:19 +02:00
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2009-05-12 20:53:10 +02:00
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/* Which UART with be tty0/console and which tty1? */
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#if defined(CONFIG_UART0_SERIAL_CONSOLE)
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# define CONSOLE_DEV g_uart0port /* UART0 is console */
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# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */
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2013-01-09 15:48:55 +01:00
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# ifdef CONFIG_LM_UART1
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2009-05-12 20:53:10 +02:00
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# define TTYS1_DEV g_uart1port /* UART1 is ttyS1 */
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2013-01-09 15:48:55 +01:00
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# ifdef CONFIG_LM_UART2
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2010-05-07 04:32:56 +02:00
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# define TTYS2_DEV g_uart2port /* UART2 is ttyS2 */
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# else
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# undef TTYS2_DEV /* No ttyS2 */
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# endif
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2009-05-19 22:50:47 +02:00
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# else
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2010-05-07 04:32:56 +02:00
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# undef TTYS2_DEV /* No ttyS2 */
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2013-01-09 15:48:55 +01:00
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# ifdef CONFIG_LM_UART2
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2010-05-07 04:32:56 +02:00
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# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */
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# else
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# undef TTYS1_DEV /* No ttyS1 */
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# endif
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2009-05-12 20:53:10 +02:00
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# endif
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#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
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# define CONSOLE_DEV g_uart1port /* UART1 is console */
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# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */
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2013-01-09 15:48:55 +01:00
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# ifdef CONFIG_LM_UART0
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2009-05-12 20:53:10 +02:00
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# define TTYS1_DEV g_uart0port /* UART0 is ttyS1 */
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2013-01-09 15:48:55 +01:00
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# ifdef CONFIG_LM_UART2
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2010-05-07 04:32:56 +02:00
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# define TTYS2_DEV g_uart2port /* UART2 is ttyS2 */
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# else
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# undef TTYS2_DEV /* No ttyS2 */
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# endif
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2009-05-19 22:50:47 +02:00
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# else
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2010-05-07 04:32:56 +02:00
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# undef TTYS2_DEV /* No ttyS2 */
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2013-01-09 15:48:55 +01:00
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# ifdef CONFIG_LM_UART2
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2010-05-07 04:32:56 +02:00
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# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */
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# else
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# undef TTYS1_DEV /* No ttyS1 */
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# endif
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# endif
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#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
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# define CONSOLE_DEV g_uart2port /* UART2 is console */
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# define TTYS0_DEV g_uart2port /* UART2 is ttyS0 */
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2013-01-09 15:48:55 +01:00
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# ifdef CONFIG_LM_UART0
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2010-05-07 04:32:56 +02:00
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# define TTYS1_DEV g_uart0port /* UART0 is ttyS1 */
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2013-01-09 15:48:55 +01:00
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# ifdef CONFIG_LM_UART2
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2010-05-07 04:32:56 +02:00
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# define TTYS2_DEV g_uart2port /* UART2 is ttyS2 */
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# else
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# undef TTYS2_DEV /* No ttyS2 */
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# endif
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# else
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# undef TTYS2_DEV /* No ttyS2 */
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2013-01-09 15:48:55 +01:00
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# ifdef CONFIG_LM_UART2
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2010-05-07 04:32:56 +02:00
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# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */
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# else
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# undef TTYS1_DEV /* No ttyS1 */
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# endif
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2009-05-12 20:53:10 +02:00
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# endif
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2013-01-09 15:48:55 +01:00
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#elifdefined(CONFIG_LM_UART0)
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2009-05-12 20:53:10 +02:00
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# undef CONSOLE_DEV /* No console device */
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# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */
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2013-01-09 15:48:55 +01:00
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# ifdef CONFIG_LM_UART1
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2009-05-12 20:53:10 +02:00
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# define TTYS1_DEV g_uart1port /* UART1 is ttyS1 */
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2013-01-09 15:48:55 +01:00
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# ifdef CONFIG_LM_UART2
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2010-05-07 04:32:56 +02:00
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# define TTYS2_DEV g_uart2port /* UART2 is ttyS2 */
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# else
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# undef TTYS2_DEV /* No ttyS2 */
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# endif
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2009-05-19 22:50:47 +02:00
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# else
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2010-05-07 04:32:56 +02:00
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# undef TTYS2_DEV /* No ttyS2 */
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2013-01-09 15:48:55 +01:00
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# ifdef CONFIG_LM_UART2
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2010-05-07 04:32:56 +02:00
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# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */
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# else
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# undef TTYS1_DEV /* No ttyS1 */
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# endif
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2009-05-12 20:53:10 +02:00
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# endif
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2013-01-09 15:48:55 +01:00
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#elifdefined(CONFIG_LM_UART1)
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2009-05-12 20:53:10 +02:00
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# undef CONSOLE_DEV /* No console device */
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# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */
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2010-05-07 04:32:56 +02:00
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# undef TTYS2_DEV /* No ttyS2 */
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2013-01-09 15:48:55 +01:00
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# ifdef CONFIG_LM_UART2
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2010-05-07 04:32:56 +02:00
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# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */
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# else
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# undef TTYS1_DEV /* No ttyS1 */
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# endif
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2013-01-09 15:48:55 +01:00
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#elifdefined(CONFIG_LM_UART2)
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2010-05-07 04:32:56 +02:00
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# undef CONSOLE_DEV /* No console device */
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# define TTYS0_DEV g_uart2port /* UART2 is ttyS0 */
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2009-05-12 20:53:10 +02:00
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# undef TTYS1_DEV /* No ttyS1 */
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2010-05-07 04:32:56 +02:00
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# undef TTYS2_DEV /* No ttyS2 */
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2009-05-12 20:53:10 +02:00
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#else
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# error "No valid TTY devices"
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# undef CONSOLE_DEV /* No console device */
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# undef TTYS0_DEV /* No ttyS0 */
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# undef TTYS1_DEV /* No ttyS1 */
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2010-05-07 04:32:56 +02:00
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# undef TTYS2_DEV /* No ttyS2 */
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2009-05-12 20:53:10 +02:00
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#endif
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/****************************************************************************
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* Private Types
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****************************************************************************/
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struct up_dev_s
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{
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2009-12-16 21:05:51 +01:00
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uint32_t uartbase; /* Base address of UART registers */
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uint32_t baud; /* Configured baud */
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uint32_t im; /* Saved IM value */
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uint8_t irq; /* IRQ associated with this UART */
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uint8_t parity; /* 0=none, 1=odd, 2=even */
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uint8_t bits; /* Number of bits (7 or 8) */
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bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */
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2009-05-12 20:53:10 +02:00
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};
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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2009-12-16 21:05:51 +01:00
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static int up_setup(struct uart_dev_s *dev);
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static void up_shutdown(struct uart_dev_s *dev);
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static int up_attach(struct uart_dev_s *dev);
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static void up_detach(struct uart_dev_s *dev);
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static int up_interrupt(int irq, void *context);
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static int up_ioctl(struct file *filep, int cmd, unsigned long arg);
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static int up_receive(struct uart_dev_s *dev, uint32_t *status);
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static void up_rxint(struct uart_dev_s *dev, bool enable);
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static bool up_rxavailable(struct uart_dev_s *dev);
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static void up_send(struct uart_dev_s *dev, int ch);
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static void up_txint(struct uart_dev_s *dev, bool enable);
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static bool up_txready(struct uart_dev_s *dev);
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static bool up_txempty(struct uart_dev_s *dev);
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2009-05-12 20:53:10 +02:00
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/****************************************************************************
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* Private Variables
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****************************************************************************/
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struct uart_ops_s g_uart_ops =
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{
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.setup = up_setup,
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.shutdown = up_shutdown,
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.attach = up_attach,
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.detach = up_detach,
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.ioctl = up_ioctl,
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.receive = up_receive,
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.rxint = up_rxint,
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.rxavailable = up_rxavailable,
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.send = up_send,
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.txint = up_txint,
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.txready = up_txready,
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.txempty = up_txempty,
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};
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/* I/O buffers */
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2013-01-09 15:48:55 +01:00
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#ifdef CONFIG_LM_UART0
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2009-05-12 20:53:10 +02:00
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static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE];
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static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE];
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#endif
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2013-01-09 15:48:55 +01:00
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#ifdef CONFIG_LM_UART1
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2009-05-12 20:53:10 +02:00
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static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE];
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static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE];
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#endif
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2013-01-09 15:48:55 +01:00
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#ifdef CONFIG_LM_UART2
|
2010-05-07 04:32:56 +02:00
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static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE];
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static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE];
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#endif
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2009-05-12 20:53:10 +02:00
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2010-05-07 04:32:56 +02:00
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/* This describes the state of the LM3S uart0 port. */
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2009-05-12 20:53:10 +02:00
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2013-01-09 15:48:55 +01:00
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|
#ifdef CONFIG_LM_UART0
|
2009-05-12 20:53:10 +02:00
|
|
|
static struct up_dev_s g_uart0priv =
|
|
|
|
{
|
|
|
|
.uartbase = LM3S_UART0_BASE,
|
|
|
|
.baud = CONFIG_UART0_BAUD,
|
|
|
|
.irq = LM3S_IRQ_UART0,
|
|
|
|
.parity = CONFIG_UART0_PARITY,
|
|
|
|
.bits = CONFIG_UART0_BITS,
|
|
|
|
.stopbits2 = CONFIG_UART0_2STOP,
|
|
|
|
};
|
|
|
|
|
|
|
|
static uart_dev_t g_uart0port =
|
|
|
|
{
|
|
|
|
.recv =
|
|
|
|
{
|
|
|
|
.size = CONFIG_UART0_RXBUFSIZE,
|
|
|
|
.buffer = g_uart0rxbuffer,
|
|
|
|
},
|
|
|
|
.xmit =
|
|
|
|
{
|
|
|
|
.size = CONFIG_UART0_TXBUFSIZE,
|
|
|
|
.buffer = g_uart0txbuffer,
|
|
|
|
},
|
|
|
|
.ops = &g_uart_ops,
|
|
|
|
.priv = &g_uart0priv,
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
2010-05-07 04:32:56 +02:00
|
|
|
/* This describes the state of the LM3S uart1 port. */
|
2009-05-12 20:53:10 +02:00
|
|
|
|
2013-01-09 15:48:55 +01:00
|
|
|
#ifdef CONFIG_LM_UART1
|
2009-05-12 20:53:10 +02:00
|
|
|
static struct up_dev_s g_uart1priv =
|
|
|
|
{
|
|
|
|
.uartbase = LM3S_UART1_BASE,
|
|
|
|
.baud = CONFIG_UART1_BAUD,
|
|
|
|
.irq = LM3S_IRQ_UART1,
|
|
|
|
.parity = CONFIG_UART1_PARITY,
|
|
|
|
.bits = CONFIG_UART1_BITS,
|
|
|
|
.stopbits2 = CONFIG_UART1_2STOP,
|
|
|
|
};
|
|
|
|
|
|
|
|
static uart_dev_t g_uart1port =
|
|
|
|
{
|
|
|
|
.recv =
|
|
|
|
{
|
|
|
|
.size = CONFIG_UART1_RXBUFSIZE,
|
|
|
|
.buffer = g_uart1rxbuffer,
|
|
|
|
},
|
|
|
|
.xmit =
|
|
|
|
{
|
|
|
|
.size = CONFIG_UART1_TXBUFSIZE,
|
|
|
|
.buffer = g_uart1txbuffer,
|
|
|
|
},
|
|
|
|
.ops = &g_uart_ops,
|
|
|
|
.priv = &g_uart1priv,
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
2010-05-07 04:32:56 +02:00
|
|
|
/* This describes the state of the LM3S uart1 port. */
|
|
|
|
|
2013-01-09 15:48:55 +01:00
|
|
|
#ifdef CONFIG_LM_UART2
|
2010-05-07 04:32:56 +02:00
|
|
|
static struct up_dev_s g_uart2priv =
|
|
|
|
{
|
|
|
|
.uartbase = LM3S_UART2_BASE,
|
|
|
|
.baud = CONFIG_UART2_BAUD,
|
|
|
|
.irq = LM3S_IRQ_UART2,
|
|
|
|
.parity = CONFIG_UART2_PARITY,
|
|
|
|
.bits = CONFIG_UART2_BITS,
|
|
|
|
.stopbits2 = CONFIG_UART2_2STOP,
|
|
|
|
};
|
|
|
|
|
|
|
|
static uart_dev_t g_uart2port =
|
|
|
|
{
|
|
|
|
.recv =
|
|
|
|
{
|
|
|
|
.size = CONFIG_UART2_RXBUFSIZE,
|
|
|
|
.buffer = g_uart2rxbuffer,
|
|
|
|
},
|
|
|
|
.xmit =
|
|
|
|
{
|
|
|
|
.size = CONFIG_UART2_TXBUFSIZE,
|
|
|
|
.buffer = g_uart2txbuffer,
|
|
|
|
},
|
|
|
|
.ops = &g_uart_ops,
|
|
|
|
.priv = &g_uart2priv,
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
2009-05-12 20:53:10 +02:00
|
|
|
/****************************************************************************
|
|
|
|
* Private Functions
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: up_serialin
|
|
|
|
****************************************************************************/
|
|
|
|
|
2009-12-16 21:05:51 +01:00
|
|
|
static inline uint32_t up_serialin(struct up_dev_s *priv, int offset)
|
2009-05-12 20:53:10 +02:00
|
|
|
{
|
|
|
|
return getreg32(priv->uartbase + offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: up_serialout
|
|
|
|
****************************************************************************/
|
|
|
|
|
2009-12-16 21:05:51 +01:00
|
|
|
static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value)
|
2009-05-12 20:53:10 +02:00
|
|
|
{
|
|
|
|
putreg32(value, priv->uartbase + offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: up_disableuartint
|
|
|
|
****************************************************************************/
|
|
|
|
|
2009-12-16 21:05:51 +01:00
|
|
|
static inline void up_disableuartint(struct up_dev_s *priv, uint32_t *im)
|
2009-05-12 20:53:10 +02:00
|
|
|
{
|
|
|
|
/* Return the current interrupt mask value */
|
|
|
|
|
|
|
|
if (im)
|
|
|
|
{
|
|
|
|
*im = priv->im;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Disable all interrupts */
|
|
|
|
|
|
|
|
priv->im = 0;
|
|
|
|
up_serialout(priv, LM3S_UART_IM_OFFSET, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: up_restoreuartint
|
|
|
|
****************************************************************************/
|
|
|
|
|
2009-12-16 21:05:51 +01:00
|
|
|
static inline void up_restoreuartint(struct up_dev_s *priv, uint32_t im)
|
2009-05-12 20:53:10 +02:00
|
|
|
{
|
|
|
|
priv->im = im;
|
|
|
|
up_serialout(priv, LM3S_UART_IM_OFFSET, im);
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: up_waittxnotfull
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
#ifdef HAVE_CONSOLE
|
|
|
|
static inline void up_waittxnotfull(struct up_dev_s *priv)
|
|
|
|
{
|
|
|
|
int tmp;
|
|
|
|
|
|
|
|
/* Limit how long we will wait for the TX available condition */
|
|
|
|
|
|
|
|
for (tmp = 1000 ; tmp > 0 ; tmp--)
|
|
|
|
{
|
|
|
|
/* Check Tx FIFO is full */
|
|
|
|
|
|
|
|
if ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFF) == 0)
|
|
|
|
{
|
|
|
|
/* The Tx FIFO is not full... return */
|
|
|
|
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* If we get here, then the wait has timed out and the Tx FIFO remains
|
|
|
|
* full.
|
|
|
|
*/
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: up_setup
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Configure the UART baud, bits, parity, fifos, etc. This
|
|
|
|
* method is called the first time that the serial port is
|
|
|
|
* opened.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
static int up_setup(struct uart_dev_s *dev)
|
|
|
|
{
|
|
|
|
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
|
2009-12-16 21:05:51 +01:00
|
|
|
uint32_t lcrh;
|
|
|
|
uint32_t ctl;
|
2009-05-12 20:53:10 +02:00
|
|
|
#ifndef CONFIG_SUPPRESS_UART_CONFIG
|
2009-12-16 21:05:51 +01:00
|
|
|
uint32_t den;
|
|
|
|
uint32_t brdi;
|
|
|
|
uint32_t remainder;
|
|
|
|
uint32_t divfrac;
|
2009-05-12 20:53:10 +02:00
|
|
|
|
|
|
|
/* Note: The logic here depends on the fact that that the UART module
|
|
|
|
* was enabled and the GPIOs were configured in up_lowsetup().
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* Disable the UART by clearing the UARTEN bit in the UART CTL register */
|
|
|
|
|
2009-05-19 22:50:47 +02:00
|
|
|
ctl = up_serialin(priv, LM3S_UART_CTL_OFFSET);
|
2009-05-12 20:53:10 +02:00
|
|
|
ctl &= ~UART_CTL_UARTEN;
|
2009-05-19 22:50:47 +02:00
|
|
|
up_serialout(priv, LM3S_UART_CTL_OFFSET, ctl);
|
2009-05-12 20:53:10 +02:00
|
|
|
|
|
|
|
/* Calculate BAUD rate from the SYS clock:
|
|
|
|
*
|
|
|
|
* "The baud-rate divisor is a 22-bit number consisting of a 16-bit integer
|
|
|
|
* and a 6-bit fractional part. The number formed by these two values is
|
|
|
|
* used by the baud-rate generator to determine the bit period. Having a
|
|
|
|
* fractional baud-rate divider allows the UART to generate all the standard
|
|
|
|
* baud rates.
|
|
|
|
*
|
|
|
|
* "The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor
|
|
|
|
* (UARTIBRD) register ... and the 6-bit fractional part is loaded with the
|
|
|
|
* UART Fractional Baud-Rate Divisor (UARTFBRD) register... The baud-rate
|
|
|
|
* divisor (BRD) has the following relationship to the system clock (where
|
|
|
|
* BRDI is the integer part of the BRD and BRDF is the fractional part,
|
|
|
|
* separated by a decimal place.):
|
|
|
|
*
|
|
|
|
* "BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate)
|
|
|
|
*
|
|
|
|
* "where UARTSysClk is the system clock connected to the UART. The 6-bit
|
|
|
|
* fractional number (that is to be loaded into the DIVFRAC bit field in the
|
|
|
|
* UARTFBRD register) can be calculated by taking the fractional part of the
|
|
|
|
* baud-rate divisor, multiplying it by 64, and adding 0.5 to account for
|
|
|
|
* rounding errors:
|
|
|
|
*
|
|
|
|
* "UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
|
|
|
|
*
|
|
|
|
* "The UART generates an internal baud-rate reference clock at 16x the baud-
|
|
|
|
* rate (referred to as Baud16). This reference clock is divided by 16 to
|
|
|
|
* generate the transmit clock, and is used for error detection during receive
|
|
|
|
* operations.
|
|
|
|
*
|
|
|
|
* "Along with the UART Line Control, High Byte (UARTLCRH) register ..., the
|
|
|
|
* UARTIBRD and UARTFBRD registers form an internal 30-bit register. This
|
|
|
|
* internal register is only updated when a write operation to UARTLCRH is
|
|
|
|
* performed, so any changes to the baud-rate divisor must be followed by a
|
|
|
|
* write to the UARTLCRH register for the changes to take effect. ..."
|
|
|
|
*/
|
|
|
|
|
2009-05-20 00:51:33 +02:00
|
|
|
den = priv->baud << 4;
|
2009-05-12 20:53:10 +02:00
|
|
|
brdi = SYSCLK_FREQUENCY / den;
|
2009-05-20 00:51:33 +02:00
|
|
|
remainder = SYSCLK_FREQUENCY - den * brdi;
|
2009-05-12 20:53:10 +02:00
|
|
|
divfrac = ((remainder << 6) + (den >> 1)) / den;
|
|
|
|
|
|
|
|
up_serialout(priv, LM3S_UART_IBRD_OFFSET, brdi);
|
|
|
|
up_serialout(priv, LM3S_UART_FBRD_OFFSET, divfrac);
|
|
|
|
|
|
|
|
/* Set up the LCRH register */
|
|
|
|
|
|
|
|
lcrh = 0;
|
|
|
|
switch (priv->bits)
|
|
|
|
{
|
|
|
|
case 5:
|
|
|
|
lcrh |= UART_LCRH_WLEN_5BITS;
|
|
|
|
break;
|
|
|
|
case 6:
|
|
|
|
lcrh |= UART_LCRH_WLEN_6BITS;
|
|
|
|
break;
|
|
|
|
case 7:
|
|
|
|
lcrh |= UART_LCRH_WLEN_7BITS;
|
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
default:
|
|
|
|
lcrh |= UART_LCRH_WLEN_8BITS;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (priv->parity)
|
|
|
|
{
|
|
|
|
case 0:
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
lcrh |= UART_LCRH_PEN;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
lcrh |= UART_LCRH_PEN|UART_LCRH_EPS;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (priv->stopbits2)
|
|
|
|
{
|
|
|
|
lcrh |= UART_LCRH_STP2;
|
|
|
|
}
|
|
|
|
|
|
|
|
up_serialout(priv, LM3S_UART_LCRH_OFFSET, lcrh);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* Set the UART to interrupt whenever the TX FIFO is almost empty or when
|
|
|
|
* any character is received.
|
|
|
|
*/
|
|
|
|
|
|
|
|
up_serialout(priv, LM3S_UART_IFLS_OFFSET, UART_IFLS_TXIFLSEL_18th|UART_IFLS_RXIFLSEL_18th);
|
|
|
|
|
|
|
|
/* Flush the Rx and Tx FIFOs -- How do you do that?*/
|
|
|
|
|
|
|
|
/* Enable Rx interrupts from the UART except for Tx interrupts. We don't want
|
|
|
|
* Tx interrupts until we have something to send. We will check for serial
|
|
|
|
* errors as part of Rx interrupt processing (no interrupts will be received
|
|
|
|
* yet because the interrupt is still disabled at the interrupt controller.
|
|
|
|
*/
|
|
|
|
|
2009-05-19 22:50:47 +02:00
|
|
|
up_serialout(priv, LM3S_UART_IM_OFFSET, UART_IM_RXIM|UART_IM_RTIM);
|
2009-05-12 20:53:10 +02:00
|
|
|
|
|
|
|
/* Enable the FIFOs */
|
|
|
|
|
2009-05-20 00:51:33 +02:00
|
|
|
#ifdef CONFIG_SUPPRESS_UART_CONFIG
|
2009-05-19 22:50:47 +02:00
|
|
|
lcrh = up_serialin(priv, LM3S_UART_LCRH_OFFSET);
|
2009-05-12 20:53:10 +02:00
|
|
|
#endif
|
|
|
|
lcrh |= UART_LCRH_FEN;
|
2009-05-19 22:50:47 +02:00
|
|
|
up_serialout(priv, LM3S_UART_LCRH_OFFSET, lcrh);
|
2009-05-12 20:53:10 +02:00
|
|
|
|
|
|
|
/* Enable Rx, Tx, and the UART */
|
|
|
|
|
2009-05-20 00:51:33 +02:00
|
|
|
#ifdef CONFIG_SUPPRESS_UART_CONFIG
|
2009-05-12 20:53:10 +02:00
|
|
|
ctl = up_serialin(priv, LM3S_UART_CTL_OFFSET);
|
|
|
|
#endif
|
|
|
|
ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE);
|
|
|
|
up_serialout(priv, LM3S_UART_CTL_OFFSET, ctl);
|
|
|
|
|
|
|
|
/* Set up the cache IM value */
|
|
|
|
|
|
|
|
priv->im = up_serialin(priv, LM3S_UART_IM_OFFSET);
|
|
|
|
return OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: up_shutdown
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Disable the UART. This method is called when the serial
|
|
|
|
* port is closed
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
static void up_shutdown(struct uart_dev_s *dev)
|
|
|
|
{
|
|
|
|
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
|
|
|
|
up_disableuartint(priv, NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: up_attach
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Configure the UART to operation in interrupt driven mode. This method is
|
|
|
|
* called when the serial port is opened. Normally, this is just after the
|
|
|
|
* the setup() method is called, however, the serial console may operate in
|
|
|
|
* a non-interrupt driven mode during the boot phase.
|
|
|
|
*
|
|
|
|
* RX and TX interrupts are not enabled when by the attach method (unless the
|
|
|
|
* hardware supports multiple levels of interrupt enabling). The RX and TX
|
|
|
|
* interrupts are not enabled until the txint() and rxint() methods are called.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
static int up_attach(struct uart_dev_s *dev)
|
|
|
|
{
|
|
|
|
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* Attach and enable the IRQ */
|
|
|
|
|
|
|
|
ret = irq_attach(priv->irq, up_interrupt);
|
|
|
|
if (ret == OK)
|
|
|
|
{
|
|
|
|
/* Enable the interrupt (RX and TX interrupts are still disabled
|
|
|
|
* in the UART
|
|
|
|
*/
|
|
|
|
|
|
|
|
up_enable_irq(priv->irq);
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: up_detach
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Detach UART interrupts. This method is called when the serial port is
|
|
|
|
* closed normally just before the shutdown method is called. The exception is
|
|
|
|
* the serial console which is never shutdown.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
static void up_detach(struct uart_dev_s *dev)
|
|
|
|
{
|
|
|
|
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
|
|
|
|
up_disable_irq(priv->irq);
|
|
|
|
irq_detach(priv->irq);
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: up_interrupt
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* This is the UART interrupt handler. It will be invoked
|
|
|
|
* when an interrupt received on the 'irq' It should call
|
|
|
|
* uart_transmitchars or uart_receivechar to perform the
|
|
|
|
* appropriate data transfers. The interrupt handling logic\
|
|
|
|
* must be able to map the 'irq' number into the approprite
|
|
|
|
* uart_dev_s structure in order to call these functions.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
static int up_interrupt(int irq, void *context)
|
|
|
|
{
|
|
|
|
struct uart_dev_s *dev = NULL;
|
|
|
|
struct up_dev_s *priv;
|
2009-12-16 21:05:51 +01:00
|
|
|
uint32_t mis;
|
2009-05-12 20:53:10 +02:00
|
|
|
int passes;
|
2009-12-16 21:05:51 +01:00
|
|
|
bool handled;
|
2009-05-12 20:53:10 +02:00
|
|
|
|
2013-01-09 15:48:55 +01:00
|
|
|
#ifdef CONFIG_LM_UART0
|
2009-05-12 20:53:10 +02:00
|
|
|
if (g_uart0priv.irq == irq)
|
|
|
|
{
|
|
|
|
dev = &g_uart0port;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
#endif
|
2013-01-09 15:48:55 +01:00
|
|
|
#ifdef CONFIG_LM_UART1
|
2009-05-12 20:53:10 +02:00
|
|
|
if (g_uart1priv.irq == irq)
|
|
|
|
{
|
|
|
|
dev = &g_uart1port;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
#endif
|
|
|
|
{
|
|
|
|
PANIC(OSERR_INTERNAL);
|
|
|
|
}
|
|
|
|
priv = (struct up_dev_s*)dev->priv;
|
|
|
|
|
|
|
|
/* Loop until there are no characters to be transferred or,
|
|
|
|
* until we have been looping for a long time.
|
|
|
|
*/
|
|
|
|
|
2009-12-16 21:05:51 +01:00
|
|
|
handled = true;
|
2009-05-12 20:53:10 +02:00
|
|
|
for (passes = 0; passes < 256 && handled; passes++)
|
|
|
|
{
|
2009-12-16 21:05:51 +01:00
|
|
|
handled = false;
|
2009-05-12 20:53:10 +02:00
|
|
|
|
|
|
|
/* Get the masked UART status and clear the pending interrupts. */
|
|
|
|
|
|
|
|
mis = up_serialin(priv, LM3S_UART_MIS_OFFSET);
|
|
|
|
up_serialout(priv, LM3S_UART_ICR_OFFSET, mis);
|
|
|
|
|
|
|
|
/* Handle incoming, receive bytes (with or without timeout) */
|
|
|
|
|
|
|
|
if ((mis & (UART_MIS_RXMIS|UART_MIS_RTMIS)) != 0)
|
|
|
|
{
|
|
|
|
/* Rx buffer not empty ... process incoming bytes */
|
|
|
|
|
|
|
|
uart_recvchars(dev);
|
2009-12-16 21:05:51 +01:00
|
|
|
handled = true;
|
2009-05-12 20:53:10 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Handle outgoing, transmit bytes */
|
|
|
|
|
2009-05-20 00:14:36 +02:00
|
|
|
if ((mis & UART_MIS_TXMIS) != 0)
|
2009-05-12 20:53:10 +02:00
|
|
|
{
|
|
|
|
/* Tx FIFO not full ... process outgoing bytes */
|
|
|
|
|
|
|
|
uart_xmitchars(dev);
|
2009-12-16 21:05:51 +01:00
|
|
|
handled = true;
|
2009-05-12 20:53:10 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
return OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: up_ioctl
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* All ioctl calls will be routed through this method
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
|
|
|
|
{
|
|
|
|
struct inode *inode = filep->f_inode;
|
|
|
|
struct uart_dev_s *dev = inode->i_private;
|
|
|
|
int ret = OK;
|
|
|
|
|
|
|
|
switch (cmd)
|
|
|
|
{
|
|
|
|
case TIOCSERGSTRUCT:
|
|
|
|
{
|
|
|
|
struct up_dev_s *user = (struct up_dev_s*)arg;
|
|
|
|
if (!user)
|
|
|
|
{
|
2012-08-01 01:45:21 +02:00
|
|
|
ret = -EINVAL;
|
2009-05-12 20:53:10 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
memcpy(user, dev, sizeof(struct up_dev_s));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
2012-08-01 01:45:21 +02:00
|
|
|
ret = -ENOTTY;
|
2009-05-12 20:53:10 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: up_receive
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Called (usually) from the interrupt level to receive one
|
|
|
|
* character from the UART. Error bits associated with the
|
2009-06-25 19:44:35 +02:00
|
|
|
* receipt are provided in the return 'status'.
|
2009-05-12 20:53:10 +02:00
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2009-12-16 21:05:51 +01:00
|
|
|
static int up_receive(struct uart_dev_s *dev, uint32_t *status)
|
2009-05-12 20:53:10 +02:00
|
|
|
{
|
|
|
|
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
|
2009-12-16 21:05:51 +01:00
|
|
|
uint32_t rxd;
|
2009-05-12 20:53:10 +02:00
|
|
|
|
|
|
|
/* Get the Rx byte + 4 bits of error information. Return those in status */
|
|
|
|
|
|
|
|
rxd = up_serialin(priv, LM3S_UART_DR_OFFSET);
|
|
|
|
*status = rxd;
|
|
|
|
|
|
|
|
/* The lower 8bits of the Rx data is the actual recevied byte */
|
|
|
|
|
|
|
|
return rxd & 0xff;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: up_rxint
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Call to enable or disable RX interrupts
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2009-12-16 21:05:51 +01:00
|
|
|
static void up_rxint(struct uart_dev_s *dev, bool enable)
|
2009-05-12 20:53:10 +02:00
|
|
|
{
|
|
|
|
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
|
|
|
|
if (enable)
|
|
|
|
{
|
|
|
|
/* Receive an interrupt when their is anything in the Rx FIFO (or an Rx
|
|
|
|
* timeout occurs.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
|
|
|
|
priv->im |= (UART_IM_RXIM|UART_IM_RTIM);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
priv->im &= ~(UART_IM_RXIM|UART_IM_RTIM);
|
|
|
|
}
|
|
|
|
up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im);
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: up_rxavailable
|
|
|
|
*
|
|
|
|
* Description:
|
2009-12-16 21:05:51 +01:00
|
|
|
* Return true if the receive fifo is not empty
|
2009-05-12 20:53:10 +02:00
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2009-12-16 21:05:51 +01:00
|
|
|
static bool up_rxavailable(struct uart_dev_s *dev)
|
2009-05-12 20:53:10 +02:00
|
|
|
{
|
|
|
|
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
|
|
|
|
return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_RXFE) == 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: up_send
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* This method will send one byte on the UART
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
static void up_send(struct uart_dev_s *dev, int ch)
|
|
|
|
{
|
|
|
|
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
|
2009-12-16 21:05:51 +01:00
|
|
|
up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)ch);
|
2009-05-12 20:53:10 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: up_txint
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Call to enable or disable TX interrupts
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2009-12-16 21:05:51 +01:00
|
|
|
static void up_txint(struct uart_dev_s *dev, bool enable)
|
2009-05-12 20:53:10 +02:00
|
|
|
{
|
|
|
|
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
|
2009-05-20 00:51:33 +02:00
|
|
|
irqstate_t flags;
|
|
|
|
|
|
|
|
flags = irqsave();
|
2009-05-12 20:53:10 +02:00
|
|
|
if (enable)
|
|
|
|
{
|
|
|
|
/* Set to receive an interrupt when the TX fifo is half emptied */
|
2009-05-20 00:51:33 +02:00
|
|
|
|
2009-05-12 20:53:10 +02:00
|
|
|
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
|
|
|
|
priv->im |= UART_IM_TXIM;
|
2009-05-20 00:51:33 +02:00
|
|
|
up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im);
|
|
|
|
|
|
|
|
/* The serial driver wants an interrupt here, but will not get get
|
|
|
|
* one unless we "prime the pump." I believe that this is because
|
|
|
|
* behave like a level interrupt and the LM3S interrupts behave
|
|
|
|
* (at least by default) like edge interrupts.
|
|
|
|
*
|
|
|
|
* In any event, faking a TX interrupt here solves the problem;
|
|
|
|
* Call uart_xmitchars() just as would have been done if we recieved
|
|
|
|
* the TX interrupt.
|
|
|
|
*/
|
|
|
|
|
|
|
|
uart_xmitchars(dev);
|
2009-05-12 20:53:10 +02:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2009-05-20 00:51:33 +02:00
|
|
|
/* Disable the TX interrupt */
|
|
|
|
|
2009-05-12 20:53:10 +02:00
|
|
|
priv->im &= ~UART_IM_TXIM;
|
2009-05-20 00:51:33 +02:00
|
|
|
up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im);
|
2009-05-12 20:53:10 +02:00
|
|
|
}
|
2009-05-20 00:51:33 +02:00
|
|
|
irqrestore(flags);
|
2009-05-12 20:53:10 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: up_txready
|
|
|
|
*
|
|
|
|
* Description:
|
2009-12-16 21:05:51 +01:00
|
|
|
* Return true if the tranmsit fifo is not full
|
2009-05-12 20:53:10 +02:00
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2009-12-16 21:05:51 +01:00
|
|
|
static bool up_txready(struct uart_dev_s *dev)
|
2009-05-12 20:53:10 +02:00
|
|
|
{
|
|
|
|
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
|
|
|
|
return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFF) == 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: up_txempty
|
|
|
|
*
|
|
|
|
* Description:
|
2009-12-16 21:05:51 +01:00
|
|
|
* Return true if the transmit fifo is empty
|
2009-05-12 20:53:10 +02:00
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2009-12-16 21:05:51 +01:00
|
|
|
static bool up_txempty(struct uart_dev_s *dev)
|
2009-05-12 20:53:10 +02:00
|
|
|
{
|
|
|
|
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
|
|
|
|
return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFE) != 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
2009-05-17 19:18:19 +02:00
|
|
|
* Public Functions
|
2009-05-12 20:53:10 +02:00
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: up_serialinit
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Performs the low level UART initialization early in
|
|
|
|
* debug so that the serial console will be available
|
|
|
|
* during bootup. This must be called before up_serialinit.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
void up_earlyserialinit(void)
|
|
|
|
{
|
|
|
|
/* NOTE: All GPIO configuration for the UARTs was performed in
|
|
|
|
* up_lowsetup
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* Disable all UARTS */
|
|
|
|
|
|
|
|
up_disableuartint(TTYS0_DEV.priv, NULL);
|
|
|
|
#ifdef TTYS1_DEV
|
|
|
|
up_disableuartint(TTYS1_DEV.priv, NULL);
|
|
|
|
#endif
|
2010-05-07 04:32:56 +02:00
|
|
|
#ifdef TTYS2_DEV
|
|
|
|
up_disableuartint(TTYS2_DEV.priv, NULL);
|
|
|
|
#endif
|
2009-05-12 20:53:10 +02:00
|
|
|
|
|
|
|
/* Configuration whichever one is the console */
|
|
|
|
|
|
|
|
#ifdef HAVE_CONSOLE
|
2009-12-16 21:05:51 +01:00
|
|
|
CONSOLE_DEV.isconsole = true;
|
2009-05-12 20:53:10 +02:00
|
|
|
up_setup(&CONSOLE_DEV);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: up_serialinit
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Register serial console and serial ports. This assumes
|
|
|
|
* that up_earlyserialinit was called previously.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
void up_serialinit(void)
|
|
|
|
{
|
|
|
|
/* Register the console */
|
|
|
|
|
|
|
|
#ifdef HAVE_CONSOLE
|
|
|
|
(void)uart_register("/dev/console", &CONSOLE_DEV);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* Register all UARTs */
|
|
|
|
|
|
|
|
(void)uart_register("/dev/ttyS0", &TTYS0_DEV);
|
|
|
|
#ifdef TTYS1_DEV
|
|
|
|
(void)uart_register("/dev/ttyS1", &TTYS1_DEV);
|
|
|
|
#endif
|
2010-05-07 04:32:56 +02:00
|
|
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#ifdef TTYS2_DEV
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(void)uart_register("/dev/ttyS2", &TTYS2_DEV);
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#endif
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2009-05-12 20:53:10 +02:00
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}
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/****************************************************************************
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|
* Name: up_putc
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*
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* Description:
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* Provide priority, low-level access to support OS debug writes
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*
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****************************************************************************/
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int up_putc(int ch)
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{
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#ifdef HAVE_CONSOLE
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struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv;
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2009-12-16 21:05:51 +01:00
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uint32_t im;
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2009-05-12 20:53:10 +02:00
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up_disableuartint(priv, &im);
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|
up_waittxnotfull(priv);
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2009-12-16 21:05:51 +01:00
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up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)ch);
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2009-05-12 20:53:10 +02:00
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|
/* Check for LF */
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if (ch == '\n')
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|
{
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|
/* Add CR */
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|
|
|
|
up_waittxnotfull(priv);
|
2009-12-16 21:05:51 +01:00
|
|
|
up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)'\r');
|
2009-05-12 20:53:10 +02:00
|
|
|
}
|
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|
|
|
|
up_waittxnotfull(priv);
|
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|
|
up_restoreuartint(priv, im);
|
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|
|
#endif
|
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|
|
return ch;
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|
|
|
}
|
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|
|
|
2012-02-11 04:50:52 +01:00
|
|
|
#else /* USE_SERIALDRIVER */
|
2009-05-12 20:53:10 +02:00
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: up_putc
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Provide priority, low-level access to support OS debug writes
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
int up_putc(int ch)
|
|
|
|
{
|
|
|
|
#ifdef HAVE_CONSOLE
|
|
|
|
/* Check for LF */
|
|
|
|
|
|
|
|
if (ch == '\n')
|
|
|
|
{
|
|
|
|
/* Add CR */
|
|
|
|
|
|
|
|
up_lowputc('\r');
|
|
|
|
}
|
|
|
|
|
|
|
|
up_lowputc(ch);
|
|
|
|
#endif
|
|
|
|
return ch;
|
|
|
|
}
|
|
|
|
|
2012-02-11 04:50:52 +01:00
|
|
|
#endif /* USE_SERIALDRIVER */
|