2017-02-26 12:39:44 +01:00
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/****************************************************************************
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* arch/arm/src/stm32/stm32f33xxx_rcc.c
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*
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* Copyright (C) 2012, 2015, 2017 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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* Modified for STM32F334 by Mateusz Szafoni <raiden00@railab.me>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Allow up to 100 milliseconds for the high speed clock to become ready.
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* that is a very long delay, but if the clock does not become ready we are
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* hosed anyway. Normally this is very fast, but I have seen at least one
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* board that required this long, long timeout for the HSE to be ready.
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*/
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#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: rcc_reset
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*
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* Description:
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* Put all RCC registers in reset state
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*
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****************************************************************************/
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static inline void rcc_reset(void)
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{
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uint32_t regval;
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putreg32(0, STM32_RCC_APB2RSTR); /* Disable APB2 Peripheral Reset */
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putreg32(0, STM32_RCC_APB1RSTR); /* Disable APB1 Peripheral Reset */
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putreg32(RCC_AHBENR_FLITFEN | RCC_AHBENR_SRAMEN, STM32_RCC_AHBENR); /* FLITF and SRAM Clock ON */
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putreg32(0, STM32_RCC_APB2ENR); /* Disable APB2 Peripheral Clock */
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putreg32(0, STM32_RCC_APB1ENR); /* Disable APB1 Peripheral Clock */
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regval = getreg32(STM32_RCC_CR); /* Set the HSION bit */
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regval |= RCC_CR_HSION;
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putreg32(regval, STM32_RCC_CR);
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regval = getreg32(STM32_RCC_CFGR); /* Reset SW, HPRE, PPRE1, PPRE2, and MCO bits */
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regval &= ~(RCC_CFGR_SW_MASK | RCC_CFGR_HPRE_MASK | RCC_CFGR_PPRE1_MASK |
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RCC_CFGR_PPRE2_MASK | RCC_CFGR_MCO_MASK);
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putreg32(regval, STM32_RCC_CFGR);
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regval = getreg32(STM32_RCC_CFGR2); /* Reset PREDIV, and ADC12PRE bits */
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regval &= ~(RCC_CFGR2_PREDIV_MASK | RCC_CFGR2_ADC12PRES_MASK);
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putreg32(regval, STM32_RCC_CFGR2);
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regval = getreg32(STM32_RCC_CFGR3); /* Reset all U[S]ARTs, I2C1, TIM1 and HRTIM1 bits */
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regval &= ~(RCC_CFGR3_USART1SW_MASK | RCC_CFGR3_USART2SW_MASK | RCC_CFGR3_USART3SW_MASK | \
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RCC_CFGR3_I2C1SW | RCC_CFGR3_TIM1SW | RCC_CFGR3_HRTIM1SW);
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putreg32(regval, STM32_RCC_CFGR3);
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regval = getreg32(STM32_RCC_CR); /* Reset HSEON, CSSON and PLLON bits */
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regval &= ~(RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
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putreg32(regval, STM32_RCC_CR);
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regval = getreg32(STM32_RCC_CR); /* Reset HSEBYP bit */
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regval &= ~RCC_CR_HSEBYP;
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putreg32(regval, STM32_RCC_CR);
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regval = getreg32(STM32_RCC_CFGR); /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
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regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL_MASK);
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putreg32(regval, STM32_RCC_CFGR);
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putreg32(0, STM32_RCC_CIR); /* Disable all interrupts */
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}
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/****************************************************************************
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* Name: rcc_enableahb
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*
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* Description:
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* Enable selected AHB peripherals
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*
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****************************************************************************/
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static inline void rcc_enableahb(void)
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{
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uint32_t regval;
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/* Always enable FLITF clock and SRAM clock */
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regval = RCC_AHBENR_FLITFEN | RCC_AHBENR_SRAMEN;
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/* Enable GPIO PORTA, PORTB, ... PORTF */
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regval |= (RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPBEN | RCC_AHBENR_IOPCEN |
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RCC_AHBENR_IOPDEN | RCC_AHBENR_IOPFEN);
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#ifdef CONFIG_STM32_DMA1
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/* DMA 1 clock enable */
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regval |= RCC_AHBENR_DMA1EN;
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#endif
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#ifdef CONFIG_STM32_CRC
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/* CRC clock enable */
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regval |= RCC_AHBENR_CRCEN;
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#endif
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#ifdef CONFIG_STM32_TSC
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/* CRC clock enable */
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regval |= RCC_AHBENR_TSCEN;
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#endif
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#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)
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/* ADC1/ADC2 interface clock enable */
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regval |= RCC_AHBENR_ADC12EN;
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#endif
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putreg32(regval, STM32_RCC_AHBENR); /* Enable peripherals */
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}
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/****************************************************************************
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* Name: rcc_enableapb1
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*
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* Description:
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* Enable selected APB1 peripherals
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*
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****************************************************************************/
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static inline void rcc_enableapb1(void)
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{
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uint32_t regval;
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/* Set the appropriate bits in the APB1ENR register to enabled the
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* selected APB1 peripherals.
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*/
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regval = getreg32(STM32_RCC_APB1ENR);
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#ifdef CONFIG_STM32_TIM2
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/* Timer 2 clock enable */
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#ifdef CONFIG_STM32_FORCEPOWER
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regval |= RCC_APB1ENR_TIM2EN;
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#endif
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#endif
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#ifdef CONFIG_STM32_TIM3
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/* Timer 3 clock enable */
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#ifdef CONFIG_STM32_FORCEPOWER
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regval |= RCC_APB1ENR_TIM3EN;
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#endif
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#endif
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#ifdef CONFIG_STM32_TIM6
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/* Timer 6 clock enable */
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#ifdef CONFIG_STM32_FORCEPOWER
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regval |= RCC_APB1ENR_TIM6EN;
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#endif
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#endif
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#ifdef CONFIG_STM32_TIM7
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/* Timer 7 clock enable */
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#ifdef CONFIG_STM32_FORCEPOWER
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regval |= RCC_APB1ENR_TIM7EN;
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#endif
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#endif
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#ifdef CONFIG_STM32_WWDG
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/* Window Watchdog clock enable */
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regval |= RCC_APB1ENR_WWDGEN;
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#endif
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#ifdef CONFIG_STM32_USART2
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/* USART 2 clock enable */
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regval |= RCC_APB1ENR_USART2EN;
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#endif
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#ifdef CONFIG_STM32_USART3
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/* USART 3 clock enable */
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regval |= RCC_APB1ENR_USART3EN;
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#endif
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#ifdef CONFIG_STM32_I2C1
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/* I2C 1 clock enable */
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#ifdef CONFIG_STM32_FORCEPOWER
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regval |= RCC_APB1ENR_I2C1EN;
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#endif
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#endif
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#ifdef CONFIG_STM32_CAN1
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/* CAN1 clock enable */
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regval |= RCC_APB1ENR_CAN1EN;
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#endif
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#ifdef CONFIG_STM32_DAC2
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/* DAC2 interface clock enable */
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regval |= RCC_APB1ENR_DAC2EN;
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#endif
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#ifdef CONFIG_STM32_PWR
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/* Power interface clock enable */
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regval |= RCC_APB1ENR_PWREN;
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#endif
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#ifdef CONFIG_STM32_DAC1
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/* DAC1 interface clock enable */
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regval |= RCC_APB1ENR_DAC1EN;
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#endif
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putreg32(regval, STM32_RCC_APB1ENR);
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}
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/****************************************************************************
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* Name: rcc_enableapb2
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*
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* Description:
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* Enable selected APB2 peripherals
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*
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****************************************************************************/
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static inline void rcc_enableapb2(void)
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{
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uint32_t regval;
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/* Set the appropriate bits in the APB2ENR register to enabled the
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* selected APB2 peripherals.
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*/
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regval = getreg32(STM32_RCC_APB2ENR);
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#ifdef CONFIG_STM32_SYSCFG
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/* SYSCFG clock */
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regval |= RCC_APB2ENR_SYSCFGEN;
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#endif
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#ifdef CONFIG_STM32_TIM1
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/* TIM1 Timer clock enable */
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#ifdef CONFIG_STM32_FORCEPOWER
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regval |= RCC_APB2ENR_TIM1EN;
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#endif
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#endif
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#ifdef CONFIG_STM32_SPI1
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/* SPI 1 clock enable */
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regval |= RCC_APB2ENR_SPI1EN;
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#endif
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#ifdef CONFIG_STM32_USART1
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/* USART1 clock enable */
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regval |= RCC_APB2ENR_USART1EN;
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#endif
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#ifdef CONFIG_STM32_TIM15
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/* TIM15 Timer clock enable */
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#ifdef CONFIG_STM32_FORCEPOWER
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regval |= RCC_APB2ENR_TIM15EN;
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#endif
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#endif
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#ifdef CONFIG_STM32_TIM16
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/* TIM16 Timer clock enable */
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#ifdef CONFIG_STM32_FORCEPOWER
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regval |= RCC_APB2ENR_TIM16EN;
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#endif
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#endif
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#ifdef CONFIG_STM32_TIM17
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/* TIM17 Timer clock enable */
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#ifdef CONFIG_STM32_FORCEPOWER
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regval |= RCC_APB2ENR_TIM17EN;
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#endif
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#endif
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#ifdef CONFIG_STM32_HRTIM1
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/* HRTIM1 Timer clock enable */
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regval |= RCC_APB2ENR_HRTIM1EN;
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#endif
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putreg32(regval, STM32_RCC_APB2ENR);
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}
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/****************************************************************************
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* Name: stm32_stdclockconfig
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*
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* Description:
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2017-06-26 18:30:10 +02:00
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* Called to change to new clock based on settings in board.h.
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2017-02-26 12:39:44 +01:00
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*
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* NOTE: This logic would need to be extended if you need to select low-
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* power clocking modes!
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****************************************************************************/
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2017-06-26 18:30:10 +02:00
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#if !defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG)
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2017-02-26 12:39:44 +01:00
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static void stm32_stdclockconfig(void)
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{
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uint32_t regval;
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/* If the PLL is using the HSE, or the HSE is the system clock */
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#if (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC) || (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE)
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{
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volatile int32_t timeout;
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/* Enable External High-Speed Clock (HSE) */
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regval = getreg32(STM32_RCC_CR);
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regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */
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regval |= RCC_CR_HSEON; /* Enable HSE */
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putreg32(regval, STM32_RCC_CR);
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/* Wait until the HSE is ready (or until a timeout elapsed) */
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for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
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{
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/* Check if the HSERDY flag is the set in the CR */
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if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
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{
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/* If so, then break-out with timeout > 0 */
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break;
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}
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}
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|
|
if (timeout == 0)
|
|
|
|
{
|
|
|
|
/* In the case of a timeout starting the HSE, we really don't have a
|
|
|
|
* strategy. This is almost always a hardware failure or
|
|
|
|
* misconfiguration.
|
|
|
|
*/
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* Set the HCLK source/divider */
|
|
|
|
|
|
|
|
regval = getreg32(STM32_RCC_CFGR);
|
|
|
|
regval &= ~RCC_CFGR_HPRE_MASK;
|
|
|
|
regval |= STM32_RCC_CFGR_HPRE;
|
|
|
|
putreg32(regval, STM32_RCC_CFGR);
|
|
|
|
|
|
|
|
/* Set the PCLK2 divider */
|
|
|
|
|
|
|
|
regval = getreg32(STM32_RCC_CFGR);
|
|
|
|
regval &= ~RCC_CFGR_PPRE2_MASK;
|
|
|
|
regval |= STM32_RCC_CFGR_PPRE2;
|
|
|
|
putreg32(regval, STM32_RCC_CFGR);
|
|
|
|
|
|
|
|
/* Set the PCLK1 divider */
|
|
|
|
|
|
|
|
regval = getreg32(STM32_RCC_CFGR);
|
|
|
|
regval &= ~RCC_CFGR_PPRE1_MASK;
|
|
|
|
regval |= STM32_RCC_CFGR_PPRE1;
|
|
|
|
putreg32(regval, STM32_RCC_CFGR);
|
|
|
|
|
|
|
|
#if STM32_SYSCLK_SW == RCC_CFGR_SW_PLL
|
|
|
|
/* If we are using the PLL, configure and start it */
|
|
|
|
/* Set the PLL divider and multiplier */
|
|
|
|
|
|
|
|
regval = getreg32(STM32_RCC_CFGR);
|
|
|
|
regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL_MASK);
|
|
|
|
regval |= (STM32_CFGR_PLLSRC | STM32_CFGR_PLLXTPRE | STM32_CFGR_PLLMUL);
|
|
|
|
putreg32(regval, STM32_RCC_CFGR);
|
|
|
|
|
|
|
|
/* Enable the PLL */
|
|
|
|
|
|
|
|
regval = getreg32(STM32_RCC_CR);
|
|
|
|
regval |= RCC_CR_PLLON;
|
|
|
|
putreg32(regval, STM32_RCC_CR);
|
|
|
|
|
|
|
|
/* Wait until the PLL is ready */
|
|
|
|
|
|
|
|
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* Select the system clock source (probably the PLL) */
|
|
|
|
|
|
|
|
regval = getreg32(STM32_RCC_CFGR);
|
|
|
|
regval &= ~RCC_CFGR_SW_MASK;
|
|
|
|
regval |= STM32_SYSCLK_SW;
|
|
|
|
putreg32(regval, STM32_RCC_CFGR);
|
|
|
|
|
|
|
|
/* Wait until the selected source is used as the system clock source */
|
|
|
|
|
|
|
|
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS);
|
|
|
|
|
|
|
|
#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_RTC_LSICLOCK)
|
|
|
|
/* Low speed internal clock source LSI
|
|
|
|
*
|
|
|
|
* TODO: There is another case where the LSI needs to
|
|
|
|
* be enabled: if the MCO pin selects LSI as source.
|
|
|
|
*/
|
|
|
|
|
|
|
|
stm32_rcc_enablelsi();
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#if defined(CONFIG_RTC_LSECLOCK)
|
|
|
|
/* Low speed external clock source LSE
|
|
|
|
*
|
|
|
|
* TODO: There is another case where the LSE needs to
|
|
|
|
* be enabled: if the MCO pin selects LSE as source.
|
|
|
|
*
|
|
|
|
* TODO: There is another case where the LSE needs to
|
|
|
|
* be enabled: if USARTx selects LSE as source.
|
|
|
|
*/
|
|
|
|
|
|
|
|
stm32_rcc_enablelse();
|
|
|
|
#endif
|
2017-06-26 18:30:10 +02:00
|
|
|
|
|
|
|
#ifdef CONFIG_STM32_HRTIM_CLK_FROM_PLL
|
|
|
|
regval = getreg32(STM32_RCC_CFGR3);
|
|
|
|
regval |= RCC_CFGR3_HRTIM1SW;
|
|
|
|
putreg32(regval, STM32_RCC_CFGR3);
|
|
|
|
#endif
|
2017-02-26 12:39:44 +01:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: rcc_enableperiphals
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
static inline void rcc_enableperipherals(void)
|
|
|
|
{
|
|
|
|
rcc_enableahb();
|
|
|
|
rcc_enableapb2();
|
|
|
|
rcc_enableapb1();
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Public Functions
|
|
|
|
****************************************************************************/
|