Please note that the PHY is reset on power up by pulling the RESET_N signal down with a resistor.
ESP32 should assert RESET_N high with GPIO5 to enable PHY. Only this can ensure the power-up of system.
Otherwise ESP32 may enter download mode (when the clock signal of REF_CLK_50M is at a high logic level during
the GPIO0 power-up sampling phase).
RMII Clock Sourced Internally from ESP32's APLL
-----------------------------------------------
Another option is to source the RMII Clock from internal ESP32 APLL, see figure below.
The clock signal coming from GPIO0 is first inverted, to account for transmission line delay,
and then supplied to the PHY.
..figure:: esp32-ethernet-kit-rmii-clk-to-phy.png
:align:center
:scale:80%
:alt:RMII Clock from ESP Internal APLL
:figclass:align-center
RMII Clock from ESP Internal APLL
To implement this option, users need to remove or add some RC components on the board.
For details please refer to the `ESP32-Ethernet-Kit V1.2 Ethernet board (A) schematic <https://dl.espressif.com/dl/schematics/SCH_ESP32-Ethernet-Kit_A_V1.2_20200528.pdf>`_,
sheet 2, location D2. Please note that if the APLL is already used for other purposes
(e.g. I2S peripheral), then you have no choice but use an external RMII clock.
Serial Console
==============
UART0 is, by default, the serial console. It connects to the on-board
CP2102N bridge and is available on the USB connector.
It will show up as /dev/ttyUSB[n] where [n] will probably be 0.
Buttons and LEDs
================
Board Buttons
-------------
There are two buttons labeled Boot and EN. The EN button is not available
to software. It pulls the chip enable line that doubles as a reset line.
The BOOT button is connected to IO0. On reset it is used as a strapping
pin to determine whether the chip boots normally or into the serial
bootloader. After reset, however, the BOOT button can be used for software
input.
Board LEDs
----------
There are several on-board LEDs for that indicate the presence of power
and USB activity. None of these are available for use by software.
1. To prevent the power-on state of the GPIO0 from being affected by the clock output on the PHY side,
the RESET_N signal to PHY defaults to low, turning the clock output off. After power-on you can control
RESET_N with GPIO5 to turn the clock output on. See also `RMII Clock Sourced Externally by PHY`_. For
PHYs that cannot turn off the clock output through RESET_N, it is recommended to use a crystal module
that can be disabled/enabled externally. Similarly like when using RESET_N, the oscillator module should
be disabled by default and turned on by ESP32 after power-up.
For a reference design please see `ESP32-Ethernet-Kit V1.2 Ethernet board (A) schematic <https://dl.espressif.com/dl/schematics/SCH_ESP32-Ethernet-Kit_A_V1.2_20200528.pdf>`_.
2. The ESP32 pins GPIO16 and GPIO17 are not broken out to the ESP32-WROVER-E module and therefore not available for use.
Configurations
==============
All of the configurations presented below can be tested by running the following commands::
