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nuttx/configs/nucleo-l073rz/nsh/defconfig

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tools/Makefile.unix, .win, and all defconfig files: Modify tools/Makefiles to add warning on defconfig files
2019-03-03 15:30:14 +01:00
#
# This file is autogenerated: PLEASE DO NOT EDIT IT.
#
# You can use "make menuconfig" to make any modifications to the installed .config file.
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
# modifications.
#
Brings in initial WIP support for the STML0. This initial commit is in pretty bad shape and, hence it it marked EXPERIMENTAL." Squashed commit of the following: arch/arm/src/stm32f0l0: Various changes for a clean compilation. Still does not compile correctly due to missing FLASH latency definitions. arch/arm/src/stm32f0l0/hardware: Add framework for the STM32 L0. Currently set to same as the STM32F0. arch/arm/src/stm32f0l0/hardware: Very fragmentary FLASH header register definitions for the STM32 L0. arch/arm/src/stm32f0l0: Bring in DMA v1. Cannot possibly be functionaly yet due to the limited number for M0 interrupts. arch/arm/src/stm32f0l0: Add STM32 F0/L0 LSE and backup power domain controls. arch/arm/src/stm32f0l0/hardware/stm32l0_pwr.h: Add STM32L0 PWR header file. arch/arm/include/stm32f0l0/chip.h: Clean up WIP chip header file. arch/arm/include/stm32f0l0/chip.h: WIP. arm/src/stm32f0l0: Resolve some small differences between F0 and L0 GPIO pin options. arch/arm/src/stm32f0l0: Better integrate STM32L0 header files. nuttx/arch/arm/include/stm32f0l0: Add STM32L0 IRQ number definition file. arch/arm/src/stm32f0l0: Add STM32L0 RCC driver. arch/arm/src/stm32f0l0/hardware: Adds basic STM32L0 header files. arch/arm/src/stm32f0l0: Add STM32L0 chip selections. configs/: Hook new STM32L0 boards into the configuration system. configs: nucleo boards use as default ST LINK MCO as clock input from MCU and for this HSEBYP must be enabled configs: add basic support for nucleo-l073rz configs: add basic support for b-l072z-lrwan1
2018-12-19 19:36:35 +01:00
# CONFIG_LIBC_LONG_LONG is not set
# CONFIG_NSH_ARGCAT is not set
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="nucleo-l073rz"
CONFIG_ARCH_BOARD_NUCLEO_L073RZ=y
CONFIG_ARCH_CHIP_STM32L073RZ=y
CONFIG_ARCH_CHIP_STM32L0=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_BOARD_LOOPSPERMSEC=2796
CONFIG_BUILTIN=y
CONFIG_DISABLE_ENVIRON=y
CONFIG_DISABLE_MOUNTPOINT=y
CONFIG_DISABLE_MQUEUE=y
CONFIG_DISABLE_POSIX_TIMERS=y
CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
CONFIG_EXAMPLES_HELLO=y
CONFIG_EXPERIMENTAL=y
CONFIG_INTELHEX_BINARY=y
CONFIG_MAX_TASKS=8
CONFIG_MAX_WDOGPARMS=2
CONFIG_NFILE_DESCRIPTORS=6
CONFIG_NFILE_STREAMS=6
CONFIG_NPTHREAD_KEYS=0
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_FILEIOSIZE=64
CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_NUNGET_CHARS=0
CONFIG_PREALLOC_TIMERS=0
CONFIG_PREALLOC_WDOGS=4
CONFIG_PTHREAD_MUTEX_UNSAFE=y
CONFIG_PTHREAD_STACK_DEFAULT=1536
CONFIG_RAM_SIZE=20480
CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_WAITPID=y
CONFIG_SDCLONE_DISABLE=y
CONFIG_START_DAY=19
CONFIG_START_MONTH=5
CONFIG_START_YEAR=2013
CONFIG_STDIO_DISABLE_BUFFERING=y
Rename STM32F0L0 to STM32F0L0G0 since it now alsow supports the STM32G0 thanks to Mateusz Szafoni's contribution Squashed commit of the following: arch/arm: Rename include/stm32f0l0 and src/stm32f0l0 to stm32f0l0g0. Change all occurrences of lower-case stm32f0l0 to stm32f0l0g0. Change all occurrences of upper-case STM32F0L0 to STM32F0L0G0.
2019-05-27 16:16:24 +02:00
CONFIG_STM32F0L0G0_PWR=y
CONFIG_STM32F0L0G0_USART2=y
Brings in initial WIP support for the STML0. This initial commit is in pretty bad shape and, hence it it marked EXPERIMENTAL." Squashed commit of the following: arch/arm/src/stm32f0l0: Various changes for a clean compilation. Still does not compile correctly due to missing FLASH latency definitions. arch/arm/src/stm32f0l0/hardware: Add framework for the STM32 L0. Currently set to same as the STM32F0. arch/arm/src/stm32f0l0/hardware: Very fragmentary FLASH header register definitions for the STM32 L0. arch/arm/src/stm32f0l0: Bring in DMA v1. Cannot possibly be functionaly yet due to the limited number for M0 interrupts. arch/arm/src/stm32f0l0: Add STM32 F0/L0 LSE and backup power domain controls. arch/arm/src/stm32f0l0/hardware/stm32l0_pwr.h: Add STM32L0 PWR header file. arch/arm/include/stm32f0l0/chip.h: Clean up WIP chip header file. arch/arm/include/stm32f0l0/chip.h: WIP. arm/src/stm32f0l0: Resolve some small differences between F0 and L0 GPIO pin options. arch/arm/src/stm32f0l0: Better integrate STM32L0 header files. nuttx/arch/arm/include/stm32f0l0: Add STM32L0 IRQ number definition file. arch/arm/src/stm32f0l0: Add STM32L0 RCC driver. arch/arm/src/stm32f0l0/hardware: Adds basic STM32L0 header files. arch/arm/src/stm32f0l0: Add STM32L0 chip selections. configs/: Hook new STM32L0 boards into the configuration system. configs: nucleo boards use as default ST LINK MCO as clock input from MCU and for this HSEBYP must be enabled configs: add basic support for nucleo-l073rz configs: add basic support for b-l072z-lrwan1
2018-12-19 19:36:35 +01:00
CONFIG_SYSTEM_NSH=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536
CONFIG_USART2_SERIAL_CONSOLE=y
CONFIG_USERMAIN_STACKSIZE=1536
CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_WDOG_INTRESERVE=0
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