60 lines
2.6 KiB
Plaintext
60 lines
2.6 KiB
Plaintext
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/****************************************************************************
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* configs/pnev5180b/scripts/memory.ld
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*
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* Copyright (C) 2019 Gregory Nutt. All rights reserved.
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* Author: Michael Jung <mijung@gmx.net>
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*
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* Based on configs/open1788/scripts/memory.ld
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/* The LPC1769 has 512Kb of FLASH beginning at address 0x0000:0000 and
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* 64Kb of total SRAM: 32Kb of SRAM in the CPU block beginning at address
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* 0x10000000 and 32Kb of AHB SRAM in two banks of 16Kb beginning at addresses
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* 0x20070000 and 0x20080000. Here we assume that .data and .bss will all fit
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* into the 32Kb CPU SRAM address range.
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*/
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MEMORY
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{
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/* 512Kb FLASH - Leave 256Kb for application usage */
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kflash (rx) : ORIGIN = 0x00000000, LENGTH = 128K
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uflash (rx) : ORIGIN = 0x00020000, LENGTH = 128K
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/* 32Kb of SRAM in the CPU block - Leave 32Kb of AHB SRAM for app usage */
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ksram (rwx) : ORIGIN = 0x10000000, LENGTH = 16K
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usram (rwx) : ORIGIN = 0x10004000, LENGTH = 16K
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}
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