2019-08-13 18:08:49 +02:00
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/****************************************************************************
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* boards/arm/lpc17xx_40xx/u-blox-c027/include/board.h
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2016-01-31 15:49:30 +01:00
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*
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* Copyright (C) 2016 Vladimir Komendantskiy. All rights reserved.
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* Author: Vladimir Komendantskiy <vladimir@moixaenergy.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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2019-08-13 18:08:49 +02:00
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****************************************************************************/
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2016-01-31 15:49:30 +01:00
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2019-08-13 18:08:49 +02:00
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#ifndef __BOARDS_ARM_LPC17XX_40XX_U_BLOX_C027_INCLUDE_BOARD_H
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#define __BOARDS_ARM_LPC17XX_40XX_U_BLOX_C027_INCLUDE_BOARD_H
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2016-01-31 15:49:30 +01:00
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2019-08-13 18:08:49 +02:00
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/****************************************************************************
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2016-01-31 15:49:30 +01:00
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* Included Files
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2019-08-13 18:08:49 +02:00
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****************************************************************************/
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2016-01-31 15:49:30 +01:00
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#include <nuttx/config.h>
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2019-08-13 18:08:49 +02:00
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/****************************************************************************
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2016-01-31 15:49:30 +01:00
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* Pre-processor Definitions
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2019-08-13 18:08:49 +02:00
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****************************************************************************/
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2016-01-31 15:49:30 +01:00
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2019-08-13 18:08:49 +02:00
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/* Clocking *****************************************************************/
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/* NOTE:
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* The following definitions require lpc17_40_syscon.h.
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* It is not included here because the including C file may not have that
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* file in its include path.
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2016-01-31 15:49:30 +01:00
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*/
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#define BOARD_XTAL_FREQUENCY (12000000) /* XTAL oscillator frequency */
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#define BOARD_OSCCLK_FREQUENCY BOARD_XTAL_FREQUENCY /* Main oscillator frequency */
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#define BOARD_RTCCLK_FREQUENCY (32768) /* RTC oscillator frequency */
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#define BOARD_INTRCOSC_FREQUENCY (4000000) /* Internal RC oscillator frequency */
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/* This is the clock setup we configure for:
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*
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2019-08-13 18:08:49 +02:00
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* SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz -> Select Main oscillator for source
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* PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz -> PLL0 multipler=20, pre-divider=1
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* CCLCK = 480MHz / 6 = 80MHz -> CCLK divider = 6
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2016-01-31 15:49:30 +01:00
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*/
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2019-07-11 18:50:00 +02:00
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#define LPC17_40_CCLK 80000000 /* 80Mhz */
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2016-01-31 15:49:30 +01:00
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2019-08-13 18:08:49 +02:00
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/* Select the main oscillator as the frequency source.
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* SYSCLK is then the frequency of the main oscillator.
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2016-01-31 15:49:30 +01:00
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*/
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2019-07-11 18:50:00 +02:00
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#undef CONFIG_LPC17_40_MAINOSC
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#define CONFIG_LPC17_40_MAINOSC 1
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2016-01-31 15:49:30 +01:00
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#define BOARD_SCS_VALUE SYSCON_SCS_OSCEN
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2019-08-13 18:08:49 +02:00
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/* Select the main oscillator and CCLK divider.
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* The output of the divider is CCLK.
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2016-01-31 15:49:30 +01:00
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* The input to the divider (PLLCLK) will be determined by the PLL output.
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*/
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#define BOARD_CCLKCFG_DIVIDER 6
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#define BOARD_CCLKCFG_VALUE ((BOARD_CCLKCFG_DIVIDER-1) << SYSCON_CCLKCFG_SHIFT)
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2019-08-13 18:08:49 +02:00
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/* PLL0.
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* PLL0 is used to generate the CPU clock divider input (PLLCLK).
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2016-01-31 15:49:30 +01:00
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*
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* Source clock: Main oscillator
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* PLL0 Multiplier value (M): 20
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* PLL0 Pre-divider value (N): 1
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*
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* PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz
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*/
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2019-07-11 18:50:00 +02:00
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#undef CONFIG_LPC17_40_PLL0
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#define CONFIG_LPC17_40_PLL0 1
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2016-01-31 15:49:30 +01:00
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#define BOARD_CLKSRCSEL_VALUE SYSCON_CLKSRCSEL_MAIN
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#define BOARD_PLL0CFG_MSEL 20
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#define BOARD_PLL0CFG_NSEL 1
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#define BOARD_PLL0CFG_VALUE \
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(((BOARD_PLL0CFG_MSEL-1) << SYSCON_PLL0CFG_MSEL_SHIFT) | \
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((BOARD_PLL0CFG_NSEL-1) << SYSCON_PLL0CFG_NSEL_SHIFT))
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/* PLL1 -- Not used. */
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2019-07-11 18:50:00 +02:00
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#undef CONFIG_LPC17_40_PLL1
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2016-01-31 15:49:30 +01:00
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#define BOARD_PLL1CFG_MSEL 36
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#define BOARD_PLL1CFG_NSEL 1
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#define BOARD_PLL1CFG_VALUE \
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(((BOARD_PLL1CFG_MSEL-1) << SYSCON_PLL1CFG_MSEL_SHIFT) | \
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((BOARD_PLL1CFG_NSEL-1) << SYSCON_PLL1CFG_NSEL_SHIFT))
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2019-08-13 18:08:49 +02:00
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/* USB divider.
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* This divider is used when PLL1 is not enabled to get the
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2016-01-31 15:49:30 +01:00
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* USB clock from PLL0:
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*
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* USBCLK = PLL0CLK / 10 = 48MHz
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*/
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#define BOARD_USBCLKCFG_VALUE SYSCON_USBCLKCFG_DIV10
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/* FLASH Configuration */
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2019-07-11 18:50:00 +02:00
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#undef CONFIG_LPC17_40_FLASH
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#define CONFIG_LPC17_40_FLASH 1
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2016-01-31 15:49:30 +01:00
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#define BOARD_FLASHCFG_VALUE 0x0000303a
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/* Ethernet configuration */
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#define ETH_MCFG_CLKSEL_DIV ETH_MCFG_CLKSEL_DIV20
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2019-08-13 18:08:49 +02:00
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/* u-blox C027 board pin usage **********************************************/
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2016-01-31 15:49:30 +01:00
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/* Pin Description Connector On Board
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* -------------------------------- --------- --------------
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* P0[0]/RD1/TXD3/SDA1 D14 TXD3/SDA1
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* P0[1]/TD1/RXD3/SCL1 D15 RXD3/SCL1
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* P0[2]/TXD0/AD0[7] USBTXD
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* P0[3]/RXD0/AD0[6] USBRXD
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* P0[4]/I2SRX-CLK/RD2/CAP2.0 CANRD CAN_RX2
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* P0[5]/I2SRX-WS/TD2/CAP2.1 CANTD CAN_TX2
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* P0[6]/I2SRX_SDA/SSEL1/MAT2[0] CANS SSEL1
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* P0[7]/I2STX_CLK/SCK1/MAT2[1] MDMUSBDET
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* P0[8]/I2STX_WS/MISO1/MAT2[2] MDMLVLOE
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* P0[9]/I2STX_SDA/MOSI1/MAT2[3] MDMILVLOE
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* P0[10]/TXD2/SDA2 GPSTXD
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* P0[11]/RXD2/SCL2 GPSRXD
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* P0[15]/TXD1/SCK0/SCK MDMTXD
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* P0[16]/RXD1/SSEL0/SSEL MDMRXD
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* P0[17]/CTS1/MISO0/MISO MDMCTS
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* P0[18]/DCD1/MOSI0/MOSI MDMDCD
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* P0[19]/DSR1/SDA1 MDMDCR
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* P0[20]/DTR1/SCL1 MDMDTR
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* P0[21]/RI1/MCIPWR/RD1 MDMRI
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* P0[22]/RTS1/TD1 MDMRTS
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* P0[23]/AD0[0]/I2SRX_CLK/CAP3[0] A0 I2S_CLK
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* P0[24]/AD0[1]/I2SRX_WS/CAP3[1] A1 I2S_WS
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* P0[25]/AD0[2]/I2SRX_SDA/TXD3 A2 I2S_SDA
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* P0[26]/AD0[3]/AOUT/RXD3 A3 AD0.3/AOUT
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* P0[27]/SDA0/USB_SDA GPSSDA
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* P0[28]/SCL0 GPSSCL
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* P0[29]/USB_D+ MDMUSBDP
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* P0[30]/USB_D- MDMUSBDM
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*
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* P1[0]/ENET_TXD0 ENET_TXD0
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* P1[1]/ENET_TXD1 ENET_TXD1
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* P1[4]/ENET_TX_EN ENET_TX_EN
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* P1[8]/ENET_CRS ENET_CRS
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* P1[9]/ENET_RXD0 ENET_RXD0
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* P1[10]/ENET_RXD1 ENET_RXD1
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* P1[14]/ENET_RX_ER ENET_RX_ER
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* P1[15]/ENET_REF_CLK ENET_REF_CLK
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* P1[16]/ENET_MDC ENET_MDC
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* P1[17]/ENET_MDIO ENET_MDIO
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* P1[18]/USB_UP_LED/PWM1[1]/CAP1[0] GPSRST
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* P1[19]/MC0A/USB_PPWR/N_CAP1.1 GPSPPS
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* P1[20]/MCFB0/PWM1.2/SCK0 D13 PWM1.2/SCK0
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* P1[21]/MCABORT/PWM1.3/SSEL0 D10 PWM1.3/SSEL0
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* P1[22]/MC0B/USB-PWRD/MAT1.0 GPSINT
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* P1[23]/MCFB1/PWM1.4/MISO0 D12 PWM1.4/MISO0
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* P1[24]/MCFB2/PWM1.5/MOSI0 D11 PWM1.5/MOSI0
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* P1[25]/MC1A/MAT1.1 ETH_LED_LNK
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* P1[26]/MC1B/PWM1.6/CAP0.0 ETH_LED_SPD
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* P1[27]/CLKOUT/USB-OVRCR-N/CAP0.1 ETH_OSC_EN
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* P1[28]/MC2A/PCAP1.0/MAT0.0 ETH_RST
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* P1[29]/MC2B/PCAP1.1/MAT0.1 GPSEN
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* P1[30]/VBUS/AD0[4] A4 AD0.4
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* P1[31]/SCK1/AD0[5] A5 AD0.5
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*
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* P2[0]/PWM1.1/TXD1 D3 PWM1.1
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* P2[1]/PWM1.2/RXD1 D5 PWM1.2
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* P2[2]/PWM1.3/CTS1/TRACEDATA[3] D6 PWM1.3
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* P2[3]/PWM1.4/DCD1/TRACEDATA[2] D9 PWM1.4
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* P2[4]/PWM1.5/DSR1/TRACEDATA[1] D8 PWM1.5
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* P2[5]/PWM1[6]/DTR1/TRACEDATA[0] MDMEN
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* P2[6]/PCAP1[0]/RI1/TRACECLK MDMPWRON
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* P2[7]/RD2/RTS1 MDMGPIO1
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* P2[8]/TD2/TXD2 MDMRST
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* P2[9]/USB_CONNECT/RXD2 MDMUSBCON
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* P2[10]/EINT0/NMI ISP_PAD
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* P2[11]/EINT1/I2STX_CLK D7 EINT1
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* P2[12]/EINT2/I2STX_WS D4 EINT2
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* P2[13]/EINT3/I2STX_SDA D2 EINT3
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*
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* P3[25]/MAT0.0/PWM1.2 LED
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*
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* P4[28]/RX-MCLK/MAT2.0/TXD3 D0 TXD3
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* P4[29]/TX-MCLK/MAT2.1/RXD3 D1 RXD3
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*/
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2019-08-13 18:08:49 +02:00
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/* LED definitions **********************************************************/
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/* The u-blox C027 board has a single red LED
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* (there are additional LEDs on the base board not considered here).
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2016-01-31 15:49:30 +01:00
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*/
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/* ON OFF */
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#define LED_STARTED 0 /* OFF ON (never happens) */
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#define LED_HEAPALLOCATE 0 /* OFF ON (never happens) */
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#define LED_IRQSENABLED 0 /* OFF ON (never happens) */
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#define LED_STACKCREATED 1 /* ON ON (never happens) */
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#define LED_INIRQ 2 /* OFF NC (momentary) */
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#define LED_SIGNAL 2 /* OFF NC (momentary) */
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#define LED_ASSERTION 2 /* OFF NC (momentary) */
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#define LED_PANIC 0 /* OFF ON (1Hz flashing) */
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#define GPIO_I2C1_SDA GPIO_I2C1_SDA_1
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#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
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#define GPIO_SSP1_SCK GPIO_SSP1_SCK_1
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#define GPIO_SSP0_SCK GPIO_SSP0_SCK_1
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#define GPIO_SSP0_SSEL GPIO_SSP0_SSEL_1
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#define GPIO_SSP0_MISO GPIO_SSP0_MISO_1
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#define GPIO_SSP0_MOSI GPIO_SSP0_MOSI_1
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#define GPIO_UART1_TXD GPIO_UART1_TXD_1
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#define GPIO_UART1_RXD GPIO_UART1_RXD_1
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#define GPIO_UART1_CTS GPIO_UART1_CTS_1
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#define GPIO_UART1_RTS GPIO_UART1_RTS_1
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#define GPIO_UART1_DCD GPIO_UART1_DCD_1
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#define GPIO_UART1_DSR GPIO_UART1_DSR_1
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#define GPIO_UART1_DTR GPIO_UART1_DTR_1
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#define GPIO_UART1_RI GPIO_UART1_RI_1
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#define GPIO_UART2_TXD GPIO_UART2_TXD_1
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#define GPIO_UART2_RXD GPIO_UART2_RXD_1
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#define GPIO_UART3_TXD GPIO_UART3_TXD_3
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#define GPIO_UART3_RXD GPIO_UART3_RXD_3
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#define GPIO_ENET_MDC GPIO_ENET_MDC_1
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#define GPIO_ENET_MDIO GPIO_ENET_MDIO_1
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#define GPIO_PWM1p1 GPIO_PWM1p1_2
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#define GPIO_PWM1p2 GPIO_PWM1p2_2
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#define GPIO_PWM1p3 GPIO_PWM1p3_2
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#define GPIO_PWM1p4 GPIO_PWM1p4_2
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#define GPIO_PWM1p5 GPIO_PWM1p5_2
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#define GPIO_PWM1p6 GPIO_PWM1p6_2
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2020-01-31 19:07:39 +01:00
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#endif /* __BOARDS_ARM_LPC17XX_40XX_U_BLOX_C027_INCLUDE_BOARD_H */
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