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nuttx/boards/arm/stm32/stm32f411-minimum/include/board.h

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Add initial support to STM32F411-Minimum board (aka BlackPill)
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/****************************************************************************
* boards/arm/stm32/stm32f411-minimum/include/board.h
*
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* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
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*
****************************************************************************/
#ifndef __BOARDS_ARM_STM32_STM32F411_MINIMUM_INCLUDE_BOARD_H
#define __BOARDS_ARM_STM32_STM32F411_MINIMUM_INCLUDE_BOARD_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
#include <stm32.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
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/* Clocking *****************************************************************/
/* System Clock source : PLLCLK (HSE)
* SYSCLK(Hz) : 96000000 Determined by PLL config
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* HCLK(Hz) : 96000000 (STM32_RCC_CFGR_HPRE)
* AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE)
* APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1)
* APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2)
* HSI Frequency(Hz) : 16000000 (nominal)
* PLLM : 4 (STM32_PLLCFG_PLLM)
* PLLN : 192 (STM32_PLLCFG_PLLN)
* PLLP : 4 (STM32_PLLCFG_PLLP)
* PLLQ : 8 (STM32_PLLCFG_PPQ)
* Flash Latency(WS) : 3
* Prefetch Buffer : OFF
* Instruction cache : ON
* Data cache : ON
* Require 48MHz for USB OTG FS, : Enabled
* SDIO and RNG clock
*/
/* HSI - 16 MHz RC factory-trimmed
* LSI - 32 KHz RC
* HSE - 25 MHz Crystal
* LSE - 32 KHz Crystal
*/
#define STM32_BOARD_XTAL 25000000ul
#define STM32_HSI_FREQUENCY 16000000ul
#define STM32_LSI_FREQUENCY 32000
#define STM32_LSE_FREQUENCY 32768
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
/* Main PLL Configuration.
*
* Formulae:
*
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* VCO input freq = PLL input clock freq/PLLM 2 <= PLLM <= 63
* VCO output freq = VCO input freq × PLLN, 192 <= PLLN <= 432
* PLL output clock freq = VCO freq / PLLP, PLLP = 2,4,6 or 8
* USB OTG FS clock freq = VCO freq / PLLQ, 2 <= PLLQ <= 15
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*
* There is no config for 100 MHz and 48 MHz for usb,
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* so we would like to have SYSYCLK=96MHz and we must have the USB
* clock = 48MHz
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*
* PLLQ = 2 PLLP = 2 PLLN=192 PLLM=25
*
* We will configure like this
*
* PLL source is HSE
* PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
* = (25,000,000 / 25) * 192
* = 192,000,000
* SYSCLK = PLL_VCO / PLLP
* = 192,000,000 / 2 = 96,000,000
* USB OTG FS and SDIO Clock
* = PLL_VCO / PLLQ
* = 96,000,000 / 2 = 48,000,000
*/
#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25)
#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(192)
#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(2)
#define STM32_SYSCLK_FREQUENCY 96000000ul
/* AHB clock (HCLK) is SYSCLK (96MHz) */
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK/4 (24MHz) */
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
/* Timers driven from APB1 will be twice PCLK1 */
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/* REVISIT */
#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
/* APB2 clock (PCLK2) is HCLK (48MHz) */
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
/* Timers driven from APB2 will be twice PCLK2 */
#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY)
/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
* otherwise frequency is 2xAPBx.
* Note: TIM1,8 are on APB2, others on APB1
*/
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/* REVISIT */
#define BOARD_TIM1_FREQUENCY (2 * STM32_PCLK2_FREQUENCY)
#define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
#define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
#define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
#define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
#define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
#define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
#define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY)
/* SDIO dividers. Note that slower clocking is required when DMA is disabled
* in order to avoid RX overrun/TX underrun errors due to delayed responses
* to service FIFOs in interrupt driven mode. These values have not been
* tuned!!!
*
* HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz
*/
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/* REVISIT */
#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT)
/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz
* DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz
*/
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/* REVISIT */
#ifdef CONFIG_SDIO_DMA
# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
#else
# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT)
#endif
/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz
* DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz
*/
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/* REVISIT */
#ifdef CONFIG_SDIO_DMA
# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
#else
# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT)
#endif
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/* DMA Channel/Stream Selections ********************************************/
/* Stream selections are arbitrary for now but might become important in the
* future is we set aside more DMA channels/streams.
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*
* SDIO DMA
*   DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA
*   DMAMAP_SDIO_2 = Channel 4, Stream 6
*/
#define DMAMAP_SDIO DMAMAP_SDIO_1
/* Need to VERIFY fwb */
#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1
#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1
#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX
#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX
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/* Alternate function pin selections ****************************************/
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/* USART1:
* RXD: PA10 CN9 pin 3, CN10 pin 33
* PB7 CN7 pin 21
* TXD: PA9 CN5 pin 1, CN10 pin 21
* PB6 CN5 pin 3, CN10 pin 17
*/
#if 1
# define GPIO_USART1_RX GPIO_USART1_RX_1 /* PA10 */
# define GPIO_USART1_TX GPIO_USART1_TX_1 /* PA9 */
#else
# define GPIO_USART1_RX GPIO_USART1_RX_2 /* PB7 */
# define GPIO_USART1_TX GPIO_USART1_TX_2 /* PB6 */
#endif
/* USART2:
* RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37
* PD6
* TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35
* PD5
*/
#define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */
#define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA2 */
#define GPIO_USART2_RTS GPIO_USART2_RTS_2
#define GPIO_USART2_CTS GPIO_USART2_CTS_2
/* USART6:
* RXD: PC7 CN5 pin2, CN10 pin 19
* PA12 CN10, pin 12
* TXD: PC6 CN10, pin 4
* PA11 CN10, pin 14
*/
#define GPIO_USART6_RX GPIO_USART6_RX_1 /* PC7 */
#define GPIO_USART6_TX GPIO_USART6_TX_1 /* PC6 */
/* UART RX DMA configurations */
#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2
#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2
/* I2C
*
* The optional _GPIO configurations allow the I2C driver to manually
* reset the bus to clear stuck slaves. They match the pin configuration,
* but are normally-high GPIOs.
*/
#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2
#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2
#define GPIO_I2C1_SCL_GPIO \
(GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8)
#define GPIO_I2C1_SDA_GPIO \
(GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9)
#define GPIO_I2C2_SCL GPIO_I2C2_SCL_1
#define GPIO_I2C2_SDA GPIO_I2C2_SDA_1
#define GPIO_I2C2_SCL_GPIO \
(GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN10)
#define GPIO_I2C2_SDA_GPIO \
(GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN11)
/* SPI
*
* There are sensors on SPI1, and SPI2 is connected to the FRAM.
*/
#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1
#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1
#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1
#define GPIO_SPI2_MISO GPIO_SPI2_MISO_1
#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1
#define GPIO_SPI2_SCK GPIO_SPI2_SCK_2
/* LEDs
*
* The STM32F411-Minimum (aka BlackPill) has a LED on PC13 pin.
*/
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/* The board has only one controllable LED */
#define LED_STARTED 0 /* No LEDs */
#define LED_HEAPALLOCATE 1 /* LED1 on */
#define LED_IRQSENABLED 2 /* LED1 on */
#define LED_STACKCREATED 3 /* LED1 on */
#define LED_INIRQ 4 /* LED1 on */
#define LED_SIGNAL 5 /* LED1 on */
#define LED_ASSERTION 6 /* LED1 on */
#define LED_PANIC 7 /* LED1 blinking */
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/* LED index values for use with board_userled() */
#define BOARD_LED1 0
#define BOARD_NLEDS 1
/* LED bits for use with board_userled_all() */
#define BOARD_LED1_BIT (1 << BOARD_LED1)
/* Buttons
*
* B1 USER: the user button is connected to the I/O PA0 of the STM32
* microcontroller.
*/
#define BUTTON_USER 0
#define NUM_BUTTONS 1
#define BUTTON_USER_BIT (1 << BUTTON_USER)
#endif /* __BOARDS_ARM_STM32_STM32F411_MINIMUM_INCLUDE_BOARD_H */
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